Design of a SET Based 4bit ALU Using Proteus
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23/09/19 Mechanics Reference this
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Table of Contents
2.1Design of a 3bit ALU using Proteus: A case study
2.3 Design of a 4bit ALU using Proteus
2.3.1 Operation table for a 4bit ALU
List of Figures
Figure 1: Basic Components of an Electronic Gates
Figure 2: Description of the shift and add algorithm
Figure 3: The Schematic diagram of a 4X1 Multiplexer
Figure 4: The Display page of a 3Bit ALU
Figure 5: A typical Adder/Subtractor Circuit
Figure 6: Simulation of a full adder in proteus
Figure 7: Simulation of an adder/subtractor circuit in Proteus
Figure 8: Simulation of a 4Bit Comparator in proteus
List of Tables
Table 1: The truthtable of a 4bit ALU
Table 2: The truthtable of a full adder
Table 3: The Truthtable implementing a subtractor circuit
Table 4: The truthtable for a 4bit comparator
Abstract
Single Electron Transistor (SET) is a lowpowered Nano device and as such it requires some sort of optimization at all levels to achieve a highend performance. This paper will be presenting the design of a SET based 4bit ALU using Proteus in view of its excellent potential for future Ultra Large Scale Integrated (ULSI) Circuits. The basic circuits required for this design such as Adder, multiplier and Comparator circuits will be designed & simulated using Proteus. However, the proposed logic design model is encouragingly operational at room temperature.
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Find out moreConversely, the SETbased ALU will be designed, simulated and optimized with incorporation of necessary and sufficient parameters in the feasible fabrication range in a hierarchical manner. It is expected that after simulation and design, we would be able to corroborate that a SETbased ALU is more efficient than CMOSbased ALU or its derivatives in terms of power consumption, delay and effectiveness. The analyses of the result could be performed if possible at 45nm technology node using Cadence EDA tool and of course, performancebased comparisons will be made with CMOSbased ALUs at percentages based on different parameters considered.
1.0 Introduction
The exponential increase in the density of integrated circuits predicted by Moore’s law has been mainly driven by reducing the dimensions of the semiconductor devices comprising these circuits. However, as semiconductor feature sizes shrink into the nanometer scale regime, device behavior becomes increasingly problematic as new physical phenomena at short dimensions occur, and limitations in material properties are reached. In effect, the SET technology circumvented the attendant problems common with CMOS technology which borders on speed and performance.
SETs are promising building blocks for future highdensity and lowpowered integrated circuits. In this paper, a SETbased 4bit Arithmetic and Logic Unit (ALU) is discussed with necessary functionalities. Essentially, paper formulation is as follows: Section 2 talks about the design and simulation of a 4bit ALU in details. Section 3 provides simulation results and section 4 is conclusion.
1.1 Single Electron Transistors (SETs)
A singleelectron transistor (SET) is a sensitive electronic device based on the Coulomb blockade effect. In this device the electron flows through a tunnel junction between source/drain to a quantum dot (conductive island). Moreover, the electrical potential of the island can be tuned by a third electrode, known as the gate, which is capacitively coupled to the island. Figure 1 Below shows the basic schematic of a SET device. The conductive island is sandwiched between two tunnel junctions,[1] which are modeled by a capacitance (C_{D} and C_{S}) and a resistor (R_{D} and R_{S}) in parallel. (Source: Wikipedia).
Figure 1: The Basic Schematic of a SET device
The SET operates mainly as a switch and the fact that SETs may exhibit negative transconductance which allows the implementation of complementary circuits using transistors of a single type.
2.0 Design Methodology
2.1Design of a 3bit ALU using Proteus: A case study
An ALU is a combinational logic circuit, meaning that its outputs will change asynchronously in response to input changes.
2.2Basic components
As a case study, I designed a 3bit ALU to be able to explain a more complex 4bit ALU. Basically, an ALU is made up of: an arithmetic and logic units. However, the basic components used to develop this sub units are electronic gates such as AND gate, OR gate, XOR gate, XNOR gate and the NOT gate. The truth table and circuit symbol of the aforementioned gates are shown below:
Figure 2: Basic Components of an Electronic Gates
More importantly, a typical ALU has sub circuitry in the child sheet of the design. It include the Addition/Subtractor, Array Multiplier, multiplexer and Logic unit blocks. This paper briefly explain all the subblock in the child’s sheet of the design.
2.2.1 Adder/Subtractor Block
In digital circuits, an adderSubtractor block is a circuit that is capable of adding or subtracting numbers in a binary system under the influence of a control signal (either 0 or 1).
2.2.2 Array Multiplier
Array multiplier is well known due to its regular structure. Multiplier circuit is based on add and shift algorithm. Each partial product is generated by the multiplication of the multiplicand with one multiplier bit. The partial product are shifted according to their bit orders and then added.
Figure 3: Description of the shift and add algorithm
2.2.3 Multiplexers
Multiplexer is a combinational circuit that has maximum of 2^{n} data inputs, ‘n’ selection lines and single output line. One of these data inputs will be connected to the output based on the values of selection lines. Since there are ‘n’ selection lines, there will be 2^{n} possible combinations of zeros and ones. So, each combination will select only one data input. Multiplexer is also called as Mux.
Figure 4: The Schematic diagram of a 4X1 Multiplexer
One of these 4 inputs will be connected to the output based on the combination of inputs present at these two selection lines. Truth table of 4×1 Multiplexer is shown below.
Selection Lines 
Output 

${\textcolor[rgb]{}{\mathit{S}}}_{\textcolor[rgb]{}{\mathit{0}}}$ 
${\textcolor[rgb]{}{\mathit{S}}}_{\textcolor[rgb]{}{\mathit{1}}}$ 
$\textcolor[rgb]{}{\mathit{Y}}$ 
0 
0 
${\textcolor[rgb]{}{I}}_{\textcolor[rgb]{}{0}}$ 
0 
1 
${\textcolor[rgb]{}{I}}_{\textcolor[rgb]{}{1}}$ 
1 
0 
${\textcolor[rgb]{}{I}}_{\textcolor[rgb]{}{2}}$ 
1 
1 
${\textcolor[rgb]{}{I}}_{\textcolor[rgb]{}{3}}$ 
From Truth table, we can directly write the Boolean function for output, Y as:
$Y={I}_{0}\stackrel{\u0305}{{S}_{0}}\stackrel{\u0305}{{S}_{1}}+{I}_{1}\stackrel{\u0305}{{S}_{0}}{S}_{1}+{I}_{2}{S}_{0}\stackrel{\u0305}{{S}_{1}}+{I}_{3}{S}_{0}{S}_{1}$
The design interface of a 3bit ALU is shown below which is able to perform addition, subtraction, multiplication and shifting operation. The picture below is just the parent sheet of the design. In the appendices section, this paper will show the full circuit.
Figure 5: The Display page of a 3Bit ALU
2.3 Design of a 4bit ALU using Proteus
Arithmetic and Logic Unit (ALU) is made of Arithmetic and Logic Units. This paper considers and designed subblocks such as Adder/subtraction block, 4bit multiplier, Magnitude Comparator and Multiplexers using Proteus.
2.3.1 Operation table for a 4bit ALU
Table 1: The truthtable of a 4bit ALU
Inputs 

${S}_{2}$ 
${S}_{1}$ 
${S}_{0}$ 
${C}_{\mathit{in}}$ 
$\mathit{Function}$ 
$\mathit{Output}$ Width 
0 
0 
0 
0 
Addition 
5bit 
0 
0 
0 
1 
Subtraction 
4bit 
0 
0 
1 
0 
Multiplier 
8bit 
0 
0 
1 
1 
Magnitude Comparator 
3bit 
0 
1 
0 
0 
Logical Left Shifter 
4bit 
0 
1 
0 
1 
Logical Right Shifter 
4bit 
0 
1 
1 
0 
Right Rotator 
4bit 
0 
1 
1` 
1 
Left Rotator 
4bit 
1 
0 
0 
0 
Bitwise Inversion 
4bit 
1 
0 
0 
1 
Bitwise AND 
4bit 
1 
0 
1 
0 
Bitwise OR 
4bit 
1 
0 
1 
1 
Bitwise XOR 
4bit 
1 
1 
0 
0 

1 
1 
0 
1 

1 
1 
1 
0 

1 
1 
1 
1 
2.3.2Adder/Subtractor block
The logical gates discussed so far can be used for performing arithmetical functions like addition,
Subtraction, multiplication and division in electronic calculators and digital instruments. In the
Central processing unit (CPU) of a computer, these arithmetic functions are carried out by the
Arithmetic and Logic Unit (ALU). The logic functions used generally are AND, XOR and OR gates. A typical adder/ Subtractor which is implemented using logic gates is shown below.
Figure 6: A typical Adder/Subtractor Circuit
2.3.2.1 Full Adder
A full adder has three inputs and two outputs.It can add 3 digits (or bits) at a time. The bits A and B which are to be added come from the two registers and the third input comes from the carry generated by the previous addition. It produces two outputs; Sum and Carryout. The truth table is shown below:
Table 2: The truthtable of a full adder
Input 
Output 

A 
B 
Cin 
Sum 
Carryout 
0 
0 
0 
0 
0 
0 
0 
1 
1 
0 
0 
1 
0 
1 
0 
0 
1 
1 
0 
1 
1 
0 
0 
1 
0 
1 
0 
1 
0 
1 
1 
1 
0 
0 
1 
1 
1 
1 
1 
1 
The resulting Boolean expression:
$\mathit{Sum},\mathit{S}=\left(\mathit{A}\stackrel{\u0305}{\mathit{\theta}}B\right)\stackrel{\u0305}{\mathit{\theta}}\mathit{Cin\; and\; Carry}\u2013\mathit{out}=(A\bullet B)+(\mathit{Cin}\bullet (\mathit{A}\stackrel{\u0305}{\mathit{\theta}}B\left)\right)$. The logic diagram of a FULL Adder is shown below.
Figure 7: Simulation of a full adder in proteus
2.3.2.2 Subtractor
This paper implements a subtractor circuit using the 2’s complement. For instance;
Table 3: The Truthtable implementing a subtractor circuit
A 
B 
Output (Y) 
0 
0 
0 
0 
1 
1 
1 
0 
1 
1 
1 
0 
When
$\mathit{A}=0,\mathit{Y}=\mathit{B}$and when
$\mathit{A}=1,\mathit{Y}=\stackrel{\u0305}{B}$. Therefore, the Adder/Subtractor circuit is shown below:
Figure 8: Simulation of an adder/subtractor circuit in Proteus
2.3.3 4Bit Comparator
Table 4: The truthtable for a 4bit comparator
${\mathit{A}}_{\mathit{2}}$ 
${\mathit{A}}_{\mathit{1}}$ 
${\mathit{B}}_{\mathit{2}}$ 
${\mathit{B}}_{\mathit{1}}$ 
$\mathit{A}\mathit{>}\mathit{B}$ 
$\mathit{A}\mathit{=}\mathit{B}$ 
$\mathit{A}\mathit{<}\mathit{B}$ 
0 
0 
0 
0 
0 
1 
0 
0 
0 
0 
1 
0 
0 
1 
0 
0 
1 
0 
0 
0 
1 
0 
0 
1 
1 
0 
0 
1 
0 
1 
0 
0 
1 
0 
0 
0 
1 
0 
1 
0 
1 
0 
0 
1 
1 
0 
0 
0 
1 
0 
1 
1 
1 
0 
0 
1 
1 
0 
0 
0 
1 
0 
0 
1 
0 
0 
1 
1 
0 
0 
1 
0 
1 
0 
0 
1 
0 
1 
0 
1 
1 
0 
0 
1 
1 
1 
0 
0 
1 
0 
0 
1 
1 
0 
1 
1 
0 
0 
1 
1 
1 
0 
1 
0 
0 
1 
1 
1 
1 
0 
1 
0 
 Equality Relationship ( A=B)
${X}_{1}=1\mathit{if}{A}_{i}={B}_{i}\mathit{for\; i}=0,1,2,3$
$\therefore \mathit{If}{A}_{3}={B}_{3}\mathit{and}{A}_{2}={B}_{2}\mathit{and}{A}_{1}={B}_{1}\mathit{and}{A}_{0}={B}_{0}.\mathit{Then},{X}_{3}={X}_{2}={X}_{1}={X}_{0}=1$
. In essence, the equality Condition is satisfied when EQ = 1.
 Greater than relationship (if $\mathit{A}\mathit{}\mathit{B}\mathit{)}$
This condition exist:
$\mathit{If}{A}_{3}{B}_{3}\to \mathit{}{A}_{3}=1\mathit{and}{B}_{3}=0$
$\mathit{OR}$ $\mathit{If}{A}_{3}={B}_{3}\mathit{and}{A}_{2}{B}_{2}\to \mathit{}{A}_{2}=1\mathit{and}{B}_{2}=0\mathit{OR\; If}{A}_{3}={B}_{3},{\mathit{A}}_{2}={B}_{2}\mathit{and}{A}_{1}{B}_{1}\to \mathit{}{A}_{1}=1\mathit{and}{B}_{1}=0\mathit{OR\; If}{A}_{3}={B}_{3},{\mathit{A}}_{2}={B}_{2},\mathit{and}{A}_{1}={B}_{1},\mathit{}{A}_{0}{B}_{0}\to \mathit{}{A}_{0}=1\mathit{and}{B}_{0}=0$
Greater Than (GT) =
${A}_{3}\stackrel{\u0305}{{B}_{3}}+{X}_{3}{A}_{2}\stackrel{\u0305}{{B}_{2}}+{X}_{3}{X}_{2}{A}_{1}\stackrel{\u0305}{{B}_{1}}+{X}_{3}{X}_{2}{X}_{1}{A}_{0}\stackrel{\u0305}{{B}_{0}}$ Less than Relationship (LT=1 if A<B)
This condition exist:
$\mathit{If}{A}_{3}{B}_{3}\to \mathit{}{A}_{3}=0\mathit{and}{B}_{3}=1$
$\mathit{OR}$ $\mathit{If}{A}_{3}={B}_{3}\mathit{and}{A}_{2}={B}_{2}\to \mathit{}{A}_{2}=0\mathit{and}{B}_{2}=1\mathit{OR\; If}{A}_{3}={B}_{3},{\mathit{A}}_{2}={B}_{2}\mathit{and}{A}_{1}{B}_{1}\to \mathit{}{A}_{1}=0\mathit{and}{B}_{1}=1\mathit{OR\; If}{A}_{3}={B}_{3},{\mathit{A}}_{2}={B}_{2},\mathit{and}{A}_{1}={B}_{1},\mathit{}{A}_{0}{B}_{0}\to \mathit{}{A}_{0}=0\mathit{and}{B}_{0}=1$
Less Than (LT) =
$\stackrel{\u0305}{{A}_{3}}{B}_{3}+{X}_{3}\stackrel{\u0305}{{A}_{2}}{B}_{2}+{X}_{3}{X}_{2}\stackrel{\u0305}{{A}_{1}}{B}_{1}+{X}_{3}{X}_{2}{X}_{1}\stackrel{\u0305}{{A}_{0}}{B}_{0}$Using Karnaugh map to simplify the greater than, less than and equal to relationship.
For A>B
${y}_{1}=\stackrel{\u0305}{{A}_{2}}{A}_{1}\stackrel{\u0305}{{B}_{2}}\stackrel{\u0305}{{B}_{1}}+{A}_{2}\stackrel{\u0305}{{A}_{1}}\stackrel{\u0305}{{B}_{2}}\stackrel{\u0305}{{B}_{1}}+{A}_{2}\stackrel{\u0305}{{A}_{1}}\stackrel{\u0305}{{B}_{2}}{B}_{1}+{A}_{2}{A}_{1}\stackrel{\u0305}{{B}_{2}}\stackrel{\u0305}{{B}_{1}}+{A}_{2}{A}_{1}\stackrel{\u0305}{{B}_{2}}{B}_{1}+{A}_{2}{A}_{1}{B}_{2}\stackrel{\u0305}{{B}_{1}}$
${y}_{1}=\stackrel{\u0305}{{B}_{2}}{A}_{2}+\stackrel{\u0305}{{B}_{1}}{A}_{2}{A}_{1}+\stackrel{\u0305}{{B}_{2}}\stackrel{\u0305}{{B}_{1}}{A}_{1}$
For A= B
${y}_{2}=\left({A}_{2}\stackrel{\u0305}{\theta}{B}_{2}\right)*\left({A}_{1}\stackrel{\u0305}{\theta}{B}_{1}\right)$
For A< B
${y}_{3}={B}_{2}\stackrel{\u0305}{{A}_{2}}+{B}_{1}\stackrel{\u0305}{{A}_{2}}\stackrel{\u0305}{{A}_{1}}+{B}_{2}{B}_{1}\stackrel{\u0305}{{A}_{1}}$
The equivalent representation of a 4bit comparator in proteus is shown below:
Figure 9: Simulation of a 4Bit Comparator in proteus
APPENDICES
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