The Digital Dice Game Biology Essay

Published: Last Edited:

This essay has been submitted by a student. This is not an example of the work written by our professional essay writers.

A traditional dice is a small polyhedral object, usually cubic in shape. It generates a random number in the range of one to six. There are also non - cubical dice with different number of faces such as tetrahedrons (four faces), octahedrons (eight faces) or dodecahedrons (twelve faces). A digital dice is an alternative device that can be used to replace the traditional device with the help of a numeric display. It is controlled with the help of a switch. The count will display numbers randomly from one to six on the 7 segment display in a push of the button.

1.1 Rules of the Game:

The Digital Dice game consists of two players, Player A and Player B.

Both the players, Player A and Player B, are given a switch each to control the dice.

In this game, only one player is allowed to play at a time and the input of only one player is counted at a time. A LED indicates the player's turn.

The output of each player's throw is added to the output of their previous throw's number. This gives their final score.

The maximum count is taken as 30. When any one of the players reaches the maximum count of 30, the Game ends. The player (Player A or Player B) has won the game.

The beeper along with a light indicates the player's victory.

Chapter 2

Circuit Description

This chapter gives a detailed description of the block diagram for the Digital Dice game project. It discusses the main parts and also gives a detailed explanation on the same.

2.1 Block Diagram

The main parts of the block diagram as shown in figure 1 are:

1. 2 - Clock pulses

2. Random Number Generator

3. Digital Dice Display

3. 2 Adder Circuits (including the seven - segment FND display)

4. 'Game - Over 'disabling circuit

5. Reset switch

Fig 1: Block Diagram for the digital dice game

2.2 Clock Pulse

Clock pulse is a signal used to synchronize the operations of an electronic system. They are continuous and precisely spaced changes in voltage. The main aim of this part in the circuit is to give the appropriate clock pulses to the next circuits to make a progress in the game.

For this purpose, 2 clocks have been employed for each player. Here a special circuit has to be employed so as not to allow the player that has already played to play until his opponent has had his chance. This is done by using the Toggling feature of J-K flip-flop (IC 7476). Each of the 2 clock pulses is then ANDED with the 2 outputs of J-K flip-flop which is Q and Q'. At any point of time, only one of Q and Q' will be HIGH and so only one player will be able to play at a time as per the rules of the game. The clock of the other player being ANDED with zero will be ineffective. The appropriate clock then will pass through the OR gate and into the input clock of the J-K flip-flop, thus toggling it and providing a chance for the other player to play. The output of the OR gate is given to the rest of the entire circuit as a 'common clock'.

2.3 Random Number Generator

The main aim of this part is to generate any number between 1 and 6 (inclusive) i.e. 3-bit binary number, similar to a cubic dice where each face represents a number. However, the number generated in this circuit is not in any kind of a predictable sequence and is in a perfectly random similar to an actual dice in such a game.

This is facilitated by the use of IC NE-555, which generates series of output clock pulses. The resistors and capacitors surrounding it formulate a particular RC time constant and the IC then continues to generate output clock pulses till the end of this time period. So, when the appropriate clock pulse is obtained from the above discussed clock pulse circuit, the pulses generated by IC NE-555 are fed to the next Integrated Circuit, Binary Ripple Counter (IC - 7493). Another Integrated Circuit, Decade Counter (IC - 7490) can also be used. The Binary Ripple Counter counts from 0 to 5 i.e. 3-bit numbers provided the MSB (Most significant Bit) of the counter is not considered. After the count reaches five, the Counter resets to zero. When many clock pulses are received by it in a single time-constant period, it counts from 0-5 many times and outputs any of these numbers. This is known as Random Number Generation.

However, the numbers obtained from the above procedure are between 0 and 5 (inclusive) and the desired numbers are from 1 - 6. This is taken into account by including another Integrated circuit, Binary Parallel Adder (IC - 7483) which increments the above generated number by 1 as it is between 0 and 5. The output of the Binary Parallel Adder is the final desired random number which is then fed into the Digital Dice-Display circuit as shown in the figure 1.

2.4 Digital Dice Display Circuit

The only purpose of this part is to show the face of the Dice corresponding to the number generated by the randomizer circuit.

This is done with the help of a BCD - 7 Segment decoder which is used to drive a common anode 7 segment display. The output of the above discussed circuit forms the input for the BCD which then enters the input of seven - segment decoder. The random number generated by the random number generator circuit will be displayed on the 7 - segment display when the button is pushed by a player. The number displayed is any number between 1to 6 in a complete random sequence.

2.5 Adder Circuits

This is the core part of this game. All the numbers generated so far should be accounted for each player independently in the form of their score. As discussed earlier, this score gets incremented by each alternate fall of numbers on the dice. The Adder circuit performs this function.

The Adder circuit is made up of a group of 3 AND gates. One of the inputs of the AND gates is a bit of the random number generation and the other input is one of Q and Q' (outputs of the J - K flip-flop as discussed above in the 'Clock Pulses' section). Hence, at a time, the score of only the appropriate player gets incremented by the number on the dice. Whereas the score of the other player remains the same (i.e. gets added by 0).

The outputs of the 3 AND gates enter the Integrated Circuit, Binary Parallel Adder (IC - 7483) as inputs for A. The Most significant bit (MSB) A is kept grounded. The inputs for B come from the output of the Integrated circuit, 4-bit Register (IC - 74194) and these stores the Least significant bit (LSB) of the final score. There are two Binary Parallel Adders and the output of this 1st Adder (IC - 7483) is connected to the 2nd Adder (IC - 7483), which converts the added binary number into its decimal equivalent and stores the output in the above mentioned 4 - Bit register (IC - 74194). This conversion is produced with the help of different logic gates (AND and OR gates). When the binary number is greater than 9, 6 (0110) is added to it, else 0 (0000) is added to the number thus generating the equivalent LSB decimal number. Therefore, the LSB remains less than or equal to 9, thus representing the score in decimal form.

The same technique is applied to the Most Significant Bit of the score. Here, 1 is added to the MSB of the Binary Parallel Adder (IC - 7483), if the above generated binary number is greater than 9. The other input for this 3rd IC-7483 comes from another 4-bit register (IC - 74194). Therefore, the MSB can also show decimal numbers from 0 - 9.

The same Most Significant Bit and Least Significant Bit numbers from the Adders are given as input to Integrated circuit, BCD (IC - 7447), which is the driver IC to the Seven-Segment LED display. The outputs of this Integrated circuit are fed into the LT-543, to show the corresponding numbers.

An important point to be noted here is that the same 'common clock' is given to the above mentioned IC-74194 registers so that they can output the stored numbers each time.

2.6 'Game - Over' Disabling Circuit

This part of the block diagram indicates the END of the game, i.e. Game - Over. The game is considered to be over once the score of any one of the two players (Player A or Player B) reaches/crosses the score of 30.

The second input of the Most Significant Bits of the Most Significant Bit of the decimal score of both the players form the input to the NOR gate. Thus, when any score reaches/crosses 30, the 2nd Most Significant Bit becomes HIGH. Thus NOR output becomes LOW (i.e. In a NOR gate, when any one of the inputs is HIGH, the output is LOW). This is then ANDED with the clock-pulse to be given to the J-K flip-flop. As a result, the J-K flip-flop does not receive any clock. Thus, the 'toggling' feature of the flip - flop stops. Thus, the random number generation stops and the Dice-display remain unchanged. And, finally the scores remain fixed. Therefore, the game has come to an end

The winning player (Player A or Player B) is identified by the tone of the buzzer/alarm along with a LED to provide an indicating light. This is having one end on the above 2nd Most Significant Bit and the other end grounded.

 2.7 Reset Switch

This is also a very important part of the game. The function of this switch is to bring the game back to start from any point of time.

This is performed with the help of a Combinational Circuit and a 'Push-to-OFF' switch. This is a kind of switch which has its 2 ends always connected, except when pressed/pushed. Thus, one end of the switch is grounded. Therefore, by default this makes the clear inputs of all registers HIGH. Here, the registers employ Active Low Clear inputs.

When the switch is not pushed, HIGH clear is fed to the registers via a NOT gate. Therefore, normal functioning of all the registers is obtained. Also, the output drawn from the OR gate then depends on the output from the AND gate (the 2 inputs of the AND gate come from the 2nd Most Significant Bit and 3rd Most Significant Bit of the output of the Binary Ripple Counter, IC - 7493).

When the switch is pressed, the connection of its 2 ends gets broken and thus making the Clear input to all registers LOW via the NOT gate (i.e. all registers are cleared). Therefore, one of the inputs to the IC - 7483 Adders become 0000. And, also the input of the OR gate becomes HIGH, thereby ignoring the 2nd input and thus providing HIGH output to the RO(1) Clear input of the Binary ripple counter, IC - 7493. Now, the counter is reset by 2nd Clear input RO(2) as it becomes HIGH, providing 0000 output. This forms the other input of Binary parallel adder, IC - 7483. Thus, the Adder circuits display 00 in the 7 - segment display. This 0000 output is then carried via the Binary parallel adder, IC - 7483 (here the input carry is also 0) to the Dice-display circuit which displays 00.

Chapter 3

Random Number Generation Circuit

This chapter explains the circuit diagram required for the random number generation and the digital - dice display. It also talks about the working for the same.

3.1 Circuit Diagram

The below figure (figure 2) shows the circuit diagram used for the random number generation of a digital dice.

Fig 2: Random Number Generation Circuit

3.2 Operation

Figure 2 shows the circuit diagram to generate any random number between 1 and 6 and display it on the 7 - segment display. In operation, a clock frequency of 50 Hz is generated by the pulse generator. It is ANDED with the push button. When the push button is pressed, the clock pulse generates a series of clock pulses. The combination of the clock pulse and the push button forms the counter clock for the Binary Ripple Counter (IC - 7493). This counter behaves as a Mod - 6 Counter and it counts from 0 - 5. Once the count reaches 5, it resets to zero. Thus, the connection of QB (with value 2) to R0 (1) and QC (with value 4) to R0(2) respectively.

The output of this counter is connected to the input A of the Binary Parallel Adder (IC - 7483), i.e. QA, QB, QC, QD to A1, A2, A3, A4 respectively. The function of the adder is to add the number 1 (Binary 0001) to the output from the Binary ripple counter. This is done by grounding the pins B1, B2, B3 and the pin B4 is connected to the supply to get a value of 1.

The output of the Adder is connected to the BCD - 7 segment display, i.e. the pins 9, 6, 12, 15 are connected to pins 7, 1, 2, 6 respectively. Therefore, any number between 1 and 6 is displayed in a totally random manner in the form of its decimal equivalent on the 7 - segment display.

This completes the random number generation and the Digital - dice display parts of the block diagram.

3.3 Components Assembled

The following components have been assembled on a Bread Board in order to create a random number display between 1 and 6.

3.3.1 Counter

A counter is a device which stores the number of times a particular event or process has occurred, usually in connection with a clock signal. Every counter requires a 'square wave' clock signal to make them count. A square wave clock signal (as shown in figure 3) is a digital waveform with sharp transitions between low (0V) and high (+Vs) voltage, such as the output from a 555 astable timer. Here it comes from the pulse generator.

Fig 3: A square wave clock signal

Examples of counting are digital clocks, watches, timers found in a range of appliances from microwave ovens to VCRs and counters are also found in everything from automobiles to test equipments.

There are mainly two types of counters:

Ripple Counters

In a ripple counter, there are a chain of flip-flops with the output of each flip - flop forming the input for the next. Every time the input of the flip - flop changes from high to low (on the falling edge), the state of the flip flop output changes.

Ripple counters mostly count on the falling-edge which is the high to low transition of the clock signal. They use this edge as linking counters becomes easier as the most significant bit (MSB) of one counter can drive the clock input of the next. This whole process occurs because the next bit must change state when the previous bit changes from high to low - the point at which a carry must occur to the next bit.

Fig 4: Falling Edge clock input

The disadvantages of this counter are:

There is a slight delay (known as a Ripple Delay) as the effect of the clock 'ripples' through the chain of flip-flops. But in many circuits, this is not a problem as it is far too short to be seen on a display.

In a logic system, the connection to the ripple counter outputs will cause false counts which may produce 'glitches' in the logic system and thereby disrupt its operation. For example, a ripple counter changing from 0111 (7) to 1000 (8) will briefly show 0110 (6), 0100 (4) and 0000 (0) before 1000.

Synchronous Counter

A synchronous counter has a more complex internal structure as compared to a ripple counter. The advantage of this counter over the ripple counter is that it ensures that all its outputs change precisely together on each clock pulse, thereby avoiding the brief false counts which occur with ripple counters.

Most synchronous counters count on the rising-edge (refer figure 5) which is the low to high transition of the clock signal. They usually have carry out and carry in pins for linking counters without introducing any ripple delays.

Fig 5: Rising - edge clock inputs

These counters have a synchronous reset which occurs on the next clock pulse rather than immediately as in a ripple counter. Since reset must be performed on the maximum count required, it is a very important function. Binary Ripple Counter (IC - 7493)

This is the counter used in the circuit. Figure 3 shows a clock signal driving a 4-bit (0-15) counter. It is connected with LEDs (Light Emitting Diodes) to show the state of the clock and counter outputs QA - QD. And Q indicates the output.

Fig 6: A 4 - Bit counter and Clock input

A counter can be used to reduce the frequency of an input signal and thus behaves as a frequency division counter (as shown in figure 7), i.e. they can be used to reduce the frequency of an input (clock) signal. Each stage of a counter halves the frequency, so here the LED on the first output QA flashes at half the frequency of the clock LED, i.e. QA is 1/2, QB flashes at 1/4, QC at 1/8 and QD at 1/16 of the clock frequency. It is usually labeled as Q1, Q2 and so on. Qn is the nth stage of the counter, representing 2n.

Fig 7: Frequency Division Process

Division by numbers that are not powers of 2 is possible by resetting counters. Counters can be reset to zero before their maximum count by connecting one (or more) of their outputs to their reset input. The counter is in two sections: Clock A for QA and Clock B for QB, QC and QD.

If the reset input is 'active-low' a NOT or NAND gate will be required to produce a low output at the desired count. 'Active - low' is indicated by a line drawn above reset. For example:   (say 'reset-bar'). The reset function requires an immediate reset on the next count. Decade Counter (IC - 7490):

A decade counter (refer figure 8) is a binary counter that is designed to count to 10 or 1010 in binary, i.e. it counts the number of pulses arriving at its input. The number of pulses is counted up till 9 and it appears in binary form on four pins of the IC. When the tenth pulse arrives at the input, the binary output is reset to zero (0000) and a single pulse appears at another output pin.

This function is performed due to the fact that the NAND output goes low, and resets the counter to zero. D going low can be a CARRY OUT signal, indicating that there has been a count of ten. So for ten pulses in the input, there is one pulse output. Therefore, the 7490 Decade Counter divides the frequency of the input by ten. And, if this pulse is applied to the input of a second 7490 decade counter, then the second IC will count the pulses from the first IC i.e. for 100 pulses input, there will be one pulse output.

Fig 8: A Decade Counter

3.3.2 Binary Parallel Adder (IC - 7483)

The parallel adder precedes the binary counter, i.e. once the counter begins its count from 0 - 5, it then enters the adder where the binary 0001 is added to it.

The central computational element in any circuit is the adder. The function of the parallel adder is to add two n - bit numbers together. For this purpose, n full - adders should be cascaded with each full - adder representing a column in the long addition. The carry signals 'ripple' through the adder from right to left.

Figure 9 indicates the working of a logic full adder/ subtractor. The adder circuit has a mode control signal M which determines whether the circuit has to operate as an adder or a subtractor. Each XOR gate receives one input from M and the other input from B, i.e. Bi. The function of the XOR gate is that if both the inputs of the XOR gate is the same, then the output of the XOR gate will be zero and if both the inputs to the XOR gate are different, then the output of the XOR gate will be 1.

When M = 0, the output of XOR gate will be Bi ⊕ 0 = Bi. Thus, the addition function takes place, i.e. the circuit performs A plus B (A + B). When M = 1, the output of XOR gate will be Bi ⊕ 1 = Bi'. Since it is the complement of B, subtraction function takes place, i.e. A plus 1's complement of B which is the same as A minus B (A - B).

Fig 9: Logic Diagram of a 4 - Bit Adder / Subtractor circuit

Every digit position consists of two operands and a carry. The operation of an adder is to add the two operands and the carry-in together. If the result is less than the base, this sum is outputted with a carry-out of 0. 0therwise the base is subtracted from the total of the two operands and the carry-in and this sum is outputted with a carry-out.

3.3.2 BCD - 7 segment display decoder

Here, the output of the Binary parallel adder forms the input for this BCD - 7 segment decoder to display the random number from 1 - 6.

The inputs A - D for the BCD (Binary Coded Decimal) display driver are connected from the outputs of the parallel adder. The display driver consists of a network of logic gates to make its outputs a - g become high or low. This lights the required segments a - g of a 7-segment display as shown in the figure. Usually, a resistor is required in series with each segment to protect the LEDs, 330 or 270 is a suitable value for many displays with a 4.5V to 6V supply. But for this project, only one 270 resistor is used which is connected between 3 (display test) and 8 (ground) pins of the integrated circuit.

Fig 10: Display driver with 7 - segment display

There are two types of 7-segment displays:

Common Cathode (CC or SC): This display consists of all the cathodes connected together. These need a display driver with outputs which become high to light each segment, i.e. they are illuminated with high voltages. For example the IC - 4511. Here, there is a connection between the common cathode to 0V. IC 4511 is designed to drive a common cathode display and thus would not work with the common anode display.

Common Anode (CA or SA): This display consists of all the LED anodes connected together. These need a display driver with outputs which become low to light each segment, i.e. they are illuminated by connecting with low voltages. For example, IC - 7447 (BCD - 7 segment decoder) which is the IC used for this project. Here, there is a connection of a resistor in series between the common anode to +Vs.

The 7447 chip is used to drive 7 segment display. The input to the 7447 is a binary number DCBA where D is 8s (1000), C is 4s (0100), B is 2s (0010) and A is 1s (0001). The IC - 7447 display is intended for BCD (binary coded decimal) which has input values from DCBA = 0000 (0) to DCBA = 1001 (9) (i.e. 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001 in binary). Inputs from 10 to 15 (1010, 1011, 1100, 1101, 1110, 1111 in binary) will light odd display segments.

The following functions can be performed on the IC - 7447:

This IC has an open collector outputs a - g, which can sink up to 40mA.

A lamp test can be performed on the IC to check if all the segments are in working condition. This is done by keeping the part of the IC low. At this point of time, all the display segments should light (showing number 8).

There is another function which is the Blanking Input (). If the blank input is low, then the display will be blank when the count input is zero (0000). This can be used to blank leading zeros when there are several display digits driven by a chain of counters. The blank output can be achieved by connecting the blank input of the next display down the chain (i.e. the next most significant digit).

Also, a function stands for Ripple Blanking Input. When is low and DCBA = 0000, the display is blank otherwise the number is displayed on the display. This is used to remove leading zeroes from a number. For example, displays 89 instead of 089. If more than one display has to be used, a connection of (Ripple Blanking Output) from most significant 7447 to the of the next 7447 has to be done.

If a connection between of the least significant 7447 to 5V is done, the display will turn off when the number is 0.

This circuit can also be controlled by a PLC (Programmable Logic Circuit), if the inputs to the BCD (Binary Coded Decimal) come from the 4 output bits of the PLC output card.

Chapter 4


This chapter lists the achievements and developments of the project

The following has been achieved in this project:

Successful design and simulation of random number generation circuit along with the dice display - Block Diagram of the Digital Dice game, circuit diagram for the display of random numbers from 1 - 6 on the 7 - segment display.

Successful assembly of wires, binary ripple counter (IC - 7493), binary parallel adder (IC - 7483), BCD - 7 Segment display decoder (IC - 7447).

The development of this project is as follows.

The digital dice game is currently being assembled, and post assembly, it will be used as a game to be played between two players..

Remaining circuit diagrams with more detail about the remaining parts of the block diagram will be designed.