# Single Stage H Biased Amplifier Biology Essay

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The objective of this laboratory exercise was to design, simulate, build and test a single stage H- biased amplifier to design specifications and requirements. The design specified a voltage gain of 50 be obtained, a lower cut off frequency of 100Hz and maximum symmetrical swing. An NPN 2N3904 transistor was to be used, with a supply voltage of 15volts. A 100kâ„¦ load resistor was also required in the design. The values for the components involved in the design were first calculated, using logical deductions, and then simulated using the software Multisim. The H- biased amplifier was then built on a solder less bread board. The various values were measured in the laboratory using the appropriate equipment. Analysis of the calculated, simulated and measured values was done. The results were discussed and used to determine whether the specifications were met.

This laboratory exercise was an introduction to the design of electronic devices. Valuable knowledge and practical skills were gained in performing this exercise. This knowledge would prove useful in future designs.

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Contents

## Table of Figures

## List of Tables

## List of Symbols/ Abbreviations

A - Amperes AC - Alternative Coupling

Av - Voltage Gain BJT - Bipolar Junction Transistor

Ci - Input Capacitor Co - Output Capacitor

CE - Emitter Capacitor (By pass) dB - Decibels

DC - Direct Coupling f - Frequency

hfe - Current Gain hie - Emitter Input Impedance

Hz - Hertz I - Current

IB - Base Current IC - Collector Current

IE - Emitter Current I1 - Current through R1

I2 - Current through R2 K.V.L - Kirchhoff's Voltage Law

k- Kilo m - milli

R - Resistance R1 - Resistor 1

R2 - Resistor 2 RE - Emitter Resistor

Re - Unbypassed Emitter Resistor RE* - Recalculated Emitter Resistor

RC - Collector Resistor RL - Load Resistor

RTH - Thevenin's Equivalent Resistance V- Voltage

VB - Voltage across Base VBE - Base Emitter Voltage

VCC - Supply Voltage VCE - Voltage across Collector and Emitter

VRC - Voltage across Collector Resistor VRE - Voltage across Emitter Resistor

VTH - Thevenin's Equivalent Voltage VR1- Voltage across R1

VR2 - Voltage across R2 XCE - Reactance of CE

XCi - Reactance of Ci XCo - Reactance of Co

Zi - Input Impedance Zo - Output Impedance

â„¦ - Ohms

## Introduction

The following gives a brief description of the Bipolar Junction Transistor (BJT).

A Bipolar Junction Transistor is an active semiconductor device formed by joining two P-N junctions whose function is amplification of an electric current. (Seale 2003). The transistor can also be used for the purposes of switching. However, in this exercise, the focus is centered on the application of amplification.

A bipolar junction transistor consists of three regions of doped semiconductors. P- type and N- type semiconductor materials are alternatively joined together to form the transistor. This therefore results in 2 PN junctions. The transistor consists of three regions, namely, the emitter, the base and the collector. The diagram below illustrates the basic structure of a transistor, showing the PN junctions and the emitter, base and collector.

BJT layers

Figure : Transistor

Source: http://encyclobeamia.solarbotics.net/articles/bip_junct_trans.html (accessed November 17th 2010 at 5:44pm.)

From the diagram it is easily seen that one P-N junction is between the emitter and the base and the other P-N junction is between the collector and the base. Since the emitter and collector are usually doped somewhat differently, they are rarely electrically interchangeable. (Seale 2003). The base also forms the mechanical base for the structure. (Seale 2003). The base region is made as thin as possible (about 10-6m) to get a reasonable good levels of current gain.(Seale 2003). Furthermore, it is made thin for easier passage of electrons through the base region to the collector.

Bipolar transistors are either NPN or PNP, based on the arrangement of their N-type and P-type materials. An NPN transistor is formed by 'sandwiching' a very thin region of P-type between two regions of N-type materials.

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Figure 2 below shows an NPN transistor, while figure 3 shows the symbol used to represent it.

NPN layers

Figure : NPN Transistor

Source: http://encyclobeamia.solarbotics.net/articles/bip_junct_trans.html (accessed November 17th 2010 at 5:44pm.)

Figure : NPN Transistor SymbolImage

Source: http://encyclobeamia.solarbotics.net/articles/bip_junct_trans.html (accessed November 17th 2010 at 5:44pm.)

Similarly, a PNP transistor is formed by 'sandwiching' a very thin region of N-type between two regions of P-type materials.

Figure 4 below shows the PNP transistor, while figure 5 shows the symbol used to represent it.

Figure : PNP TransistorPNP layers

Figure : PNP Transistor SymbolImage

(It should be noted that the circle around the transistor usually not seen when the transistor is drawn in circuit diagrams.) It is clear that the distinguishing characteristic of the two transistor symbols is the direction of the arrow.

A transistor in a circuit will be in one of three conditions:

Cut off (no collector current). In this region it can be used as switch.

In the active region (some collector current, more than a few tenths of a volt above the emitter. In this region, it can be used for amplifier applications.

In saturation (collector a few tenths of a volt above emitter), large current useful for "switch on" applications.(Nave)

The figure below illustrates these regions of operation.

http://hyperphysics.phy-astr.gsu.edu/hbase/solids/imgsol/tran6.gif

Figure : Regions of Operation of the Transistor

Source: http://hyperphysics.phy-astr.gsu.edu/hbase/solids/trans2.html#c4 , accessed November 17th 2010 at 5:40 pm.

A NPN transistor was used to in this laboratory exercise to act as an amplifier. The transistor must therefore be in the active region.

## Background Theory

The following describes the reasons for the choice of biasing arrangement and type of configuration. Possible applications of the design project are also included.

For transistors to produce amplification, an operating point must first be established. Since a transistor can act as an amplifier in the active region, it is here that the operating point is established. This operating point is fixed, and so it is referred to as a quiescent point (Q point). This is known as biasing. This operating point is the point where the applied signal would be amplified. Therefore it is required that this point be constant. Biasing is the operation of setting an operating point within an operating range and the purpose of bias design is to set the collector current of a transistor to a specific value and keep deviations due to temperature and beta variations to a specified minimum.(Kuhn 2008)

Biasing can take two forms, fixed biasing and H biasing. The fixed bias design works with a transistor with an appropriate current gain, beta. Temperature changes results in a change of beta. This results in a variation of Ic and consequently, the Q point changes. Hence, the fixed biased arrangement is thermally unstable. In the H biased design, the Q points are independent of beta and therefore the Q points are more stable. Two resistors form a potential divider and fix the base potential. Since the base potential is kept nearly constant, if Ic changes, an increase potential drop would develop across RE and VBE would decrease. This results in Ic dropping to its original value. This biased arrangement is therefore thermally stable. Due to this thermal stability, the H biased arrangement was chosen in preference to the fixed biased arrangement.

Now, though the H biasing arrangement was chosen, the type of configuration was still undecided. Three types of configurations exist. These include the common emitter, common base and common collector. According to Kuhn 2008, in general, the best amplifier to use is the one whose input resistance is comparable to the source resistance and whose output resistance is comparable to the load resistance.

Source Resistance/ Load resistance

Good Choice of Amplifier to consider

Greater than 10

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This essay has been submitted by a student. This is not an example of the work written by our professional essay writers.

Examples of our workCommon Collector

2 -10

Common Collector or Common Emitter

0.5 -2

Common Emitter

0.1 -0.5

Common Emitter or Common Base

Less than 0.1

Common Base

Table Showing Choice of Amplifier based on Source/Load Resistance

Source: http://www.kennethkuhn.com/students/ee351/text/bjt_general_design.pd, accessed 17th November 2010 at 5:17 pm.

It can be shown that the common-emitter amplifier is capable of achieving the highest possible power gain. He concludes by saying that, overall, the common-emitter amplifier is the most flexible in terms of input and output resistance while also achieving reasonable power gain.

Therefore, the common emitter configuration was chosen. Figure 7 shows this configuration.

Figure 7: Common Emitter Configuration

Source: Electronic Workbench Software- Multisim

Figure 7: Common Emitter ConfigurationQ1

## 2N3904

## Vcc

## R1

## R2

## Re

## RE*

## Rc

## RL

## Co

## Ci

## CE

This design project would serve as an introduction to the practical application of electronics. With the experience, knowledge and understanding gained in designing and the building the circuit, more advanced and complex circuits could possibly be built. These circuits would then be used in everyday applications, e,g a microphone, speaker or perhaps a new innovation. This simple circuit in itself could be used to amplify signals with the appropriate adjustments.

## Design Objectives

The following shows the specifications required for the design of the amplifier.

The specifications involved in the design of the single stage H-biased amplifier were as follows:

Voltage gain of 50

Lower cut off frequency less than 100Hz

Maximum symmetrical swing

Supply voltage of 15volts

It was required that a small signal NPN 2N3904 transistor be used in the design. A fixed load resistance of 100kâ„¦ was also required.

## Method

The following shows the apparatus and materials used in the design project, the operating conditions, how the various resistor and capacitor values were obtained and the basic laboratory procedure.

## Apparatus and Materials

The following shows a list of the apparatus and materials used in overall design and building of the amplifier.

2N3904 NPN Transistor

Solder less Bread board

Resistors (56â„¦, 680â„¦, 3.6kâ„¦, 62kâ„¦,10kâ„¦,100kâ„¦)

Capacitors (4.7uF, 47uF ,330uF)

Connecting wires

Pliers

Dual trace Oscilloscope

Power Supply

Function Generator

Multi-meter

LRC meter

## Analysis of Operating Conditions

The following gives an analysis of the operating conditions for the circuit.

The design of the amplifier consisted of two types of operating conditions. These included the DC conditions and the AC conditions. The DC and AC conditions were not mixed. Therefore each type of operating condition was considered individually.

## DC Analysis

The following describes the operating conditions for the DC analysis.

In DC circuits, capacitors act as an open circuit. In an open circuit, no current flows. Therefore the capacitors were omitted when considering the operating conditions for DC.

For the transistor to function as an amplifier, the various quiescent currents and voltages associated with it need to be known. Also, the resistor values need to be known. Therefore, some calculations must first be made.

The figure below shows the circuit required for DC analysis.

Figure : Circuit Required for DC Analysis

Figure : Circuit Required for DC AnalysisVcc

## R2

## RE

## Rc

## Q1

## 2N3904

## R1

Figure 8: Circuit Required for DC Analysis

Source: Electronic Workbench Software - Multisim

Note that this circuit is similar to figure 7. However, the capacitors were omitted as they are part of the AC analysis.

The supply voltage, , was given as 15 volts.

## Determining Ic

The following describes how the value of Ic , was chosen.

The transistor datasheet (found in the appendix) was used to choose an appropriate value for. Firstly, the graph of - Typical Pulsed Current Gain vs Collector Current, , was used. Since the quiescent points are independent of beta, Î², (), then the exact value of Î² becomes irrelevant. Hence, beta can be chosen as any appropriate value. Since the operating temperature for the transistor was room temperature, therefore, the graph at 25Â°C was selected. From the graph it was seen that beta was relatively constant at an of 2mA. Due to this constant beta, a selection of 2mA for was made. It was found that beta was approximately 230. It should be noted that a value of 1mA could also have been chosen, based on the same criteria upon which was chosen. To add some justification to the value chosen, the graph of Base- Emitter ON voltage vs Collector Current was also considered. It was known that an approximate value for was 0.68V. Using again the graph at room temperature, (25Â°C), the corresponding value for a voltage of 0.68 was 2mA. Since multiple graphs indicated that a value of 2mA would be appropriate, therefore, was chosen to be 2mA.

## Calculation of

The following shows the steps involved in determining the value of.

A requirement was maximum symmetrical swing. That is, must be able to increase and decrease by the same value. From the circuit,( figure 8), is in series with the emitter of transistor, and therefore in series with the voltage. Since would cause a voltage drop, , across itself, this would therefore reduce the voltage . This voltage drop across, that is, would therefore limit the symmetrical swing. So, to obtain maximum symmetrical swing, it was desired that be negligible, when compared to the voltage drop across. With a small , then would be large, and hence produce maximum symmetrical swing. Since 10% can be considered negligible in comparison to 90%, it was therefore assumed that was one tenth the supply voltage.

That is,= 1/10........[1]

Since was given as 15volts, then,

= 1/10 (15)

= 1.5 volts

Ohm's law was applied,

Then, = â€¦â€¦ [2]

In the circuit, the current which flows through , was the same current . (It is seen later that â€¦.[20])

Therefore, = â€¦[3]

The formula was rearranged to make the subject,

## =÷.

Since = 2mA,

Therefore,= 1.5V÷2mA

So, = 750â„¦

## Calculation for

The following shows the steps involved in determining the value of.

The design for maximum symmetrical swing was considered here.

Applying Kirchhoff's Voltage Law (K.V.L) to the circuit:

= â€¦..[4]

Equation [4] was rearranged giving the equation:

## =

So, = -â€¦..[5]

Recall, for maximum symmetrical swing, that must increase and decrease by the same value. This implies that would therefore be equal to.

â€¦â€¦[6]

Therefore,

= -â€¦..[7]

So, 2=-â€¦â€¦[8]

Hence, =-) ÷2 â€¦.[9]

Where =15V and =1.5V

Therefore = (15-1.5) ÷2

=13.5 ÷2

= 6.75V

Ohm's law was applied, = â€¦[10]

The formula was rearranged to make the subject giving,

## = ÷,

Since = 2mA

Therefore, = (6.75V) ÷ 2mA

= 3375â„¦

## Calculation for values of and

The following shows the steps involved in determining the value of and .

The circuit in figure 8 was firstly redrawn as shown in figure 9. This was done so that the Thevenin's model of the circuit could be easily obtained. Figure 10 shows the Thevenin's model for the circuit.

## Q1

## 2N3904

## Vcc

## R1

## R2

## RE

## Rc

## Vcc

Figure : Redrawn Circuit from Figure 8

Source: Electronic Workbench Software- Multisim

## Q1

## 2N3904

## Vcc

## RTH

## Re

## Rc

## VTH

Figure 10: Thevenin's Model of the Circuit

Source: Electronic Workbench Software

From figure 9, Thevenin's Theorem was applied for the resistance.

This gave, = // â€¦â€¦â€¦[11]

= ) ÷ â€¦â€¦.[12]

Below shows how an expression for was found.

Since was in parallel with, therefore, the voltage across is the same as the voltage across.

Voltage Divider Rule was applied to obtain:

= ÷ ]* â€¦â€¦â€¦â€¦â€¦.[13]

K.V.L was applied to the circuit in figure 10, this resulted in,

= ++â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦.[14]

But = +â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦.[15]

So, by substitution of equation [4] into equation [3] gives,

= +++â€¦â€¦â€¦â€¦â€¦â€¦[16]

Also, = Î²â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦[17]

Substituting [17] in [16] gives,

= ++ (Î²+

= ++ (1+Î²

= + {1+Î²)+ â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦..[18]

Rearranging [18] to make the subject of the formula gives,

+{1+Î²)+ =

+{1+Î²) =-

Therefore, =- ÷ +{1+Î²)â€¦â€¦â€¦â€¦â€¦â€¦â€¦â€¦[19]

Since hfe is high, to ensure that IB does not cause variations in VB, IB was chosen as one tenth .

Also, Recall [15]:= +

In transistor designs, the base current, , is made much smaller than the collector current. (recall from introduction).

Hence, â€¦.[20]

Since is therefore significantly smaller than, then, it can be said that is negligible when compared to. Therefore, it was assumed that was one tenth of. So =1/10 â€¦[21]

Since = 2mA

Hence,=1/10 (2mA)

So,= 0.2mA

Since = I2, then,

I2 = 0.2mA

When the transistor is on, also known as being forward biased, there is a voltage drop of 0.7 volts across the base-emitter.i.e. = 0.7 volts.

K.V.L was applied to the circuit in figure,

V2=+â€¦[22]

Ohm's law was used,

I2R2= +â€¦.[23]

The formula was rearranged to make R2 the subject,

R2 =+) ÷ I2 â€¦â€¦[24]

Since = 1.5V, = 0.7V and I2 = 0.2mA

Then, I2R2= (1.5V +0.7V)

Therefore, R2 = (1.5V +0.7V) ÷ 0.2mA

R2 = 2.2V ÷ 0.2 mA

Hence, R2 = 11kâ„¦

The Voltage divider rule was used to find the value of R1

So, VB =(R2 * ) ÷ (R1 +R2)â€¦â€¦[25]

The formula was rearranged to make R1 the subject.

(R1 +R2) VB = (R2 * )

(R1 +R2) = (R2 * ) ÷ VB

Therefore, R1 = [(R2 * ) ÷ VB ] - R2 â€¦..[26]

So, R1= [(11kâ„¦ *15V)÷ 2.2V] - 11kâ„¦

R1= [(165000)÷ 2.2] - 11kâ„¦

R1= 75000-11000

Therefore, R1 =64000â„¦

R1 = 64kâ„¦

The following table shows the calculated and standard resistor values. The standard resistor values represent the resistors that are available. It is unlikely that stores have a 3.375kâ„¦ resistor, hence a value close to it (3.6kâ„¦) would be chosen.

Resistor

Calculated Value (kâ„¦)

Standard Value(kâ„¦)

RE

0.75

0.75

RC

3.375

3.6

R1

64

62

R2

11

10

Table Showing Calculated and Standard Resistor values

Now that R1 and R2 have been calculated, VTH , RTH and IB , can now be calculated.

Recall [12]

= ) ÷ â€¦...[12]

Therefore, RTH = (64k*11k) ÷ (64k+11k)

RTH = 9386.667â„¦

Recall [13]

= ÷ ]* â€¦â€¦â€¦[13]

Therefore, = [ 11k ÷(11k +64k)]* 15

= 2.2V

Therefore, IB can now be found. Recall [19]

=- ÷ +{1+Î²â€¦â€¦â€¦[19]

So, IB = 2.2 -0.7 ÷ (9386.667 + {1+230}(750)

IB = 0.0082mA

## AC Analysis

The following describes the operating conditions for the AC analysis.

The AC analysis was done using h-parameters.

The figure below shows the circuit used for AC analysis.

## Q1

## 2N3904

## Vcc

## R1

## R2

## Re

## RE*

## Rc

## RL

## Co

## Ci

## CE

Figure : Circuit used for AC Analysis

Source: Electronic Workbench Software- Multisim

The equivalent of this circuit is shown below.

Figure 12: Equivalent Circuit

Source: Electronic Workbench Software-Multisim

Figure : Equivalent Circuit

## hfeIB

## R1

## hie

## R2

## Re

## Rc

## RL

K.V.L was applied and the result was obtained. (Re and RE* were taken as a single resistor, RE)

So, Vin= hie IBâ€¦â€¦.[27]

And Vo= - hfeIB(Rc//RL)â€¦â€¦â€¦[28]

Since voltage gain is given by, Av = â€¦.[29]

Therefore, Av = -hfeIB(Rc//RL) ÷ hie IBâ€¦â€¦.[30]

Hence, Av =- hfe(Rc//RL) ÷ hieâ€¦..[31]

The value for Av was therefore found.

In the transistor data sheet, using the graph of Input Impedance, it was seen that at a collector current, of 2mA, that the corresponding hie value was 2kâ„¦. The graph of - Typical Pulsed Current Gain vs , hfe was 230.

Av = - 230( 3375//100000) ÷ 2000

Av = -230 ( 3265) ÷ 2000

Av = -(750950) ÷ 2000

Therefore, Av = - 375.475

However, the design specified a voltage gain of 50. Since 375.475 is greater than 50, the resistor RE was split into two smaller resistors, Re and RE*. The resistor RE* was bypassed with a capacitor. (Page 28 shows theoretically how the introduction of the bypass capacitor reduces the gain of the amplifier.)

## Calculation of Re and RE*

The following shows the method in which Re and RE* were determined

K.V.L was applied to the circuit in figure 12.

At the input, Vin = IBhie + (IB +hfeIB) Reâ€¦[32]

Vin = IB (hie + (1 +hfe) Re )â€¦[33]

At the output, Vo = -IBhfe (Rc //RL)â€¦..[34]

Therefore, voltage gain, Av = Vo÷ Vinâ€¦â€¦ [29]

Av = -IBhfe(Rc //RL) ÷ [IB(hie + (1 +hfe) Re )]â€¦[35]

[35] Simplified was to,

Av = - hfe(Rc //RL) ÷ [(hie + (1 +hfe) Re )]â€¦..[36]

The formula,[36] was rearranged to make Re the subject.

So, [(hie + (1 +hfe) Re )] = - hfe(Rc //RL) ÷ Av

[(1 +hfe) Re ] = [ - hfe(Rc //RL) ÷ Av ] - hie

Therefore , Re = {[ - hfe(Rc //RL) ÷ Av ] - hie }÷ (1+ hfe )â€¦[37]

The appropriate values were substituted into the equation and the value of Re was determined.

Since the desired gain is 50, hence, Av is substituted as 50.

Re = {[ - 230(3375 //100) ÷ -50 ] - 2000 }÷ (1+ 230)

Re = {[ - 230(3265) ÷ -50 ] - 2000 }÷ ( 231)

Re = {[ 15019 ] - 2000 }÷ ( 231)

Re = {13019}÷ ( 231)

Re = 56.359

Therefore, Re = 56â„¦

Since RE = Re + RE*â€¦..[38]

Then , 750 = 56 + RE*

Therefore, RE* = 694â„¦

The following table shows the calculated and standard resistor values for Re and RE*.

The standard values represent the values of resistors that were available.

Resistor

Calculated value (kâ„¦)

Standard value (kâ„¦)

Re

0.056359

0.056

RE*

0.694

0.680

Table Showing Calculated standard resistor value

Calculation for Capacitor values, Ci ,Co and CE

The following shows the steps involved in the calculations of Ci , CO and CE.

Ci and CO act as decoupling capacitors in the circuit. The power supply decoupling capacitors filter undesired electronic signals which have been coupled onto the power supply voltage. (Kelly and Emad 1998). Essentially, what this means is that the decoupling capacitors block the DC voltage while permitting the AC to flow. This prevents the DC signal from affecting the bias. Also, it blocks the DC from reaching the AC input source.

The main function of the bypass capacitor was to reduce the gain of the amplifier to the desired value. Without the bypass capacitor, the gain of the amplifier was given by,

Av =- hfe(Rc//RL) ÷ hieâ€¦..[31]

With the introduction of the bypass capacitor, the gain was now denoted by,

Av = - hfe(Rc //RL) ÷ [(hie + (1 +hfe) Re )]â€¦[36]

From these two equations, since the numerator is the same, and the denominator is larger in [36], hence, the value of Av would be smaller. Therefore, the gain would be reduced with the introduction of the bypass capacitor.

Also, the bypass capacitor is to filter out noise at high frequencies. Basically, as the frequency of a signal increases and the pulse width decreases, the impedance of the capacitor decreases and the bypass capacitor acts as a short circuit to these high frequency charges. The dissipation of high frequency charge is related to the value of the capacitor and the subsequent series resistance associated with it. (Wenzel et al.1997.)

Firstly, when a particular capacitor was being analyzed, (to be calculated), the other two capacitors were considered as short circuits. This was done so that the effect of the individual capacitor on the circuit could be analyzed. Capacitors act as short circuits, allowing current to flow through them and bypassing the component.

The reactance of a capacitor, Xc, is given by,

Xc =1÷ (2Ï€fC)â€¦â€¦â€¦.â€¦[39]

where f is the frequency.

There would be a voltage drop across the capacitor. With respect to the capacitor at the input, this voltage drop across the capacitor would therefore limit the voltage across the resistors R1 and R2 .Hence , reduce the voltage being sent to the input of the amplifier to be amplified. It is desired that the maximum voltage possible, be sent to the input to be amplified. Since this voltage drop across the capacitor limits the voltage being sent to the input, it is therefore desired that the voltage drop across the capacitor be negligible in comparison to the input impedance of the circuit. Hence, the reactance of the capacitor was assumed to be one tenth of the input impedance, Zi.

So, for capacitor Ci, , Reactance Xci = 1/10 Ziâ€¦â€¦[40]

In figure 12 , the input impedance Zi is given by,

Zi = R1 //R2//hieâ€¦..[41]

In the transistor data sheet, using the graph of Input Impedance, it was seen that at a collector current, of 2mA, that the corresponding hie value was 2kâ„¦.

Therefore, Zi = 64kâ„¦//11kâ„¦//2kâ„¦

Zi =9.387kâ„¦//2kâ„¦

So, Zi = 1.649kâ„¦

Now, Xci = 1/10 Zi

Hence, Xci = 1/10(1.649kâ„¦)

So, Xci = 164.9â„¦

Recall [39], Xc =1÷ (2Ï€fC)

Therefore, Xci =1÷ (2Ï€fCi)

The formula was rearranged to make Ci the subject.

2Ï€fCi =1÷ Xci

Therefore, Ci = 1÷ (Xci *2Ï€f)â€¦.[41]

Since f represents the lower cut off frequency, which was given as 100Hz. Hence the value for Ci was found.

C i= 1÷ (Xci *2Ï€f)

Ci = 1÷ (164.9 *2Ï€{100})

Ci = 1÷ (103609.726)

Ci = 0.00000965F

So, Ci = 9.65uF

A similar method was used to find CO.

The reactance of the capacitor was considered negligible in comparison the output impedance. This was done so that there would be a minimal voltage drop across the capacitor and the maximum output voltage dropped across the load resistor, RL.

So, XCO = 1/10 ZO, (similar to [40] )

Where ZO= (RC//RL)

Then, ZO= (3.375kâ„¦//100kâ„¦)

So ZO= 3.265kâ„¦

Since XCO = 1/10 ZO

Then, XCO = 1/10(3.265kâ„¦

XCO =326.5â„¦

Now, XCO =1÷(2Ï€fCO)

The formula was rearranged to make CO the subject. The result was as follows.

CO = 1÷ (XCO *2Ï€f)

Therefore CO =1÷(326.5 *2Ï€*100)

CO = 4.87uF

Similarly, for CE.

The reactance of the capacitor was considered negligible in comparison the output impedance. This was done so that there would be a minimal voltage drop across the capacitor and the maximum output voltage dropped across the resistor, Re.

XCE = 1/10 Re

XCE = 1/10 (56)

XCE = 5.6â„¦

Since , XCE = 1÷ (2Ï€fCE)

The formula was rearranged to make CE the subject. The result was as follows.

CE= 1÷ (XCE*2Ï€f)

CE = 1÷ (5.6*2Ï€*100)

CE = 284uF

The following table shows the calculated, standard and the chosen capacitor values for Ci ,Co and Ce .

Capacitor

Calculated Value (uF)

Standard Capacitor Value(uF)

Capacitor value chosen (uF)

Ci

9.65

10 ,47

47

Co

4.87

4.7

4.7

Ce

284

330

330

Table Showing Calculated and Standard Capacitor values

The standard capacitor values represent the capacitor values that were available in stores. It is generally rare to find a capacitor value of exactly 4.87uF, hence a value of 4.7uF was chosen.

The value of Ci was chosen to be 47uF instead of 10uf to ensure that the frequency was not exceeded. From the equation, C i= 1÷ (Xci *2Ï€f), it was noticed that if that capacitor value was increased, the frequency would decrease. This is easily seen when the equation is rearranged to make frequency, f , the subject of the formula.

C i= 1÷ (Xci *2Ï€f),

Ci *(Xci *2Ï€f) = 1

(Xci *2Ï€f) = 1 ÷ Ci

2Ï€f = (1 ÷ Ci ) ÷ (Xci)

2Ï€f = 1 ÷ ( Ci *Xci)

f =[ 1 ÷ ( Ci *Xci) ] ÷ 2Ï€

Therefore, f = 1 ÷(Xci *2Ï€C),

So, since 2Ï€ is a constant and if Xci is also considered a constant value, therefore it appears that frequency is inversely proportional to capacitance. Hence, an increase in capacitance would bring about a reduction in frequency. So, to ensure that the lower cut off frequency of 100 Hz is not exceeded the capacitor value was increased.

The capacitors used were polarized capacitors. This was done to ensure that there was current flows in only one direction.

The circuit diagram below, (figure 13) shows the final circuit diagram complete with the components and their respective values.

## Q1

## 2N3904

## V1

## 15 V

## R1

## 62kâ„¦

## 5%

## R2

## 10kâ„¦

## 5%

## Re

## 56â„¦

## 5%

## R3

## 680â„¦

## 5%

## RE*

## Rc

## 3.6kâ„¦

## 5%

## RL

## 100kâ„¦

## 5%

## V2

## 100mVpk

## 1kHz

## 0Â°

## C2

## 4.7uF

## C1

## 47uF

## C3

## 330uF

## 20%

Figure 13: Completed Common Emitter Amplifier

Source: Electronic Workbench Software

Figure : Completed Common Emitter Amplifier

## Laboratory Procedure

The following includes the method in which the circuit was connected to measure the respective values. Some safety precautions/ requirements associated with laboratory use are also included.

Firstly, it was required that Proper Protective Equipment, PPE, be worn at all times. There was no eating and drinking allowed in the lab. This was to reduce the possibility of spillage which could damage the equipment. The workstation was organized neatly, to allow as much free space as possible.

Before the circuit was built, the following precautions were taken:

The bread board was checked for continuity to ensure no breaks were present.

The resistors values were checked using the multimeter to ensure that they were within their tolerance range. Resistors that were not in their tolerance range were discarded.

The following table summarizes the standard resistor values available and their actual values.

Standard Resistor Value (kâ„¦)

Tolerances (%)

Upper Tolerance

(kâ„¦)

Lower Tolerance (kâ„¦)

Measured

Value of Resistor (kâ„¦)

Within Tolerance

(Yes/No)

0.0560

5

0.0588

0.0532

0.0555

Yes

0.6800

5

0.7140

0.6460

0.6690

Yes

3.6000

5

3.7800

3.4200

3.5200

Yes

10.0000

5

10.5000

9.5000

9.7800

Yes

62.0000

5

65.1000

58.9000

61.1000

Yes

100.0000

5

105.0000

95.0000

99.4000

Yes

Table Showing Resistor values and their tolerances

From this, it is easily seen that all resistors were within their tolerance ranges.

Using the LCR meter, the values of the capacitors were also checked. The ends of the capacitors were touched so that they were discharged. Then their values were obtained. The following table shows the standard capacitor values and the values measured.

Standard Capacitor Value (uF)

Measured Capacitor Value (uF)

4.7

4.45

47

52.3

330

294

Table Showing Standard and Measured Capacitor Values

The following outlines how the circuit was connected to the devices:

The function generator was calibrated using the oscilloscope to ensure it would produce an accurate input signal. Both the function generator and the oscilloscope were then turned off.

The power supply was turned on. It was ensured that the current limiter control was set in its mid position. The voltage was then set to 15V, and then turned off.

The function generator was connected to the input of the circuit.

Channel 1 of the oscilloscope was also connected to the input of the circuit.

Channel 2 of the oscilloscope was connected to the output of the oscilloscope.

It was ensured that all connections were correct and components were properly inserted. All necessary ground connections were made.

It was ensured that the capacitors were connected in their proper directions. Any equipment not currently in use was switched off.

All related equipment was switched on and the various quiescent points were measured and the gain was obtained. It should be noted that, when the oscilloscope was in use, it was known very bright stationary spots damage the phosphor coating on the screen. Therefore the intensity control was adjusted until it was appropriate.

## Results

The following shows the results obtained from the design of the amplifier. These results include the quiescent points and the voltage gain, both obtained firstly from Multisim, then measured in the laboratory.

## Quiescent points

The following shows the various quiescent points obtained from Multisim and the laboratory.

After the values for the required components were calculated, the circuit was simulated in Multsim. From this, the simulated quiescent currents and voltages values were obtained. The simulation showed that the circuit was functioning properly. It was then built on a solder less breadboard. The quiescent currents and voltages were then measured in the laboratory using the appropriate devices. The tables below summarize the results.

The table below compares the calculated, simulated and measured quiescent currents.

Quiescent Current

Calculated (mA)

Simulated (mA)

Measured (mA)

Ic

2.000

1.783

1.700

IB

0.008

0.012

0.011

I1

0.200

0.211

0.209

I2

0.200

0.211

0.209

Table Showing quiescent currents

It was known that that the base is made very thin in transistor design. Therefore it was expected that IB would be very small.

The table below compares the calculated, simulated and measured quiescent voltages.

Quiescent Voltage

Calculate (V)

Simulated (V)

Measured (V)

VRE

1.500

1.300

1.268

VCE

7.500

7.286

7.580

VRC

6.200

6.405

6.170

VR1

12.400

13.017

13.100

VR2

2.000

1.982

1.968

Table Showing quiescent voltages

It is clear from both tables 4 and 5 that the simulated and measured values, somewhat coincide with the calculated values.

## Voltage Gain

The following shows how the gain of the amplifier was obtained. The oscilloscope and bode plot were both used.

Firstly, using Multisim, the bode plotter and the oscilloscope were connected to the appropriate parts of the circuit. This is shown in the figure below.

Figure : Circuit with Bode Plot(center) and Oscilloscope (right) connected in Multisim

Source: Electronic Workbench Software

Channel A of the oscilloscope was connected to the input of the circuit, while channel B of the oscilloscope was connected to the output of the circuit. The resulting waveform from the oscilloscope is shown below.

Figure : Input and Output Waveforms

Source: Electronic Workbench Software - Multisim

From this diagram, it is seen that the input voltage, Vin is approximately100mV and the output voltage, Vo is 5 volts. Approximately because the waveform is just below the 100mV mark, hence it is approximately 100mV.

Since voltage gain, Av is given by Vo ÷ Vin

Therefore, Av = 5V ÷ 0.1V

Therefore, Av = 50

So, Av is approximately 50.

The bode plot was also used in the simulation. It resulted in producing 2 graphs. These graphs, figures 16 and 17 respectively, are shown below.

Figure : Graph of Gain (dB) vs Frequency (Hz) obtained from Bode Plot

Source: Electronic Workbench Software - Multisim

Figure : Graph of Phase vs Frequency

Source: Electronic Workbench Software - Multisim

Figure 16 shows a graph of Gain in decibels (y axis) versus Frequency (x axis). While, figure 17 shows a graph of Phase in degrees, versus frequency. It is clear that both had the same scale.

From figure 16, the graph of gain vs frequency, the voltage gain was obtained. The horizontal portion of the graph indicates the gain. The maximum value of this gain was found to be 34.237. However, this gain was in decibels, (dB. Therefore, it was converted to volts.

Using the relationship, Av (d B) = 20 log Av (V)

So, gain in volts, Av (V) = log-1[Av(dB)÷ 20], where, log-1 represents the inverse logarithm.

Hence, Av (V) = log-1[34.237÷ 20],

Av (V) = log-1[1.71185]

Therefore, Voltage Gain, Av = 51.51

So a gain of 51.51 was obtained from the bode plot.

The oscilloscope in Multisim showed that the amplifier produced a gain of 50, while the bode plot produced a gain of 51.51. These values were quite close. Since the circuit had simulated a voltage gain of approximately 50, this was then an indication to measure the gain in the laboratory.

In the laboratory, an input waveform of 100mV peak to peak was obtained from the function generator and this was seen in channel 1 of the oscilloscope. The VOLTS/DIV knob was set to 1 volt peak to peak. Therefore, 1*100mV is equal to 0.1V. Hence, the input signal, or input voltage, Vin was 0.1 volts. In channel 2, the output produced a waveform of 5 volts peak to peak and the VOLTS/DIV knob was set to 1 volt peak to peak. Therefore 1*5V is equal to 5 volts. Hence, the output signal, or output voltage, was 5Volts. The input and output waveforms were similar to those on figure 15.

Now, Voltage Gain, Av = Vo ÷ Vin

Av = 5Volts ÷ 0.1Volts

Av = 50

Therefore, a voltage gain of 50 was obtained from the oscilloscope.

## Lower Cut- off Frequency

The following describes how the lower cut off frequency was determined.

The upper and lower cut off frequencies of the circuit are defined as the frequencies, which are above and below the gain, when the gain drops by 3dB or . Only the lower cut off frequency was of concern. From the graph of gain vs frequency, (figure 16), the gain was determined to be 34.237 dB. When this gain drops by 3dB, the result was 31.237dB. (34.237 -3 =31.237). So, at the point on the graph where the gain was 31.237, the frequency was determined. A line called the 'Interpolator line' was dragged across the plot to determine the frequency and gain at different points on the plot. The interpolator line was dragged to two points, one where the gain was 31.076dB and the other where the gain was 31.483dB (on the left of the plot obtains lower frequencies). The frequencies at these points were 7.903Hz and 8.692 Hz respectively. The exact gain of 31.237dB was not located on the plot, so the closest gain above and below it was taken. Since a gain of 31.237dB is between that of 31.076dB and 31.483dB, hence it was assumed that the frequency would lie between the respective frequencies of 7.903Hz and 8.692Hz. Therefore it can be assumed that the lower cut-off frequency is approximately 8.4Hz.

## Maximum Symmetrical Swing

The following shows how the maximum symmetrical swing was illustrated.

Refer to figure 15. It is seen that the input waveform goes from positive 100mV to negative 100mV, this is an example of maximum symmetrical swing because it increases and decreases by the same value. Now, figure 18 below, shows the waveform just before clipping. The input voltage was increased until the point before clipping occurred. This input voltage was 145mA and the resulting output waveform was approximately 13V peak to peak. This demonstrates maximum symmetrical output swing just before clipping. Figure 19 illustrates a clipped waveform.

Figure : Waveform Just Before Clipping

Source: Electronic Workbench Software - Multisim

Figure : A Clipped Waveform

Source: Electronic Workbench Software - Multisim

## Discussion

The following discusses the results of the experiment.

From the results form tables 5 and 6 showed that there was a small difference in the calculated, simulated and measured values for the quiescent points.

The following may account for the changes in the quiescent points:

The breadboard itself had internal resistance. Therefore, this may explain why the measured values for quiescent currents are slightly smaller than the simulated values.

Resistors had tolerances.

The simulation does not take into account the environmental factors which would affect a real life circuit. Hence the conditions in the laboratory would affect the Q points.

The voltage gain of an amplifier is the ratio of the output voltage to the input voltage. Since it is a ratio, therefore, it has no units. A voltage gain of 50 was a requirement of the design. This '50' indicates that the output signal must be 50 times that of the input signal, or in other words, the input voltage must be amplified by 50. In the laboratory, a signal of 100mV was introduced to the input of the circuit from the function generator. The oscilloscope showed that the output signal was 5V (refer to results). Since 5V is 50 times that of 0.1V (100mV), hence, the input signal was amplified by 50. Therefore, a gain of 50 was obtained for the circuit. So, based on the results, it can be justified that the design specification of a voltage gain of 50 has been met. However, in reality, the gain was approximately 50 because the signal was approximately 100mV. Figure 15 shows the input signal is just below the 100mV mark, hence the gain is slightly greater than 50,but it is approximately 50. The slight difference can be accounted to the tolerances of the resistors. Also, it is possible that the function generator used to produce the input signal was not functioning properly, (though it was calibrated using the oscilloscope). Another possible cause was the fact that the laboratory, where the results were taken, was at a temperature which was not 25Â°C. From the graph of Base- Emitter on voltage vs , (transistor datasheet found in appendix), it is clear to see that if the temperature changes, Ic would vary. Hence, the working of the circuit would be compromised.

Maximum symmetrical swing is simply the waveform being able to obtain the maximum amplitude possible from the given supply, hence, maximum swing. The symmetrical refers to the waveform on both the negative and positive half cycles being equal, hence symmetrical. Therefore, maximum symmetrical swing would refer to the waveform produced having the maximum amplitude on both positive and negative half cycles. In other words, Vce being able to increase and decrease by the same value. Due to the voltage drop across RE , the swing in this case was limited to +6.75V and -6.75V. Clipping occurs when an input voltage goes past a particular reference voltage. From figure 19, the swing was affected by the effect of clipping.

Since the initial waveform, (figure 15) showed maximum symmetrical swing, therefore, this design specification was met.

The lower Cut off frequency was determined to be between 7.903Hz and 8.692Hz (approximately 8.4Hz) for a gain of 31.237dB. Since this frequency is lower than 100Hz, therefore, this design specification was met.

This design was limited since it can only amplifier voltages up to a particular value, until clipping occurs.

## Conclusion

The following shows the conclusions drawn from the design.

From the results, a voltage gain of 51.51 was obtained form the bode plot, while a voltage gain of 50 was obtained from the oscilloscope. Since 51.51 is approximately equal to 50, hence, the voltage gain of 50 was obtained and this task was accomplished. Maximum symmetrical swing was demonstrated, so this was also achieved. The lower cut- off frequency was found to be approximately 8.4Hz, which is less than 100Hz. Therefore, the specification of a lower cut -off frequency less than 100Hz was achieved.

Due to the time constraint, it was not possible to design more than one circuit. Multiple circuits with different Ic , resistor and capacitor values could test the design specifications more thoroughly and comprehensively and expose any faults in the designs. It is therefore recommended that multiple circuits be built.

It can now be concluded that an H-biased common emitter amplifier was designed, simulated, built and tested. The design specifications were met. Therefore, the project can now be classed as a success.

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