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Benefits of Ferroelectric Random Access Memory as Unified Memory

Paper Type: Free Essay Subject: Sciences
Wordcount: 4972 words Published: 23rd Sep 2019

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Ferroelectric random access memory (FRAM) as unified memory and benefits over existing data storage technology

Abstract—The design of ferroelectric random access memory (FRAM or FeRAM) cells provides a unique combination of the benefits of static random access memory technology with those of flash memory. While similar semiconductor processes are involved in the three, the flexibility of FRAM allows for both processing of program code and storage of data in the same cell network. Benefits such as low power consumption, high read/write speeds, high read/write endurance, and use as either flash memory or working RAM make modern FRAM technology appear as a promising next step toward unified code/data computing. Some benefits of DRAM and flash storage place them ahead of FRAM in terms of cost effectiveness in a computing role. Currently, FRAM is finding use in certain niche applications such as parameter storage in various electronic laboratory equipment, handheld electronics, microprocessors, microcontrollers, and other areas. Recent advancements in the technology may allow FRAM to become a reasonable replacement for existing RAM and long-term data storage if cost effectiveness can match that of existing technologies.

Index Terms—ferroelectric, flash memory, random access memory (RAM), unified memory, perovskite crystal structure.


Some of the most common types of computer memory and long term data storage today are dynamic random access memory (DRAM) and flash memory storage, which is a form of electronically erasable programmable read only memory or EEPROM. These have emerged as two prominent technologies due in large part to their high storage unit densities. If more cells can be fit onto a smaller area, the storage capacity of a device increases without increasing the area required on a given wafer or substrate. This translates directly to higher cost efficiency, and cost per bit is very crucial in the competition between such technologies as all continue to scale down [11].

Some limitations of these technologies involve the speed of reading/writing, power consumption, write endurance, and the fact that they are different types of data storage/memory. The latter means that they can not be used interchangeably. Flash memory can be used for long term storage but is not suitable for data processing, as the read/write cycles are much too long (on the order of milliseconds)[1]. RAM on the other hand is fast enough for data processing, but must be refreshed periodically because it uses capacitors with a small discharge time. Thus, the two are clearly not suited for use in reverse roles.

 The actual design of a dynamic random access cell is a MOSFET with a capacitor connected to the drain to act as a controlling switch. The resulting device is referred to as a 1C1T memory cell. Some different orientations of such cells are shown in Fig. 1.

Fig. 1. A 1-transistor 1-capacitor memory cell shown for various existing configurations that offer different amounts of data storage per unit area [15].

 The cell allows for a “1” or “0” to be saved by the existence or lack of a charge on the capacitor at one transistor terminal. The storage of either a 1 or 0 is referred to as writing to the cell. Reading from the cell involves sensing either the charge or lack of charge in the capacitor when the cell is selected. With large arrays of these cells, multiple specific cells can be selected at a time in order to perform binary operations using other circuitry. This allows information processing in the form of these high and low voltage levels to act as the electronic language spoken by all processors, microcontrollers, computers, and electronic equipment.

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 The capacitors used are so small, however, that they can not retain a charge for long enough to be considered useful unless the stored value is refreshed periodically (typically every 64 ms or less) [15]. This is why DRAM cells must be constantly powered in order to retain their stored values and “remember” information. This is known as volatile memory. Thus, other technologies such as the aforementioned flash storage cell, magnetic storage, etc. are used for long term storage or in cases where critical data could be lost during a power failure.

 Flash memory involves a MOSFET with an added floating gate that allows electrons to become trapped and thus store a charge that can then be read as a “1” or “0”. This trapped charge remains in the floating gate region of the cell even when the power supply used to store it is removed. Thus, flash memory is nonvolatile. The trapped charge causes the threshold voltage of the MOSFET to change such that a check voltage will either be able to turn on the FET (erased) or not (programmed). This is shown in Fig. 2.

Fig. 2. The programmed and erased states of a flash memory cell showing the floating gate with and without trapped electrons [11].

 “To program the MOSFET, a large [drain to source voltage] is applied to accelerate the channel electrons to kinetic energies larger than the energy barrier between the silicon and the oxide. Thus accelerated electrons are referred to as hot electrons” [1]. Erasing requires forcing the trapped electrons to tunnel back into the substrate through the thin oxide barrier. These processes take a substantial amount of time relative to that of a DRAM read/write. They are therefore not fast enough to be used for data processing.

 Ferroelectric random access memory (FRAM or FeRAM) is a technology that could potentially be suitable for both roles. It is a form of nonvolatile storage, so can be used for long term information storage without a power supply. It also has high enough reading/writing speeds to push it into the realm of a potential data processing technology as well. Technologies capable of performing both of these tasks are known as unified memory.

“For decades researchers have been trying to find a nonvolatile technology that could rival volatile memory (namely DRAM) in terms of active power efficiency and read/write speeds. Such a device would allow for a machine with ‘unified’ memory, significantly simplifying the architecture of the modern PC. For that reason unified memory has been oft referred to as the ‘Holy Grail’ of memory technology” [15].

II.   Ferroelectric Random Access Memory

A.      Ferroelectric Materials

FRAM cells are essentially the same as DRAM, but with a ferroelectric capacitor replacing the metal-dielectric-metal capacitor. Ferroelectric capacitors have two stable states that can be used for the two binary levels of a digital memory and they can retain these states with no power supply. This is similar to ferromagnetic core memory, but with faster switching.

The most common material used for such ferroelectric technology is PZT (Pb {ZrTi}O3), perovskite-type structure (ABO3). The ability of the zirconium or titanium atom to move to one of two positions in the unit cell and stay there after respective application and removal of an electric field as shown in Fig. 3 gives the ferroelectric material its binary nature. The power consumption required for data storage in such a system is very low because no power is required to keep the atoms in the specified positions in the crystal. [7]

Fig. 3. A ferroelectric perovskite-type atomic unit cell with applied electric field and corresponding hysteresis loop [7].

B.      Ferroelectric + Semiconductor Memory Cell Operation

An array of these FRAM cells similar to that of DRAM can be used for computer memory applications as shown in Fig. 4. The main differences are the capacitor replacement and the driveline or plateline required by FeRAM.

Fig. 4. Showing DRAM and FRAM cells connected to wordline, bitline, and for FRAM, the driveline of a typical accessible memory network. [2]

The write and read processes of a FRAM cell are slightly different than that of a DRAM, because of the driveline. The hysteresis loop of the ferroelectric material makes it easier to view the process of “writing” specific polarizations to a cell. Fig. 5 gives a good depiction of writing a “0” or “1” to a cell.

Applying a voltage to the wordline acts to “turn on” the access transistor, allowing writing to the capacitor. Writing a binary “0” (positive polarization state) to a cell requires application of the positive power supply voltage, VDD, to the bitline with the driveline grounded and the wordline applied. For a “1” (negative polarization state), a positive voltage (VDD) is applied to the driveline with the bitline now grounded and the wordline again applied. There is a time constant corresponding to the capacitor just like in any standard double-plate capacitor application. This charging limits the write speed of the device. Removing the voltage from the wordline then cuts off access to the capacitor, leaving the written state undisturbed. [4]

Fig. 5. (a) Timing diagram for a write operation of the memory cell shown in Fig. 4. (b) The state sequence for the memory cell capacitor as a “1” or a “0” being written into the cell. The initial state of the capacitor , in both cases, does not affect the subsequent states of the capacitor. [4]

The reading sequence of an FRAM cell involves overcoming the parasitic capacitance of the bitline, so requires more care with the timing than does writing to the cell. The bitline is pre-charged to the 0 V level, and then the wordline is activated. The ferroelectric capacitor and parasitic capacitance in series act as a capacitor divider between the plateline and ground at the bitline.

When the plateline voltage VDD is applied, the voltage is divided between the two capacitors. Since the capacitance of the ferroelectric capacitor will vary based its “0” or “1” state, the capacitance and therefore voltage across the baseline capacitor will have two possible values.

Fig. 6. Parasitic bitline capacitance in series with the ferroelectric capacitor [4].

A sense amplifier on the bitline will bring the bitline level to either full VDD or 0 V depending on the voltage appearing across the parasitic capacitance. This process is destructive, as there is a voltage applied to the plateline just as during writing. Therefore, “the wordline is kept activated until the sensed voltage on the bitline restores the original state back into the cell and the bitline is pre-charged back to 0 V”. [4]

C.     Technology Benefits and Issues

The following discusses some of the benefits of and issues facing current attempts at making FRAM a viable unified memory device. In order for such a device to become the norm, the nonvolatile characteristics must outdo that of existing technologies at a lower cost, and the data processing parameters must outdo current RAM and processing technology.

In terms of read/write speed and endurance, power requirement, and unified memory capability, FRAM can easily compete with existing technologies. Fujitsu, a leading company in FRAM technology production, claim the following statistics for their products: FRAM is 30,000 times faster, provides 1 million times higher endurance, and offers 200 times lower power consumption than E2PROM as well as integrating excellent tamper prevention techniques. [7]

Texas Instruments claims the following: at equal throughput, FRAM consumes 250x less power than flash, up to 16 kb of unified FRAM configurable as data or code memory, FRAM maximum throughput 100x faster than flash maximum throughput while consuming 3x lower power than flash, and FRAM’s increased write endurance enables 10,000,000,000x longer memory life cycles than flash. It also mentions the fact that the crystal-based FRAM structure is more stable and not susceptible to radiation and offers more tamper/profiling protection. [10]

The potential for unified memory is probably the most attractive of the FRAM parameters. The low power characteristic comes not only from the low read/write voltage requirements, but the fact that power is not required to retain data states. This is attractive because if FRAM is to replace both RAM and a form of non-volatile storage for some application, the power consumption needs to be less than either of the two. The benefit comes from the ability to partition memory to both types of memory depending on the necessary application. This makes FRAM more immediately applicable to certain niche areas.

Microcontrollers for instance require non-volatile memory to store program parameters and fast, low-power memory for data storage and manipulation. Typically SRAM and flash are used together in microcontrollers. This requires integrating the two, and often scaling the two together based on the need for one. In such highly RAM-intensive applications as microcontrollers and running LCD displays, a real-time operating system, USB, or a wireless stack, a large amount of flash can go to waste. This translates to an often unnecessary increase in physical space. Partitioned memory between FRAM cells eliminates this issue. Dynamic partitioning allows for full customization of the FRAM cells to fit any application. [11]

Fig. 7. The dynamic partitioning of unified memory allows for switching between data and program memory as necessary for a given application. [11]

One reason that FeRAM has not already completely replaced all other forms of memory in all markets and applications is scaling. The number of memory cells or bits that can be fit onto a given area of a silicon chip corresponds to price per bit, and this plays a significant role in the marketability of such device technology. Until recently, many RAM and flash arrays have been able to be fabricated more densely than those of FRAM. This minimal cell size (and therefore density) is largely dependent on the amount of charge required to trigger the sense amplifiers of a given cell. This limit has been found to be somewhat larger for ferroelectric capacitor cells than for existing DRAM and others (Around 350-130 nm for FRAM versus 55 nm for DRAM). A recent study at the Université de Liège in Belgium on critical thickness for ferroelectricity in perovskite ultrathin films presents the idea that there may in fact be no critical limit [13]. The speed of performance compared to modern DRAM could also be an issue, but it is difficult to compare the two at their different minimum sizes.

Flash cells can store multiple bits per cell, and therefore have a higher bit density than FeRAM as well. Thus, the cost per bit is lower for flash as with DRAM. Improvements to the density of FRAM cells may allow them to advance into a broader range of applications in the near future.

Another downside to FeRAM 1C1T cells is the fact that the read cycle is a destructive process and thus, the data must be held long enough to be rewritten, as this slows down the overall process. This will be further discussed in terms of a specific current advancement known as FeTRAM.

D.     Current Advancements

Some of Fujitsu’s most recent (2013) developments include increases in the density of their existing FeRAM cells. In March of 2013, the company released 1Mbit and 2Mbit single-chip FRAM cells capable of reducing the necessary physical space from that of a typical EEPROM plus SRAM of the same data capacity with a backup battery. This works by reducing the number of components because no battery is required, and the two types of memory are shared on one chip. [8]

Fig. 8. Fujitsu’s FRAM cell saves space by removing the need for separate components and a backup battery. [8]

 A November 2013 release shows a similar money saving benefit of scaled down FRAM technology. Figs. 9-11 give Fujitsu’s explanation of the benefits.

Figs. 9-11. The cost decrease of FRAM cells compared to same capacity SRAM cells due to power supply cost and space. [9]

 These types of chips are causing FRAM to become more feasible and even the sensible choice for microcontrollers and other RAM intensive applications that still require non-volatile storage of machine parameters and other data upon shutdown or power failure. It will most likely continue to find its way into small consumer devices such as personal digital assistants, handheld phones, power meters, smart cards, and security systems – due to its fast memory and low power requirements.

Competing with the bit density of DRAM and flash cells continues to be the largest barrier to FeRAM overtaking the computer and data storage market as we every day users know it.

One interesting study at Drexel University presents a finding that would allow for significantly reduced density of ferroelectric cells with higher stability of states than the current state of the art. For ferroelectric materials to retain their state, they must be screened from undesirable electric fields that could change the polarization of the perovskite crystal. Typically, metal electrodes are used for this purpose. The Drexel team, however, found that molecules such as hydroxyl (OH) ions and hydrocarbons like carbonyl (COOH) actually work better and, interestingly, allow for much smaller stable nano-scale ferroelectric materials. [12]

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“…molecules enable a wire having a diameter equivalent to fewer than ten atoms to act as a stable and switchable dipole memory element,” reports one team member [12]. If fabrication of such materials can be perfected, the increased density could greatly improve on that of existing RAM for use in all avenues of computing. This could very well be the push needed to make FRAM the state of the art in all memory related applications.

Another advancement that attempts to tackle the destructive readout problem of capacitive FeRAMs is the FeTRAM or ferroelectric transistor random access memory. This refers to the fact that the nonvolatile charge is stored in ferroelectric material as part of a secondary transistor versus a ferroelectric capacitor. This allows for a slightly different circuit that in turn enables nondestructive readout of stored values.

Fig. 12. “(a) Comparison of the FETRAM cell with a commercial ferroelectric RAM cell. (b) Operation principal of a ferroelectric memory transistor. (c) Desired transfer characteristics of a ferroelectric memory transistor. (d) Energy band diagram of the FeFET corresponding to the two polarization states of the ferroelectric insulator. (e) A table showing the operation voltages for the FETRAM cell.” [16]

 The FeTRAM 1T1T cell proposed by Purdue’s article uses silicon nanowires and an organic polymer versus crystalline ferroelectric material. This is for compatibility with conventional silicon CMOS processes and implementation in a top-gated geometry. The polarization of the gate ferroelectric controls the conductance of the semiconducting channel.

The cell works by allowing the stored polarization to remain in the gate, where it has been written, as the channel of the so-called ferroelectric memory transistor is checked as opposed to the gate charge itself. Fig. 12 shows the read and write processes for each binary state of the gate ferroelectric. [16]

The control transistor is depletion-type, so for writing, the wordline is simply grounded and the desired voltage is applied to the bitline to polarize the memory transistor gate ferroelectric. For reading, the wordline voltage is applied to turn off the control transistor and the current through the memory transistor channel is then sensed. This current depends on the polarization of the gate ferroelectric, and the sensing leaves the state undisturbed, thus eliminating the need to rewrite it. [16]

 Advantages of the presented design include: no chemical reaction necessary for formation of ferroelectric film, small depolarization field with stable operation ensured, silicon nanowire CMOS compatibility, and scalability. Again, the nondestructive aspect stems from the location of the stored charge (the gate) being different than the location of the sensed current upon reading (the channel). The authors believe that this improvement to FeRAM could help ferroelectrics become integral to future IC technology. [16]

E.      Related Topics

One potential device that could compete with ferroelectric memory is MRAM or magnetoresistive random access memory. It seeks to use magnetism in a similar fashion that FRAM uses electric fields for polarization. It too presents the potential to act as unified memory if it can find a way out of solely niche markets. Some variations include T-MRAM or toggle MRAM and STMRAM or spin-torque MRAM.

Ferroelectrics are also being used in other semiconductor applications such as solar cell and optoelectronic devices. They have been looked at for potential use in adjusting the wavelength band gap of solar cell materials in order to maximize the frequencies of the solar spectrum that can be absorbed by a given photovoltaic material [14]. Some optoelectronics work focuses on the effects of radiation on polarization states of ferroelectrics. Many patents already exist for various circuit architectures and device designs involving these materials, and there are undoubtedly many more fields emerging for which they could present solutions or new applications.

III. Conclusions

Ferroelectric materials are being used for their ability to be placed in one of two states and retain that state until desirably changed. This has allowed them to find application in semiconductor technology as capacitive elements in MOSFET memory devices capable of acting as RAM and/or long term nonvolatile memory devices. They hold many benefits over existing RAM and ROM technologies with the main setback being the density of bits on a given device. With modern advancements, niche applications have begun to increase in number and devices have continued to catch up to existing technology in terms of desirable parameters. Promising research on the topic may very well produce devices capable of acting as unified memory in personal computers and all data processing and storing applications in the near future. Study of ferroelectrics has also led to advancements in other semiconductor, optoelectronics, and related fields.


[1]      S. Dimitrijev, “MOSFET,” in Principles of Semiconductor Devices, 2nd ed.. New York: Oxford Press, 2012, pp. 339-342.

[2]      A. Sheikholeslami, P. G. Gulak. (2000, May). A survey of circuit innovations in ferroelectric random-access memories. Proceedings of the IEEE [Online]. 88(5). pp. 667-672. Available: http://www.eecg.toronto.edu/~ali/papers/survey_proc.pdf

[3]      S. Thakoor and A. Thakoor. Jet Propulsion Laboratory, California Institute of Technology: Optically Addressed Ferroelectric Memory. Pasadena, CA. [Online]. Available: http://trs-new.jpl.nasa.gov/dspace/bitstream/2014/33777/1/94-0506.pdf

[4]      A. Sheikholeslami. (1997, July). FeRAM Tutorial [Online]. Available: http://www.eecg.toronto.edu/~ali/ferro/tutorial.html

[5]      A. Sheikholeslami. (1997, July). Selected FeRAM Patents [Online]. Available: http://www.eecg.toronto.edu/~ali/ferro/patents.html

[6]      M. Rouse. (2005, April). FRAM (ferroelectric RAM) [Online]. Available: http://searchstorage.techtarget.com/definition/FRAM

[7]      Fujitsu. (2000-2013). Ferroelectric Random Access Memory (FRAM) Product Overview [Online]. Availabile: http://www.fujitsu.com/us/semiconductors/memory/fram/

[8]      Fujitsu and phys.org. (2013, March). New 1 Mbit and 2Mbit FRAM products released by Fujitsu [Online]. Available: http://phys.org/news/2013-03-mbit-fram-products-fujitsu.html

[9]      Fujitsu and phys.org. (2013, November). Fujitsu releases new 4 mbit FRAM with non-volatile memory with SRAM-compatible parallel interface [Online]. Available: http://phys.org/news/2013-11-fujitsu-mbit-fram-non-volatile-memory.html

[10]   Texas Instruments. (1995-2013). FRAM Technology Overview [Online]. Available: http://www.ti.com/mcu/docs/mcuproductcontentnp.tsp?familyId=1751&sectionId=95&tabId=2840&family=mcu&paramCriteria=no

[11]   M. Stein. (2013, March). FRAM Tears Down Traditional Microcontroller Design Barriers [Online]. Available: http://eecatalog.com/8bit/2013/03/13/fram-tears-down-traditional-microcontroller-design-barriers/

[12]   Drexel University and phys.org. (2006, May). For a Bigger Hard-drive, Just Add Water [Online]. Available: http://phys.org/news66555256.html

[13]   inovacaotecnologica.com.br. (2011, September). FeTRAM: Non-volatile memory consumes 99% less energy [Online]. Available: http://www.inovacaotecnologica.com.br/noticias/noticia.php?artigo=fetram-memoria-nao-volatil&id=010110110929

[14]   Drexel University College of Engineering. (2013, November). Drexel and Penn Team exploring new paradigm for solar cell construction [Online]. Available: http://drexel.edu/engineering/news/archive/2013/November/DrexelandPennTeamExploringNewParadigmforSolarCellConstruction/

[15]   J. Mick. (2013, November). Coalition of 20+ Tech Firms Backs MRAM as Potential DRAM, NAND Replacement [Online]. Available: http://www.dailytech.com/Coalition+of+20+Tech+Firms+Backs+MRAM+as+Potential+DRAM+NAND+Replacement/article33826c.htm

[16]   S. Das and J. Appenzeller. (2011, September). FETRAM- an Organic Ferroelectric Material Based Novel Random Access Memory Cell. Birck and NCN Publications. Paper 778 [Online]. Available: http://docs.lib.purdue.edu/cgi/viewcontent.cgi?article=1778&context=nanopub


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