Field Programmable Gate Array based Digital Module

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Field Programmable Gate Array based Digital Module for Laser Frequency Stabilization

A.Rastogi1, N. Batra, S.De2, S.Panja and A. Sen Gupta



Frequency stabilized lasers are a crucial part in variety of atom-photon experiments such as atomic spectroscopy [1], laser cooling [2], probing the excited states of atoms [3] etc. Depending on the application, a stability in bandwidth from few MHz to sub Hz maybe required. It is therefore, essential to stabilize the frequency of a laser source to an absolute reference. Atoms or ultra stable fabry- perot cavities are used for this purpose [4]. Such stabilization schemes require electronic feedback / servo loops that allow for a correction in laser frequency deviation.

At CSIR-NPL, we are developing the first optical frequency standard in India with a single trapped Ytterbium ion (171Yb+). The project aims at trapping a single Yb ion in a Paul trap, laser cooling the ion to about mK temperatures for a precise frequency measurement of the ultranarrow octupole transition at a wavelength of 467 nm. The 171Yb+ frequency standard will require a simultaneous operation of five lasers for photoionization (399 nm), cooling (369 nm), repumping (935 nm and 760 nm) and probing the clock transition (467 nm) [5]. All the laser lights for our experiment would be produced from extended cavity diode lasers (ECDL) which drift in their frequencies due to environmental factors as temperature fluctuations and mechanical vibrations. Such drifting renders them unstable and hence, incorporating frequency stabilization systems becomes an essential requirement for precise frequency standards. In general a frequency stabilization of a laser, as for example using saturated absorption spectroscopy [6], requires the use of a frequency synthesizer for scanning and modulation of the laser frequency , lock-in amplifier for phase sensitive detection, low / high pass filters, and servo electronics for feeding control signals to the piezo / current terminals of the laser. Instead of procuring these analog modules for each of the lasers used in our experiment, we have taken an effort of developing them indigenously with an all digital control using field programmable gate array technology(FPGA). Hence, the functionality of all the hardware components can be embedded inside a single chip. In this paper, we present an FPGA based laser frequency stabilization design and show some preliminary results of the performance of the FPGA design modules.

An active laser feedback control loop mainly consists of a lock-in amplifier (providing phase sensitive detection) and a PID controller. As mentioned earlier, the controller generates correction signals that drive either a piezo attached to the laser cavity (as in case of ECDL lasers) or a current so as to adjust the laser frequency. Using FPGA’s the entire functionality of a laser frequency locking system can be implemented in a single chip with an area of few mm2 . Moreover, the truly concurrent nature of FPGA processing algorithms results in the FPGA design modules behaving like dedicated hardware circuits. Minimal use of hardware leads to lesser probability of picking up noise from the surroundings and also reduces cost. The FPGA’s could always be reprogrammed to incorporate extra adders, multipliers, filters i.e. they provide re-configurability.

FPGA’s are programmed using hardware description languages (HDL) such as Verilog-HDL or VHDL. We have implemented the laser frequency locking modules using VHDL. A schematic of various VHDL design modules implementing a laser frequency locking setup is shown in Fig.1. In our module, the FPGA chip (Xilinx Spartan 6 XCSLX16) receives an input signal either from an atomic spectroscopy or from a fabry-perot cavity[4] [6] .As shown in Fig.1, the acousto-optic modulator (AOM) does amplitude modulations of the laser signal resulting in variations in the intensity of light at the photodetector output. This modulated signal at the photodiode output is the derivative of the laser absorption signal i.e. proportional to the slope of a resonant feature. At a resonant frequency, the derivative signal is zero and on both sides of resonance, the derivative signal is 180 degrees in phase. This signal is the input to the FPGA systemwhich is then digitised using a 12-bit A/D converter (AD7476) and then passed through a high pass filter component. High pass filtering extracts the high frequency modulated features from the input signal. The filtered signal then goes to the input of the lock-in amplifier component (that implements phase sensitive detection). The reference signal for the lock-in amplifier comes from a VHDL component that implements a square DDS generator. A phase shifted version of this reference signal can be used by the AOM to amplitude modulate the laser signal. The lock-in amplifier component demodulates the modulated photodiode signal by multiplying it with the reference signal followed by low pass filtering thereby generating what is called an error signal. The error signal contains information as to which side of resonance, the laser frequency is. This signal is then processed by a PID controller component. The control signals generated by the PID component adjust the laser piezo and current signals in such a way so as to ensure that the error signal is always zero (which corresponds to a resonant frequency).Many a times, it is needed to just scan over the complete laser spectrum or to zoom in on a particular spectral feature. In this case, the PID action is disabled and a slow triangular scan signal (generated by a scan generator component) is fed to the laser piezo.All signals coming out of the FPGA are converted into the analog form via 12-bit DAC (DAC121S101). Moreover, to aid in the flexible tuning of locking parameters such as the lock-in gain, PID parameters, modulation frequency and phase, scan amplitude and frequency ; we are working on developing a graphical user interface (GUI) that would allow easy access to and modification of the parameters’ values inside the FPGA registers.

Figure 1: A schematic of an FPGA based closed loop laser frequency locking system. The experiment (atomic spectroscopy setup) and the electronic feedback servo (implemented using FPGA) are shown separately. On the right is shown the image of our FPGA development board with the Xilinx based FPGA chip at the centre. All the feedback components have been implemented as programmable VHDL modules .

Results of Some of the VHDL design modules

Operation of the individual VHDL modules as well as of the entire system as shown in Fig.1.have been verified, as for example, by observing the physical signals generated from the software implementation of lock-in amplifier, high pass filter , square DDS , scan generator etc. Here we are showing some of these results from our prototype setup.

Function Generation:We have implemented the functional behaviour of a square DDS generator and a triangular generatorby developing VHDL components for them. The output of the square DDS module is used as a reference signal for the lock-in detection stage and a phase shifted version of the reference signal is used in the amplitude modulation of the laser frequency by the AOM. The output of the triangular generator is used as a scan signal that drives the laser piezo for observing the laser absorption spectra over a wide range of frequencies. The signals generated from these VHDL components are shown in Fig.2 (a-b).

Figure 2 : (a) Shows a square wave of 20 KHz. This would be used as a reference signal for lock-in detection and for modulation by the AOM. (b) Shows a triangular scan of 10 Hz. This would be given to the laser piezo for scanning over a huge range of laser spectrum. (c) A sine wave of 100 Hz (red) was distorted by a high frequency pseudo random sequence resulting in a distorted signal (blue). The high pass filter module filters out the low frequencies and only high frequencies remain (green). For the response shown, the cut-off frequency was kept at 1 KHz.

High Pass Filter:Our high pass filter implements a first order IIR digital filter. As shown in Fig.1.the high pass filtering is needed to extract the high frequency amplitude modulations of the photodiode signal superimposed over the slowly scanned doppler absorption profile. As a way of verifying the functionality of this component, a low frequency sine way (100 Hz) was added to a pseudo-random number sequence (10-bit maximal sequence) which was generated at 1 MHz. The result is a highly distorted sine wave comprising high frequency fluctuations superimposed over a slowly varying sine wave. When such a signal is passed through the high pass filter component, the slow sinusoid is removed and only the fast fluctuations appear at the filter output. The cut-off frequency determines the signal at the output. The high pass filtering is shown in Fig.2 (c).

Lock -In Amplifier(Phase Sensitive Detector):Software implementation of a lock-in amplifier constitutes developing a binary multiplier in conjunction with a low pass filter. The binary multiplier multiplies an input signal with a reference signal The product is then passed to the low pass filter of a suitable cut-off frequency such that only the portion of the input signal that occurs at the reference frequency remain while the rest are filtered out. Moreover, the output of the lock-in amplifier (i.e. the low pass filtered signal) is directly proportional to the amplitude of the input signal and inversely proportional to the relative phase difference between the input and reference signals. Hence, for a given phase relationship, theoutput increases with increase in input signal amplitude. Similarly, for a fixed amplitude of input signal, the output is maximum when the reference and input signals are in phase (0 degrees) ; minimum when the two are out of phase (180 degrees) and averages to zero when they are 90 degrees phase separated. In Fig. 3, we demonstrate the amplitude and phase dependence of a lock-in amplifier circuit whose behaviour we have implemented in VHDL. The input signal to this component was an internally generated sine wave (5 KHz) and the reference signal was a square wave (5 KHz). From Fig.3 (a) , it is clear that as the amplitude of input signal (red) increases, the output signal (blue) shifts in the upward direction. For very small input signals (near to zero) , the output is also close to zero. From Fig.3(b), it is clear that the outputs of the lock-in amplifier are equal and opposite for phase separation of 0 (blue) and 180 degrees (red) between the input and reference signals. Moreover, the output signal averages to zero (green) when the corresponding phase difference is 90 degrees.

Figure 3 : (a),(b) and (c)show the dependence of the lock-in amplifier output (blue) upon the input signal (red). As the input signal amplitude increases from (a) to (c), the output level also shifts up(d) The mean of the lock-in amplifier is minimum when the phase difference between the reference signal and input is 180 degrees (red), maximum when the two are in phase (blue) and lies in the middle of the two extremes when the phase difference is 90 degrees (green).

Implementation of Frequency Locking Using Simulated Atomic Spectroscopy

Reference frequency from the laser driven atomic spectroscopy is currently not available due to in- availability of the laser.Therefore, to overcome this practical situation and test the FPGA based frequency locking modules,we describe an elegent simulation scheme for testing the closed loop FPGA based frequency control by simulating the atomic spectroscopy experiment described in [6] inside the FPGA chip itself. Essentially, inside the FPGA chip , there would be two main modules : (1) An experiment module that simulates a saturated absorption spectroscopy setup and (2) A feedback module that implements lock-in detection and a PID control action.

The experiment module would include three components : A laser piezo scan / control block that receives a voltage at its input and generates a frequency as a predetermined function of that voltage ; an atomic spectroscopy block which generates a derivative intensity profile as a function of the frequency from the piezo block . This in effect results in a derivative feature as a function of the input voltage to the piezo block. In addition , there is a modulation block that mimics an AOM driver. The block modulates the derivative signal in a certain algorithm such that the positive and negative cycles of the derivative signal are 180 degrees out of phase. The modulated signal then goes to the feedback block. The functions for voltage to frequency conversion and for frequency to derivative intensity conversion can be carefully chosen such that over one complete scan cycle , the derivative is zero at a particular voltage. The frequency corresponding to this voltage is the desired frequency and the feedback loop should effectively generate a voltage corresponding to this frequency by making the error signal zero. In this sense, the feedback module includes the basic components as high pass filter (for removing the slow doppler profile features from the modulated derivative signal) , lock-in amplifier (for phase sensitive demodulation of the derivative signal thereby giving an error signal) , a PID controller loop that fixes the error signal to zero and a scan generator that is used for observing the derivative over a complete scan range. Also, the reference signal for lock-in detection and the modulation signal from the AOM block are generated from a square DDS (implemented inside the feedback module). The output of the feedback module is either a scan voltage or a PID control voltage. In either case, the voltage signal goes to the piezo component of the experiment module. In this way, a closed feedback scheme is achieved as shown in Fig.4 At the time of writing this paper, the experimental module has been successfully implemented and we are able to simulate both the ‘scan’ and ‘lock’ conditions. In the scan mode, PID loop is disabled and the error signal is observed over a defined sweep span. Under the locking condition, the PID loop is enabled which pins the error signal down to the zero value. In this way, the system gets ‘locked’ to the frequency corresponding to zero error voltage. After the first order confirmation of frequency locking , we next plan to charcterise the lock quality , add facilities of scan offset and error signal offset to the existing simulation scheme as well as introduce noise into the system .

Figure 4 :(Left) A closed loop scheme simulating an atomic spectroscopy experimental setup and a feedback system both implemented inside the FPGA chip. (Right) A falling edge of scan signal (blue) with an error signal (red) simulating a spectroscopic feature is shown. A mirror image of the feature is observed on the rising scan edge . When in ‘lock’ mode, the error signal falls flat to zero voltage (green) demonstrating that the system gets locked to a particular frequency.


We have developed an all digital laser frequency stabilization module using field programmable gate array technology as against traditional bulky and expensive analog controllers. The VHDL design modules developed, imitate the functionality of typical hardware electronics used in a laser frequency locking system. The design modules were tested both individually as well as end to end through different testing methodologies. Some of the results were presented in this paper.Also, before incorporating the design modules into locking an actual laser, we have developed a scheme that simulates an entire atomic spectroscopy experiment with an electronic feedback system, both implemented inside the FPGA chip. We have successfully shown the ‘frequency locking’ action of our feedback modules through this scheme and plan to test them more rigorously by making enhancements in the existing simulation scheme.


S. De acknowledges support from Board of Research in Nuclear Sciences (BRNS) for funding this project under the project code :34/14/19/2014-BRNS/0309.


[1] K.B. Mac Adam, A Steinbach and C. Wiemann, Am. J. Phys. 60 , 1098 (1992).

[2] D. J. Wineland and H. Dehmelt,Bull. Am. Phys. Soc.20, 637 (1975).

[3] Chien-Nan Liu, Toru Morishita and Shinichi Watanabe, 2009 J. Phys.: Conf. Ser. 194 032014.

[4] W. Z. Zhao, J. E. Simsarian, L. A. Orozco, and G. D. Sprouse, Rev. Sci. Instrum. 69, 3737(1998).

[5] S. De, N. Batra, S. Chakraborty, S. Panja, A. Sen Gupta, .Current Science 106, 1348 (2014).

[6] Hall,J.L.;Hollberg,L.;Baer,T.;Robinson,H.G., ApPhL,39,680 (1981).

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