Speed control of dc motor using pll

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INTRODUCTION:

Feasibility Study, for final year project, is to establish whether the project is technically or financially feasible. The aim for the report is to ascertain an understanding between the student and the supervisor on the title of the project. It also requires establishing an understanding on the matter of aims and objectives. Such understanding is vital for the success of the project. The project work, that is to be undertaken, should be well planned so as to oversee the problems that lay ahead. Thus, the report delivers some insight into the planning phase. It gives aims and objectives for the project and explains various stages of work which will be involved. It further gives out a time plan that would direct the project itself through out the year. Such a planning would ensure the success of the project. Hence, the documentation of such a planning gives Feasibility Study.

AIMS:

Use the technique of Phase Locked based speed estimator to control the speed of a DC motor.

  • To create the overall system with,
  • A Phase Locked Loop (PLL) for the speed feedback.
  • A Phase Detection Logic that would compare the user speed (set point/frequency) to the motor's actual speed.
  • A method for detection of the speed of the DC motor.

OBJECTIVES:

  • A firm grip of theory on the Phase Locked Loop would clear all the concepts of such a technique and its industrial uses.
  • To devise a ‘Closed Loop Control System' that would enable the user to control the speed of the DC motor. It should be based on frequency domain design techniques (bode diagrams).
  • Detail work on the logic for Phase Detector or Synthesizer.
  • Research on how the Voltage Control Oscillator (VCO) works.
  • To use a suitable optical sensor that senses and returns the speed of the DC motor. The logic behind the signals, to and from the sensor, to be calculated.
  • Using Mat-lab for devising the transfer function and Tina for the circuit of the system.
  • Designing the hardware for the system.

TOPIC OVERVIEW:

A Phase Lock Loop (PLL) synchronizes an output signal with a reference or input signal in frequency as well as in phase.Phase Locked Loop is used in various communication networks to chuck out noise from various signals. Here it is used to control the speed of a DC motor. This is because PLL has a capability to control the manner in which the phase of the Voltage Control Oscillator (VCO) follows a changing reference phase. In other words it can be said that the designer can make the loop to follow quickly or sluggishly to the original input signal. This characteristic would enable users to control the speed of the DC motor.

WORK STAGES:

  • Literature Search
  • A brief research, comprising of study related to Phase Locked Loop and Control System such as closed loop system, was conducted to facilitate in writing the feasibility report. Extensive study in the mentioned fields must be obtained before the practical work is started. Research would be required to deal with the prospect of working out the components for the PLL Fig 2. Comprehensive research would also be required to create and build the circuits for the components in Fig1. Phase detection logic have to be devised that would require the time.

    Study related to transfer functions, of an order, that uses frequency domain should be done. Further study for the Bode diagrams would be needed. Simulink for the Mat-Lab and Tina would require some attention as they are the primary tool for testing. A research in optical sensors would be likely and the transfer of data, to and from the sensor, would need investigation. The speed of the motor and what is given by the user can be represented on a screen. An insight into it would be an option. The equipments provided, like PLL IC and VCO Unit, would require thorough study.

  • Block Diagram Design
  • Protocol Design
  • This phase of the work will be based on Mat-lab and Tina. The experiment would be simulation of the transfer function. Once the theory for the transfer function is completed, the derived function is written in Mat-lab and the corresponding bode graphs are investigated. These graphs would give a comprehensive illustration of the relevant components in the system. In other words it can be presumed, for the mat-lab simulation, that it would provide every bit of detailed information before the real circuit is built and the motor is accelerated.

  • Pseudo-Code
  • Pseudo-Code is a program code unrelated to the hardware of a particular computer and requiring conversion to the code used by the computer before the program can be used. This area of work deals with what is called extensive programming. The project would not require such level of programming. It would only require the simulation for the transfer function via using Mat-lab. Hence learning the software would be crucial for the success of the project.

CAPITAL RESOURCES:

The total budget allocation to the project is £ 50. The equipment used within the project are given to be,

  • Phase Locked Loop (PLL) IC.
  • Op-amps ICs
  • VCO Unit and Counter
  • Usual lab equipment
  • Software
  • Mat-Lab 7.0 ( Simulate the transfer function of the control system)
  • Tina 6.02 (For designing and testing the circuits)

PROJECT TIME PLAN

REFERENCES:

  • http://dictionary.reference.com/ for definitions
  • http://hem.passagen.se/communication/fm_pll_vco.html an insight for the VCO unit and PLL unit.
  • Phase-locked loops : design, simulation, and applications / Roland E. Best.(621.3815364 BES)
  • Phase-locked loops : theory and applications / John L. Stensby (621.3815364 STE)
  • Phase-Lock Basics/ William F.Egan(621.3815364 EDA)
  • The art of Electronics, Second Edition/ Paulhorowitz Winfield Hill.
  • Phase Locked Loops, 1993/ J.B.Encinas
  • Modern Control System Theory and Design, Second Edition/Stanley M.Shinners
  • Speed Control of a stepper motor using PLL, University of Hertfordshire,2005/ Anthony Richard
  • Phase Locked Loops, University of Hertfordshire,2003/ Mihir Shah
  • Design of a phase locked loop for coherent optical demodulat, University of Hertfordshire,2005/ Hua Zhou
  • ‘The control second order system fo PLL', University of Hertfordshire,2006/ Mingshu
  • http://dictionary.reference.com/ for definitions
  • http://hem.passagen.se/communication/fm_pll_vco.html an insight for the VCO unit and PLL unit.
  • Phase-locked loops : design, simulation, and applications / Roland E. Best.(621.3815364 BES)
  • Phase-locked loops : theory and applications / John L. Stensby (621.3815364 STE)

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