Master slave flip flop

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Flip Flop :

A Flip Flop is backbone of the digital electronics. It is one bit memory unit structure. It has two stable states and thereby is capable of serving as one bit of memory.

A flip-flop is generally controlled by one or two control signals and/or a gate or clock signal. The output often includes the complement as well as the normal output. As flip-flops are implemented electronically, they require power and ground connections.

Introduction to Basic Flip-Flop Circuit :

Two NAND gates or two NOR gates can be used to construct Flip flop. Each flip-flop has two outputs, Q and Q', and two inputs, set (1) and reset (0). This type of flip-flop is referred to as an SR flip-flop or SR latch. Conditions are sa follows :

When Q=1 and Q'=0, it is in the set state (or 1-state). When Q=0 and Q'=1, it is in the clear state (or 0-state). The outputs Q and Q' are complements of each other and are referred to as the normal and toggled outputs, respectively. The binary state of the flip-flop is taken to be the value of the normal output.

If a 1 is applied to both the set and reset inputs of the flip-flop in figure below both Q and Q' outputs go to 0. This condition opposes the fact that both outputs are complements of each other. In normal operation this condition must be avoided by making sure that 1's are not applied to both inputs simultaneously.

(a) Logic diagram

(b) Truth table

Basic flip-flop circuit with NAND gates

The NAND basic flip-flop circuit in figure operates with inputs normally at 1 unless the state of the flip-flop has to be changed. A 0 applied momentarily to the set input causes Q to go to 1 and Q' to go to 0, putting the flip-flop in the set state. When both inputs go to 0, both outputs go to 1. This condition should be avoided in normal operation.

Master-Slave Flip-Flop


A master-slave flip-flop is constructed from two seperate flip-flops. One circuit serves as a master and the other as a slave..The master flip-flop is enabled on the positive edge of the clock pulse CP and the slave flip-flop is disabled by the inverter. The information at the external R and S inputs is transmitted to the master flip-flop. When the pulse returns to 0, the master flip flop is disabled and the slave flip-flop is enabled. The slave flip-flop then goes to the same state as the master flip-flop.

Logic diagram of a master-slave flip-flop

In addition to these two flip-flops, the circuit also includes an inverter. The inverter is connected to clock pulse in such a way that the inverted CP is given to the slave flip-flop. For example, if the CP=0 for a master flip-flop, then the output of the inverter is 1, and this value is assigned to the slave flip-flop. In other words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop.

A master-slave flip flop can be constructed using any type of flip-flop which forms a combination with a clocked RS flip-flop, and with an inverter as slave circuit.

An RS master-slave flip-flop consists of two RS flip-flops; one is the master flip-flop and the other a slave. The inverted CP is given to the slave flip-flop. Now when CP=0, the master flip-flop is disabled. So the external inputs R and S of the master flip-flop will not affect the circuit until CP goes to 1. The inverter output goes to 1 and it enables the slave flip-flop. The output Q=Y and Q'=Y'.

When CP=1, the master flip-flop is enabled and the slave flip-flop remains isolated from the circuit until CP goes back to 0. Now Y and Y' depends on the external inputs R and S of the master flip-flop.

Suppose that the flip-flop is in a clear state and no clock pulse is applied to the circuit. The external inputs given are S=1 and R=0. This input will not affect the state of the system until the CP=1. Now the next clock pulse applied should change the state to SET state (S=1, R=0). During the clock pulse transition from 0 to 1, the master flip-flop goes to set state and changes the output Y to 1. However this does not affect the output of the system since the slave flip-flop is isolated from the system (CP=0 for slave). So no change is observed at the output of the system.

When the CP returns to 0, the master flip-flop is disabled while the slave is enabled. So the information from the master is allowed to pass through to the slave. Since Y=1, this changes the output Q to 1.

The output of the flip-flop and the external input with same clock pulse can be changed in case of the master slave flip flop. This is because the external input S can be changed at the same time while the pulse goes through its negative edge transition. When CP=0, change in external input S would not affect the state of the system. From this behavior of the master slave flip-flop it is quite clear that the state change in flip-flops coincide with the negative edge transition of the pulse.

Negative edge transition means an inverter is attached between the CP terminal and the input of the slave. In positive edge triggered master slave flip-flops an additional inverter is attached between the CP terminal and the input of the master. Such flip-flops are triggered with negative pulses. Negative edge of the pulse affects the master and positive edge affects the slave.

Timing Diagram

The timing relationship is shown in figure and is assumed that the flip-flop is in the clear state prior to the occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on the negative transition of the clock pulse. Some master-slave flip-flops change output state on the positive transition of the clock pulse by having an additional inverter between the CP terminal and the input of the master.

Timing relationship in a master slave flip-flop

Need for implementing Master Slave Flip Flop:

Race Around Condition:

Consider a JK Flip flop.The excitation table of this FF is as given here :

J K Qn+1

0 0 Qn

0 1 0

1 0 1

1 1 Qn C (toggle of Qn)

Suppose that a clock of certain frequency is fed to the flip flop, and consider the case of J K being 11. The propagation delay of flip flop is very very less than the clock pulse time.The flip flop continues toggling the output an unpredictable number of times, thus leading to the final output after the pulse time of the clock is completed. At the end the clock pulse, the value of Q is uncertain.This continuous toggling of output when clock is HIGH is known as Race Around condition. This can be eliminated by

1. Clock time should be less than the propagation delay time of the latch.

2. By using Masterslave JK Flip flop.

Pulse-Triggered Master-Slave

These flip-flops are constructed from two separate flip-flops. The term pulse-triggered means that data are entered into the flip-flop on the leading edge of the clock pulse, but the output does not reflect the input state until the trailing edge of the clock pulse. This is due to the master flip-flop being rising edge triggered and the slave flip-flop being falling edge triggered as illustrated in the figure below.

R-S Master-Slave configuration

Master-Slave J-K Flip-Flop

A master slave flip flop is a cascade of two S R flip flops with feedback from the outputs of the second to the inputs of the first. Positive clock pulses are applied to the first flip flop and clock pulses are inverted before these are applied to the second flip flop.

The logic symbol for the master-slave flip-flop only indicates the initial inputs to the master and the outputs from the slave as indicated by the J-K master-slave flip-flop shown in figure

Logic symbol for J-K master-slave flip-flop









Hold (no change)

















J-K Flip-flop Truth Table

Let us now examine the operation of the master-slave J-K flip-flop as shown in figure

Operation of master-slave J-k flip flop

Whe CK=1, the first flip flop is enabled and the outputs Q and Q(toggle) respond to the J & K according to its truth table.At this time the second flip flop is inhibited because its clock is LOW. When CK goes LOW, the first flip flop is inhibited and the second flip flop is enabled, because now its clock isHIGH.Since the second flip flop simply follows the first one it is referred to as slave and he first one as the master.


Master-slave D flip-flop

Consider the following terms :

RIPPLE THROUGH: An input changes level during the clock period, and the change appears at the output.

PROPAGATION DELAY: The time between applying a signal to an input, and the resulting change in the output.

These problems can be overcome by masterslave D Flip flop.

A master-slave D flip-flop is created by connecting two gated D latches in series, and inverting the enable input to one of them. It is called master-slave because the second latch in the series only changes in response to a change in the first (master) latch.

The term pulse-triggered means that data is entered on the rising edge of the clock pulse, but the output does not reflect the change until the falling edge of the clock pulse.

It responds on the negative edge of the enable input usually a clock.

For a positive-edge triggered master-slave D flip-flop, when the clock signal is low (logical 0) the "enable" seen by the first or "master" D latch (the inverted clock signal) is high (logical 1). This allows the "master" latch to store the input value when the clock signal goes from low to high. As the clock signal goes high (0 to 1) the inverted "enable" of the first latch goes low (1 to 0) and the value seen at the input to the master latch is "locked". Nearly simultaneously, the twice inverted "enable" of the second or "slave" D latch transitions from low to high (0 to 1) with the clock signal. This allows the signal captured at the rising edge of the clock by the now "locked" master latch to pass through the "slave" latch. When the clock signal returns to low (1 to 0), the output of the "slave" latch is "locked", and the value seen at the last rising edge of the clock is held while the "master" latch begins to accept new values in preparation for the next rising clock edge.

By removing the leftmost inverter in the above circuit, a D-type flip flop that strobes on the falling edge of a clock signal can be obtained. The truth table obtained is as follows:














* If the circuit is set, it means output = 1

* If the circuit is reset, it means output = 0

* Flip-flops have two output Q and Q'.

* Due to time related characteristic of the flip-flop, Q and Q' are usually represented as :

o Qt or Q: present state

o Qt+1 or Q+: next state


* When using a real flip-flop, the following information is needed to be considered:

* propagation delay (tpLH, tpHL) - time needed for an input signal to produce an output signal

* minimum pulse width (tw(min)) - minimum amount of time a signal must be applied

* setup and hold time (tsu, th) - minimum time the input signal must be held fixed before and after the latching action.


* A flip-flop is used to store one bit, or binary digit, of data.

* Any one of the flip-flop types can be used to build any of the others.

* Many logic synthesis tools will not use any other type than D flip-flop and D latch.

* Level sensitive latches cause problems with Static Timing Analysis (STA) tools and Design For Test (DFT).

* Many FPGA devices contain only edge-triggered D flip-flops

* The data contained in several flip-flops may represent the state of a sequencer, the value of a counter, an ASCII character in a computer's memory or any other piece of information.

* One use is to build finite state machines from electronic logic. The flip-flops remember the machine's previous state, and digital logic uses that state to calculate the next state.

* A chain of T flip-flops will function to divide an input in frequency by 2n, where n is the number of flip-flops used between the input and the output.

* Master Slave Flip Flop is useful in eliminating race around condition.

* They are used in both asynchronous and clocked sequential systems.



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