# Literature Review Of Low Noise Amplification Engineering Essay

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Published: *Mon, 5 Dec 2016*

The main function of low noise amplifier (LNA) in communication system is to amplify very low signals without adding noise. At the same time it must be able to amplify the large signal without introducing any distortions. Hence the goal in designing LNA is normally governed by several objectives. There are the ability to provide high gain which is measured in term of Voltage Gain () or Power Gain (), to attain the minimum noise figure (NF), to reduce nonlinearity and to deliver tolerable matching at the input and output ports. Linearity is measured by two types of characteristics, an Input 1-dB Compression Point (IP1dB) and Input-Referred Third-Order Intercept Point (IIP3). The matching impedance is to meet 50â„¦ at the input and output, which is measured by input and output reflection coefficient, and respectively. Generally, the goal of low noise amplifier (LNA) design is to achieve simultaneous noise and input matching at any given amount of power dissipation (Nguyen et al., 2004).

## 2.2 Scattering Parameters

In microwave frequencies, S-parameter refers to the way in which the traveling currents and voltages of a two-port network.

Figure 2.1 Two port network setup to measure S-parameters

From Figure 2.1, a1 and a2 are incident wave at the Port1 and Port2 accordingly. b1 and b2 are reflected wave at Port1 and Port2 respectively. The equations relate the S-parameters with the incident and reflected wave are

(2.1)

(2.2)

(2.3)

refers to the signal reflected at Port1 for the signal incident at Port1 which indicates input return loss

(2.4)

refers to the signal exiting at Port2 for the signal incident at Port1 which indicates the forward power gain

(2.5)

S-parameter convention always refers to the corresponding port first.

refers to a signal exiting at Port2 for an incident signal at Port2 which indicates the output return loss

(2.6)

refers to a signal exiting at Port1 for incident signal at Port2 which indicates reverse isolation.

(2.7)

## 2.3 Linearity Measures

Linearity of the LNA is very important. Besides to amplify extremely low signal level without adding noise, LNA also take responsibility to amplify the large signal level without any distortion. The most typical measures of linearity are the third-order intercept points IIP3 and 1-dB compression points P1dB. IIP3 and IP1dB are measuring the linearity of the receiver part while OIP3 and OP1dB are measuring the linearity of the transmitter part.

Figure 2.2 P1dB and IIP3

Compression point 1dB is the input signal level that caused the small-signal gain to drop 1dB (E.V.Balashov et al., 2005) . At this point, if the signal input power is increase, the gain will further reduced and circuit no longer linear. Figure 2.2 shows the plotting of the output power over the input power. IP1dB is the input power and OP1dB is the output power corresponding to the 1-dB compression point.

Intermodulation product

When the desired signal frequency is interfered by the strong unwanted signal, it will produce inter-modulation (IM) which caused non-linearity of the LNA. IM can occur when the interference present at the input of the circuit together with the desired signal. Because of the non-linearity of the LNA, the interfering signal will also consists in the sum and difference of frequency terms at output together with the preferred signal and also together with the preferred’s signal harmonics. Some of these terms can lie in the desired signal bandwidth consequently can harm the preferred signal.

. These products are the sum and difference of multiples of the fundamental signal. Equation below shows the series expansion of multiplying two signals f1 and f2. Notice that the order is characterized by the sum of the fundamental factors. From Jasper;

Pout = a1f1 + a2f2 +a3(f1 ± f2) + a4(f1 ± 2f2) + a5(2f1 ± f2) + a6(2f1 ± 2f2) +… + aâˆž(âˆžf1 ± âˆžf2) (2.4.0)

a1f1 + a2f2 +a3(f1 ± f2) is a fundamental

a3(f1 ± f2) is a second order

a4(f1 ± 2f2) + a5(2f1 ± f2) is a third order

a6(2f1 ± 2f2) is a fourth order

aâˆž(âˆžf1 ± âˆžf2) others

many of the spurious signal is far away from the fundamental signal. It will not give any problem. The third order signal is close to the fundamental signal that will cause a distortion to the output. From Figure 2.2, it can be observed the curve for 1dB compression point and third order interception point are linear with different slopes. The curves then will intersect at a point and this intersection is IIP3 (corresponding magnitude when refer to input power axis) and OIP3 (corresponding magnitude when refer to output power axis). IIP3 indicates the maximum input power of an LNA before the third order IM products effect the performance of the circuit. OIP3 represents the maximum output power that LNA can produce before it degrades. A higher IIP3 will give the lower IM products for a given input power. Hence, LNA with the higher the IIP3, will have better linearity.

## Inductively Degenerated CS Amplifier

This topology offers resistive input impedance with no participating of resistor. The advantage of this circuit is it does not bring with it the noise of an ordinary resistor. The existence of the resistor will lead to the present of noisy resistance in the signal path and the circuit will suffer noise figure (NF) degradation (Noh, 2009). The topology of inductively degenerated CS LNA is shown in Figure 2.4:

Figure 2.4 Inductively degenerated CS amplifer (Lee, 2001)

Inductively degenerated property can be exploited to provide specified input impedance without degrading the noise performance of the amplifier (Lee, 2001). The small signal model in Figure 2.3.2 below is used to calculate the input impedance. From (Noh, 2009):

Figure 2.4 Small signal model for the inductively-degenerated CS amplifier

(2.41)

## ,

(2.42)

Input impedance is a series RLC network with a resistive term that is directly proportional to the inductance value (Lee, 2004). At resonance, the real term in take in . Thus, this degenerated inductor is utilized for input matching. assists to achieve an appropriate input impedance which is normally matched to 50. will resonate with and bring the input frequency to be worked at the operating frequency. At resonance, from (Noh, 2009):

This topology has an advantage of greatest noise performance because it has no resistor in its structure.

## 2.5 Inductively-degenerated Cascode LNA

Figure 2.3.3 shows the inductively cascode LNA. Transistor 1 is inductively-degenerated common source amplifier while transistor 2 is common gate amplifier and inductors Lg and Ls are used for input impedance matching of the LNA to the 50â„¦ (Manku, 1998). The advantages of this topology are stated as following:

Figure 2.5 Single-stage open-drain inductively-degenerated CS LNA (Shaeffer & Lee)

The cascode topology combines the high input resistance and large transconductance offered by a CS amplifier with the current-buffering capability and good high-frequency response of a common-gate amplifier (Sedra and Smith, 2004).

Another important advantage is that the cascode able to reduce the effect of M1’s gate-to drain capacitance, i.e. the Miller effect (Noh and Zulkifli, 2007). This happen due to the input resistance of is much smaller than output resistance of the CS .

The advantage of the open-drain connection is that Ld with the node capacitance at the drain of M2 will resonate at the operating frequency and provide more band pass filtering. Besides this, a very small voltage drop across Ld due to its series resistance makes this configuration attractive for low power design (Noh, 2009).

The biasing circuit for this LNA is form by which is connected to as a current mirror. Both these transistors ratio will define the current operating in the cascode circuit. Appropriate selection the width of will determine the voltage across gate-source of . is functioning to isolate the signal path from the current mirror. Therefore the input signal will be ac coupled to the LNA input. is not a big concern as long as it is greater than the input impedance of the cascode LNA.

The involvement is such as mention in the previous section before. This degeneration inductor helps the matching at the input stage to be achieved at 50â„¦ effectively. It also contributes to the LNA’s gain. and work together to tune the input to the desired frequency.

## 2.6 Noise

Noise factor is define as

(2.50)

SNRin and SNRout are the signal-to-noise ratio at the input and output accordingly. The noise figure (NF) is the common measurement of noise performance.

## Noise in MOS

One of the factor that contributes to the total noise in the MOS is the thermal noise,which is resulting from the electrical noise arising from the random of electronics in a conductor. MOS is essentially a voltage-controlled resistor, it demonstrates thermal noise. Another source of noise in MOS device is a distributed gate resistance RG. It can be modelled by a series resistance in the gate circuit and an accompanying white noise generator . The distributed gate resistance is given by (Shaeffer&Lee,1997)

(2.51)

is a sheet resistance, W and L are the total gate width and channel length respectively in the devicen n is the number of gate fingers used to lay out the device. Hence, by interdigitating the device this kind of noise can be reduced.

Figure 2.6: Equivalent circuit for the input stage noise calculations for an inductively-degenerated LNA (Shaeffer & Lee,1997)

Figure 2.7 shows the input stage of the inductively-degenerated cascode LNA. This stage is the major contributor to the total noise of this circuit. From the Figure above, RS, RLg and Rg represent the source resistance, series resistance of Lg and the gate resistance of CMOS device. , and are representing the noise source for the source resistance, internal resistance of Lg and Rg accordingly. In this representation, Lg is assumed not contributing anything to the noise of circuit as its inductance is small. Finally is the channel thermal noise of the device. Through the noise figure expression getting from the Figure above, the noise can be reduced by having smaller width device. However,by using a smaller device indirectly the Cgs will also smaller. Therefore to maintain a constant operating frequency, Lg has to be made large. Unfortunately, a higher Lg will increase the noise unless Qind is high. The circuit technique to solve this constraint, Power Constrained Simultaneous Noise and Input Matching (PCSNIM) can be employed.

## 2.7 Classical noise matching (CNM) techniques

## LNAs with noise and input matching techniques

In this technique, the LNA is designed for minimum NF by presenting the optimum noise impedance to the given amplifier, which is typically implemented by adding a matching circuit between the source and input of the LNA (Nguyen et al.,2004). There is no degeneration inductor in this circuit. Yet the amplifier can experience a significant mismatch at the input if there is mismatch between input impedance and complex conjugate of the input impedance (Nguyen et al.,2004). As a result, the tradeoff between gain and noise performance is inescapable. Figure 2.7 shows the schematic of CNM cascade LNA and the small signal model which shows the source of noise from the circuit. The CG transistor’s effect on the noise and frequency response in this circuit is neglected for simplification as well as parasitic capacitance.

(a)

(b)

Figure 2.7 (a) The CNM cascode LNA (b) The small-signal model with noise sources of CNM cascode

Mean -squared channel thermal noise current is given by

(2.8.0)

is the D-S conductance at V

k = Boltzman constant,

T = absolute temperature

Î”f = bandwidth

Ï’ = 1 at V and 2/3 when the transistor is in saturation. The Ï’ increases at high and and can be more than two in short-channel devices (Nguyen et al.,2004)

Regarding to the channel thermal noise, there will be fluctuation in the channel potential. This fluctuation will be capacitively coupled to the gate terminal which causing a noisy gate current.

The mean-squared gate-induced noise current

(2.8.1)

Where

Î” is a constant with value of 4/3 in long channel devices (Lee,2001). represents the gate-source capacitance of the input transistor, which is been ignored for simplification. Since the gate-induced noise current has a correlation with the channel noise current, c their relationship is defined as (Lee,2001)

(2.8.2)

From Nguyen et al., (2004) the noise parameter for the cascode amplifier is expressed as

Noise Resistance:

(2.8.3)

Optimum noise admittance:

(2.8.4)

Minimum noise factor:

(2.8.5)

and =1 for long channel devices. From Figure 2.8.1(b) it can be seen that the input admittance is purely capacitive, . By comparing the complex conjugate of this admittance with Yopt equation, it can be seen the Yopt contains a real term which not exist in Yin. Thus, this shows that the input matching and minimum noise figure cannot be simultaneously achieved through this technique.

## 2.8 Simultaneous Noise Input Matching (SNIM)

In this method, the feedback technique is implemented by using inductor, . Feedback techniques are often adopted in designing low noise amplifier in order to shift the optimum noise impedance, to the desired point (Nguyen et al., 2004). Figure 2.8 below shows the schematic of SNIM.

VDD

(a)

Figure 2.8 (a) The SNIM cascode LNA

This kind of input matching widely used for narrow-band applications and for large transistor with a high power dissipation and high frequency of operation. From the equation (2.8.3), problem can occur if the size of the transistor is small, giving low gm and Cgs (Darabi & Abidi,2000). This is also makes SNIM topology not suitable for circuits requiring low power consumption and device having small transition angular frequency. If the circuit operates under these conditions, the minimum noise factor will be higher than the Fmin of the typical CS amplifier. Therefore the implementation of SNIM will be inadequate. From Nguyen et al.,(2004)

.(2.8.2)

(2.8.3)

-s (2.8.4)

(2.8.5)

(2.8.6)

(2.8.7)

Equation 2.8.7 shows there is real term in Zin equation. The amendment to the circuit that includes Ls in the cascode will be very significant to bring Zin close to .

Simultaneous noise and input matching will be possible with these conditions (Nguyen et al.,2004)

(2.8.8)

(2.8.9)

(2.8.10)

(2.8.11)

With the SNIM topology, the simultaneous noise and input matching would be achieved as long as the Equations 2.8.9,2.8.10 and 2.8.31 are fulfilled and Equations 2.8.5 to 2.8.7 are valid. However, from equation Zopt, the operating frequency is low or/and when the size of the device is small, the real part of Zopto will be high. With the certain amount of , the increased real part of Zopto due to the reduction in size will involve a large Ls to fulfill Zopt=Zin* . There will be an issue if Ls is made larger than a certain value that leads to the expression of Fmin=Fmino becomes inacceptable. Hence, the utilizing of SNIM is undeserving.

## 2.9 PCNO technique

In this technique, both gain and noise matching can be achieved simultaneously at any specified power dissipation. It can be realized by appropriate selection of Ls at any given Cgs. With the fixed drain current, there is available the transistor width that can have low NF result. The width of an optimum device is (Lee,2001,2004):

(2.8.30)

is the quality factor of LNA’s input circuit that leads to the power-constrained minimum noise figure (Lee,2001,2004) It is defined as:

(2.8.31)

Where |c|=0.395 and

Mentioning by Lee (2004), a more exact analysis discovers that the optimum value is normally closer to 4.5 for 0.35 µm process that was realized on Lee’s design. However, the noise figure is insensitive to value of between 3.5 and 5.5 as the noise figure is only change by 0.1 dB (Lee,2001). For 0.18 µm process, the noise contours that were plotted shows that for a fixed NF, a variation of Qs from 3.5 to 4.5 will result in constant power dissipation(Noh, January 2009).

With a device that has width , the noise figure obtained within the power constraint is (Lee,2001,2004):

(2.8.32)

## 2.10 PCSNIM LNA

The last noise and input matching technique is PCSNIM. This technique allows simultaneous noise and input matching at low power implementations. SNIM technique does not permit this. In PCSNIM, the additional Cex is placed in parallel with Cgs. Through this technique, the noise and input matching still can be achieved even the transistor is small. It can be done by manipulating the value of Cex . the schematic and small signal model with noise sources that represents the PCSNIM topology is shown in Figure 2.10

(b)

Figure 2.10 (a) The PCSNIM cascode LNA with additional capacitor across the input transistor. (b) The small signal model with noise sources of the PCSNIM LNA (Nguyen,2003)

(2.10)

(2.11)

(2.12)

Noise parameter

(2.13)

From the expression getting from small signal circuit, Cex can be manipulating to maintain optimum impedance without having to increase Ls.

## 2.11 PCSNIM with output buffer

This technique is used to tackle an output matching at the output stage. The employment of LC circuit is replaced with an output buffer. Instead of using L-C network that requires large space due to the inductors is huge passives, there are two capacitors and transistors with a resistor will take place to perform the task. Figure 2.11 shows the PCSNIM with output buffer LNA.

Figure 2.11 The modified PCSNIM with output buffer LNA

A common-drain transistor is used to perform as the buffer, shown as M4. M5 is operating as current-source. Ld is to resonate with Cd, Cgs_M4,C0,Cgd_M5 and the bondpad to provide tuning at the 2.14GHz. Cc1 is the coupling capacitor that will isolate the biasing of the buffer from the cascode. To perform the function, the large capacitor is needed. Ro is to isolate the signal path from the current mirror, same function to R2.

The transistor M2 has a width of half of the width of M1. In term of linearity performance, M2 has more influenced as compared to M1. Therefore, if the linearity of the LNA needs to be boosted, the M2 should be the one to be modified. From the study performed by Guo&Huang, it was discovered that the IIP3 of M2 improves with the increase of DC biasing of M2. By increasing the supply voltage, the DC biasing if this transistor also will increase but indirectly it will increase the total power consumption of the whole circuit. One of the ways out is to increase the DC bias of M2 by optimizing the width at a suitable bias voltage. This method can be considered to ensure it does not affect the total power consumption of the whole circuit as well as good noise performance.

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