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Scrambling is a digital encoding technique that is used in modern data communication schemes and can principally provide aid in retrieving information from received data enhancing synchronization between the transmitter and the receiver. In digital systems it is common to encounter long sequences of 1s and 0s making it difficult for the receiver to retrieve timing information . As a result, the input device randomizes data but the receiver fails to obtain them in their consistent countenance. Adaptive equalization, clock recovery and variations of received data are difficulties that can be eliminated if the bit sequence is randomized and that is a procedure that a scrambling device can guarantee.
Scrambling techniques can be divided into two classes; additive scrambling and multiplicative scrambling. In the first case scramblers tend to use modulo-2 addition in order to transform the input data stream and attain synchronization of both ends by using a sync-word. A specific pattern is placed at the beginning of each frame that’s being sent and can be decrypted only by the receiver [googlebook]. On the other hand, multiplicative scramblers are named that way because they implement a multiplication between the input signal and the scrambler transfer function. This class of scrambling is also referred as self-synchronizing scrambling because they don’t need a sync-word for synchronization [googlebook].
Scramblers are used in a variation of applications. In security systems for example, they can encrypt data and send them into a channel sequence with safety. That way they can’t be intercepted on the way to the receiver and can be decrypted by the descrambler installed at the terminal. The main purpose of scrambling devices in data communication systems is to make sure that information from data that has been received from a terminal include timing material that aid the synchronization of both ends such as two modems .
2. Understanding scrambling
Accuracy in data communications is highly considerable as otherwise could lead to data loss. For example, a huge network malfunction could take place considering modem’s scramblers in the infrastructure of a country’s stock market were data must be represented live. This failure could be catastrophic considering the fact that data is being transmitted and received from all over the world. Thus, an errorless communication system is essential with quite accurate timing devices appended to it. This could be easily feasible if communication networks were simply constructed but at present numerous devices are being attached and large data sets are being processed in complex communication grids making it difficult to achieve or even approach the objective of punctual contact.
2.1 Additive (Synchronous) scrambler
Data scrambling basically uses fixed binary sequences that mostly resemble a random signal. Feedback generates and provides shift registers with these sequences that afterwards are being exploited by modulo 2 adders. Shift register consists of flip-flops which are placed in a specific order in which they receive the bits and gradually forward them to the next flip-flop in a cascade formation [DTS]. Feedback connections in some stages include taps in which the tapped signals are added modulo 2 and fed back to the first flip-flop. In figure 1 flip-flops 2 and 5 are mod-2 added, flip-flops 1 and 2 are shift to 2 and 3 until they gradually land at flip-flop 4 and 5 and mod-2 output reverts back to flip-flop 1. The result of this shift register will go through thirty-one different states and then it will repeat this process of incoming bits from scratch. This outcome sequence might look fortuitous at first sight but taking under consideration the shift register, length and taps one can perceive the exact bits of the fed sequence [DTS].
Following, a simple example of the scramblers operation is comprehensively explained. Paradigm copes with an additive scrambler were an input bit sequence is exploited to fit the modulo 2 logic addition of a pseudorandom sequence.
As shown in figure 1 a sequence is granted from a pseudo-random sequence generator and is composed of a 5-bit non zero seed. This sequence of bits (s1) is brought to the scrambler which are summed modulo 2 of locations 2 and 5 in the shift register.. Before the data transmission begins, bits are shifted up one stage as follows: 5 shifts to channel, 4 shifts to 5, 3 shifts to 4, 2 shifts to 3 and 1 shifts to 2. After this procedure takes place, sequence’s next bit is imported and this process is repeated.
When data transmition (s2′) arrives the descrambler, bits are summed in to modulo 2 sums at the stages of 2 and 5, just like the values given in the in the primary phase of scrambling. The first bit of the incoming sequence results from this sum and the contents at the registry are shifted up one stage as follows: 5 shifts to receiver, 4 shifts to 5, 3 shifts to 4, 2 shifts to 3 and 1 shifts to 2. This procedure is then repeated.
Looking up to the beginning of the paradigm, it should be mentioned that scrambler’s structure is identical to the one that descrambles the data of the outgoing frame. Therefore, any optimization of the scrambler’s circuit must be implemented on both ways in order to carry out an accurate scrambling and descrambling action . Suppose that the channel hasn’t enticed any bit errors a successful scramble and descramble is being performed regarding that s1 = s2.
Going even deeper with the scrambler’s action, a moreover examination of the example above should take place considering the circuit’s application. The basic characteristic of scrambling is the use of Galois Theory on polynomials which finds implementation in the afore mentioned example in the following equation:
s2 = 1 + D2s2 + D5s2 (1)
Where D is a unit delay operator representing the delaying sequence by one bit. Thus, D2s2 and D5s2 refer to the equivalent bits of the scrambled sequenced that is transmitted into the channel as represented in figure 1 and the binary X-OR operator taking place between them. Taking all terms of s2 in one side of the equality the following equation is obtained:
[1 + D2 + D5] s2 = s1 (2)
or, regarding the transfer process:
s2 = [ 1 / (1 + D2 + D5 )] s1 (3)
As for the descrambler’s equation approach, it is reflected as follows:
s3 = [1 + D2 + D5] s2′ (4)
All the above circuits in depth approximation can be generally represented form the following equations:
s2 = F(D)s1 (5)
s3 = G(D)s2 (6)
which, in the scrambling and descrambling pair procedure are used as:
F(D)G(D) = 1 (7)
Thus, any receiving or transmitting connected shift registers that indulges Equation 7 are proper for use as a scrambler and descrambler pair.
Furthermore, it is now clear that data can be scrambled for many reasons but in order for a terminal to receive these data and modify them into a distinctive countenance a descrambling device is necessary. Descrambling is the inverse of scrambling and its purpose is to restore the signal’s data state as they were originally supplied to the coupled scrambler [descrambler]. Descrambling is accomplished through using the exact algorithms that were implemented at the initial scrambled signal. Any other use of algorithms at the descrambler doesn’t cohere to the complete scrambling and descrambling procedure.
2.2 Multicapitave (Self-synchronizing) scrambler
Self-synchronizing scrambling operation acts in two modes. First mode is called start-up and copes with data which are placed to a coupled scrambler and descrambler. This specific seed of information is similarly stored on both ends. After a predestined time interstice, the first mode is terminated and the second one initiates a procedure were information that is stored on both end devices is used to form key signals . This technique deals successfully with randomizing bits by using a logic addition of delayed digits from the source sequence. While in this steady-state mode, errors cannot affect the data as they are already loaded in the devices before the descrambling initiates. Figure 2 represents an indiscriminate scrambler and descrambler that contains M stages and output is given by the following equation:
in which + (X-OR) and Î£ denote modulo addition. Shift register of the descrambler receives the M error-free scrambled bits and initiates decoding after affirming that they are identical to the ones transmitted by the receiver [DTS]. Descramblers decoding equation is familiar to the one of scramblers and favors the following:
Figure 2 Block diagram of Self-Synchronizing Scrambler and Descrambler [DTS].
In data communication systems where scrambling contains bit stream transmissions, an improved method of self-synchronizing technique can be applied. Guided scrambling is accepted to be an extension of multicapitave scrambling and its basic principle is based on a refined encoding technique which provides an enhanced transmission . Analytically, this method exploits the drawback of a single source bit affecting many other quotient bits. For example , if
is the source sequence, the scrambled should be:
which is an unbalanced sequence presenting only a few alterations. The most significant bit of this sequence is 0 but if an altered quotient required this bit to be 1 the new sequence would be:
This sequence, with the alteration of only one bit, carried in the modulo-2 scission process, plainly depicts better transmission attributes.
Guided scrambling is widely implemented in fiber optics communications and assures balanced, efficient transmission with high transition density.
3. Data scrambling in the employment of security
Since the amount of digitalized content increases rapidly, data protection becomes a great issue to deal with, as important as encoding techniques implemented to achieve desirable security [MIS]. Scrambling is greatly well-known and effective security technique as it’s applied on most communication forms [AMIP].
Encryption is the formal name of the scrambling process which applies the function that alters the scope of data in order to be protected before transmitted [SC]. Modern encryption involves algorithms that are based on complex mathematical functions making difficult or in some cases impossible to reverse the scrambled data. Confidentiality is clearly the need that encryption is called to fulfill. However, integrity is also a great issue that data encryption successfully faces. For a long time it has been believed that the feature where one can copy and distribute content freely is advantageous but apart from reading data one can easily change them in a meaningful manner [AMIP]. Furthermore, data scrambling and encryption are fundamental components of protocols that enable the provision of security while executing a system, network or communication task [SC].
4. Implementation of scramblers in 56kbps V.92 modems
V.92 modems are almost extinguished since broadband internet has been solidly established all over the world, but it’s quite interesting to investigate the implementation of the scrambling and descrambling technique on this device because this is where it was elevated. Wherever GSTN and PSTN are the only communication networks’ infrastructure, this type of modem is the state of the art. Data rates of a V.92 modem are 56kbps for downstream when in use from server to client connection and 48kbps for upstream when in use from client to server.
Term modem emanates from the words modulation and demodulation which basically refer to the main process executed by this specific device: turning to account of the analog signal carried by telecommunication network for data transmission and elaboration. Scrambler in this case guarantees sufficient transitions in the transmitted data for clock extraction and avoids a continuous stream of ones and zeros using an algorithm to alter the data sequence [DCCN]. In order for a modem to perform a one to one mapping between bits and encoding procedure of another modem device it must also be equipped with a descrambler.
Data communications very often transmit idle characters, particularly when paired modems make no use of the transmission medium for a relatively long period [DCCN]. Initiating a data transmission again could evoke a data blast with repeating errors presented at the beginning of data. This error occurs because clock phase’s pattern is quite sensitive but can be overcome from scramblers ability to randomize data before their transmission [DCCN].
Figure 3 Scrambler block diagram [MATLAB]
A scrambler’s block diagram is characteristically represented in Figure 3. As mentioned before, all adders perform a modulo-2 addition and switches in the schematic are defined by the implementing polynomial. In the case of a 56kbps modem the polynomial in use is:
y(x) = 1 + x-18 + x-23
which reflects a self-synchronizing scrambling procedure yet bearing a feature of creating the handshake between the terminals. If transmission in the communication network is errorless then the descrambler will be able to translate the signal using the same polynomial contrarily.
5. Application of Matlab to simulate a 56kbps modem’s scrambler
Matlab’s Simulink toolbox can fulfill the potential of simulating a scrambler with all the adjustments required. Figure 4 enacts a full scrambling procedure from the signal generation to the scrambling feature and after that to the “scope” function.
Figure 4 Scrambler simulation on Simulink
Going deeper in this scheme analysis, a signal generator is situated at the beginning of the diagram. Bernouli’s Binary Generator is using a distribution to produce a sequence of random 0s and 1s. In addition to that, a probability of P is applied to produce 0s and 1-P for 1s. The scrambler feature is using a scheme like the one represented in Figure 3 for its fundamental use and utilizes all polynomials capabilities. For example if the polynomial is y(x) = 1 + x-6 + x-8 then the data to be imported are: p = [1 0 0 0 0 0 1 0 1] and p = [0 -6 -8] [MATLAB]. Last, but not least, the “scope” widget where conclusive measurements can be extracted from all the previous signal processing.
The most common test to be implemented in this simulating scheme would consider time and the input value of P. Particularly, P configures the quantity of 0s and 1s that will shape the outgoing stream of the binary generator. Speed of the user on the other hand in comparison with the real speed of the 56kbps modem is quite low, resulting a long stream of idle status or 0s. In the subsequent examination P will be given the value of 0.9 in order to have maximum possibilities for this stream to appear. Using the spectrum analyzer from Matlab’s Simulink the following results of Figure 5 appeared.
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