Characteristics of buses
This report focuses on the computer system architecture of buses. The research is based on the buses which used by AMD K computer system. Those are includes bus characteristics, bus arbitration and bus topology.
In bus characteristics, we had cover the bus width and bus speed, types of buses and bus lines, and also advantages and disadvantages of a "bus" to a "network". In bus arbitration, there was include purpose of arbitration, how does the arbitration protocol work and multiplexing. Other else was the bus topology.
In the end of the report, there was a summarize results which include why a bus hierarchy is required, how a bus hierarchy works and additional hardware circuitry required.
This assignment is mainly explaining a fundamental architectural feature present in all computer system, buses. Buses have historically provided a flexible communications structure in computer systems.
Furthermore, buses in computing are a digital communication mechanism that allows two or more functional units to transfer control signals or data. Most buses are designed for use inside a single computer system; some are used within a single integrated circuit. Many bus designs exist because a bus can be optimized for a specific purpose. For example, a memory bus is intended to interconnect a processor with a memory system and an I/O bus is intended to interconnect a processor with set of I/O devices.
Furthermore, buses can be divided into two major groups based on their control. Those two groups are local buses and system buses.
Various bus designs have been used in the PC, including ISA, EISA, Micro Channel, VL-bus and PCI. Other peripheral busses are NuBus, TURBOchannel, VMEbus, MULTIBUS and STD bus.
A bus is characterized by the amount of information that can be transmitted at once. It is call bus width. The amount expressed in bits, corresponds to the number of physical lines over which data is sent simultaneously. The term "width" is used to refer to the number of bits that a bus can transmit at once. Typical widths are 8, 16, 32, or 64 bits at a time.
In other words, the bus width means the size of the entity that the bus sends data in one cycle. For example 32 bits, this means that the bus has 32 wires that are used for the transmission. (This may also be different, depending on the transmission protocol).
Bus speed means how many bits or bytes (1 byte = 8 bits) is the bus able to send in a unit of time (typically second). For example for a computer network it could be 100 Mbs means 100 Megabits (12, 5 Megabytes) in a second. The bus speed is also defined by its frequency. It expressed in Hertz. Frequency means the number of data packets sent or received per second. Each time that data is sent or received is called a cycle.
Besides, the bus speeds also commonly known as front side bus (FSB). It is shows how fast the components can communicate with each other. Faster bus speed means faster computer. You can easily see how a faster FSB helps your computer get more information from one place to the other. For example, if two computers are exactly the same in all ways except one has an FSB speed of 500 MHz and the other has an FSB of 1066 MHz, twice as much data will get through on the second computer compared to the first. This means your computer will get more work done in the same amount of time faster spreadsheet calculations, faster decoding of that movie, or smoother video games.
To increase the bus speed you can either increase the bus width or the frequency of the transmission on the bus.
The Different Types of Buses
- Local Buses
- Address buses tend to be specialized in purpose and are usually unidirectional. It carries an address from the CPU to memory or I/O devices.
- Data buses tend to be more general in purpose and are bidirectional. It carries data between the CPU and memory or I/O devices.
- Control buses carry signals from the control unit to other components of the computer and back to control unit.
- System Buses
A local bus is the simplest buses consist of set of wires. Within the central processing unit (CPU), local buses can generally be divided in three types. They are address buses, data buses or control buses.
Unlike local buses, system buses are independent functional components of many computers. Each system bus has its own control circuit, called a bus controller, and within each bus controller is an arbiter, which process requests to use the bus. The bus controller may be distributed among the devices that use the bus. Systems buses generally connect system components together, such as the CPU,I/O system and often the main-memory system, and designers often optimize system buses for transferring data between I/O devices and main-memory.
A key distinction between system buses and local buses is that system buses tend to have well-documented and stable definitions, so that designers can attach a wide variety of devices to them. Local buses are processor-specific and not widely documented. They tend to be proprietary. Example of system buses are DEC UNIBUS and the Apple NuBus.
The wires that comprise a bus are called lines.
Four main categories of bus lines :
- Data lines - Carry data from one place to another.
- Address lines - Specify the recipient of data on the bus.
- Control lines - Provide control for the synchronization and operation of the bus and the modules to which it is connected.
- Power lines - Provide power to various components connected to the bus.
Advantages / Disadvantages of a "Bus" to a "Network"
Data bus networks have quite a few advantages compare the other network topologies such as point-to-point links in these applications. Generally, a data bus can make possible the interconnection of a set of terminals when the number of terminals is so large that interconnection through individual point-to-point links becomes unusable. Furthermore, a data bus topology can provide large configurationally flexibility. Terminals can be added to the network or moved to different locations without major revisions in the cabling layout. Both of these advantages are of particular importance in applications in which cable installation is the dominant system cost, for example in shipboard applications.
Purpose of arbitration
In a computer system, all the devices communicate with the other device are connected to the main board over a same bus. If two or more I/O (input and output) devices try to use the bus at the same time to access the main board, there will be a conflict arise. Therefore, bus arbitration is created is to resolve the problem. Bus arbiter is a circuit to coordinate the activities of devices request for memory transfer using the bus. The process that runs by bus arbiter is name as Bus Arbitration. It is to prevent two or more I/O devices initiating transfers at the same time.
The bus arbitration mechanism is designed to allow high priority devices such as the processor and RAM get first access to the bus, while the other devices (disks, video cards, sound cards etc.) get lower priority, and often have to wait to access the bus. The prioritization is according numbered interrupts to priority systems. The lower the numbered interrupts will has the higher priority. On many systems, the CPU has interrupt 0. Therefore, CPU always goes first on the bus. Meanwhile, there are time slices provided over the bus.
How does the arbitration protocol work
The device that uses to allow for initiating data transfers on the bus is called as bus master. Therefore, only one bus master can exist at a time. When the bus master relinquished its control, the other device also can act as bus master. However, the process of transferring the bus mastership from one device to another device has to coordinate carefully to take account of the needs of various devices. As stated earlier, the bus arbitration has been design to use by high priority device. Therefore, scheduling function will be performs by bus arbiter. Bus arbiter can be part of the processer or separate unit that connected to bus.
The diagram above show a basic arrangement example of processor contains the bus arbiter circuitry. In this case, the processor is act as the bus master. However in some cases, the other DMA (direct memory access) controller can gain the bus mastership. DMA controllers activate the Bus-request line, BR before it gain the bus mastership. The Signal of Bus- request line is transfer using the logical OR concept from the bus-request line to the other I/O devices. When the bus request is activated, the processor will activates the bus Grant signal, BG1, gives permission to the DMA controller use the bus when it become free. The signal is using a daisy-chain arrangement to connect all DMA controllers. Therefore, when DMA controller 1 request for the bus, it will block the propagation of the grant signal to other I/O device automatically. Else, it will assert BG2 to grant downstream. The bus master indicates all I/O devices that it is using the bus by activating another open collector line call as Bus Busy, BBSY. Therefore, a DMA controller need to wait for Bus busy to inactive after the Bus Grant signal send. In the situation, the DMA controller can assumes the bus mastership.
Multiplexed bus is a type of bus structure which the number of signal lines represented by the bus is less than the number of bits of data, addresses, and control information being transferred between devices of the computer system. For example, if a multiplexed address bus use 8 signal lines to transmit 16 bits of address information. The information is transferred sequentially where the additional control line is being used for sequencing the transfer.
In another example, the system represent a master control unit (MCU) connecting to one or more receiver-transmit unit (RTU) by a data bus. The MCU transmits a message to the RTU for comprising a synchronization pulse of known duration and successive time spaced timing signals separated by time duration T marking the boundaries of data bits to be transmitted from the RTU to the MCU. The RTU is including a clock pulse source which utilizes the synchronization pulse to determine the frequency of the clock pulse source in P pulses per duration T. The value P is used in conjunction with the timing signals to create properly timed data determining signals in the data bits.
Point to point topology
Point to point (PTP) is directly connects two nodes to together. Following is some example of using PTP to connect 2 nodes together.
- Two computers communicating via modems.
- A mainframe terminal communicating with a front end processor.
- A workstation communicating along a parallel cable to a scanner.
In a point-to-point topology, all the devices are connected with a shared switch. The switch is different from the shared topology. Computational components that are connected using a point-to-point topology do not need to use any type of bus arbitration scheme. Instate, the shared switch breaks the continuous stream of data on the bus into data packets that are routed to the individual devices. Using this method, the shared switch able establishes point-to-point connections between the different devices. From an individual device's perspective, a connection has to be a private, direct, continuous connection to another device. The connection may comprise one or more two-way of serial-connections. By increasing the number of lanes of a connection, therefore the bandwidth of the connection can by increase. An example of point-to-point bus topology is the implementation in peripheral component interface expresses ("PCI Express"). PCI Express is a computer expansion card standard designed to replace the older PCI, PCI-X, and AGP standards. It was introduced by Intel in 2004, PCIe is the latest standard for expansion cards that is available on mainstream personal computers.
Multipoint is a bus topologies that carries signals to several destinations. It is also known as multidrop bus (MDB) or broadcast bus. Multipoint bus usually requires addressing signals on the bus to identify the addressed destination. Example : Ethernet. It is also a computer bus in which all components are connected to same set of electrical wires.
From this assignment, we had classified out the type of buses which it's basically grouped into four parts known as processor bus, cache bus, local I/O bus and standard I/O bus. Each of this is different as processor bus is the highest-level bus that the chipset uses to send information to and from the processor.
While, cache bus used to accessing the system cache. At the same time, the local I/O bus is for connecting performance-critical peripherals to the memory, chipset, and processor such as video cards and disk storage devices. Example of local I/O bus is like Peripheral Component Interconnect Bus (PCI).
Last would be the standard I/O bus which it used for slower peripherals such as modems while it also for compatibility with older devices. Bus hierarchy is required due to the lower level bus like local and standard I/O buses need to steps by steps sent the data to the upper levels of buses in order to allow users to retrieve or transfer the data from each particular memory to another.
Hence, I consider them a hierarchy because each bus is to some extent further removed from the processor; each one connects to the level above it, integrating the various parts of the PC together. Each one is also generally slower than the one above it. As a conclusion, bus is generally designed for multiple devices to share the medium. Furthermore, additional hardware circuitry is needed because of that may have problems when two clients want to transmit at the same time on the same bus. Therefore, hardware like bus arbitration is needed to overcome this conflict.
As a conclusion, buses are actually helpful as its act as a vital medium in order to transferring data. Basically, buses connect different modules within the CPU and to memory and other I/O peripherals. Meanwhile, buses can also connect two different components at the same time through the usage of point-to-point or multipoint.
Buses can carry data, address and control function as it could transmit the instructions of the users into the outputs. Buses are form in the combination of data line, address line, power line and control line. Then, buses and buses communicate through a medium called bridge.
Further, we had identified the characteristics of the buses as it categorized into two categories. For bus speed, it covers the area for speed of transmitting data to another medium. While, bus width is the amount of data can be transferring. Besides, type of buses, pros and cons of bus and network and buses arbitration also included within our report. Lastly, we had also stated out the purposes of buses arbitration.
Frequently Ask Question (FAQ)
- What is a bus?
- How to solve the conflict of different data is being transferring through the same bus but at different devices?
- What are the functions of buses?
- How to measure the speed of transferring or retrieving data from buses?
- How does buses connected to each other?
- How to increase the buses speed?
- Which method allows buses to connect 2 devices?
- Jospeph.S, 1985, Multiplex bus system for controlling the transmission of data between a master control unit and a plurality of remotely located receiver-transmitter units [online], Available from http://www.freepatentsonline.com/4538262.html [Accessed 30 October 2009]
- What is a computer bus? [Online], Available World Wide Web : URL http://en.kioskea.net/contents/pc/bus.php3 [Accessed 26 Oct 2009]
- Shinichi, What is bus speed? [Online], Available World Wide Web : URL http://www.helium.com/items/986164-what-is-bus-speed [Accessed 26 Oct 2009]
- Multidrop bus [Online], Available World Wide Web : URL http://wikirank.com/en/Multidrop [Accessed 02 Nov 2009]
- Derwyn.J, 1984, Passive fiber optic data bus configurations [online], Available from http://www.freepatentsonline.com/4457581.html [Accessed 10 November 2009]
- System bus, online, Available from http://www.inetdaemon.com/tutorials/computers/hardware/mainboards/bus/[Accesed 30 October 2009]
- DAINTITH.J, 2004, "multiplexed bus." A Dictionary of Computing [online], Available from http://www.encyclopedia.com [Accessed 03 November 2009]
- Hamacher.C, Vranesic.G, Zaky.G, 1996, computer organization In, 4th edition, McGraw-hill international editions, Singapore, 1996, pp186
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