Project Development in XILINX ISE 10.1
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A design engineer in electronic industry uses hardware description language to keep pace with the productivity of the competitors. With VHSIC (Very High Speed Integrated Circuits) Hardware Description Language (VHDL) we can quickly describe and synthesize circuits of several thousand gates. In addition VHDL provides the capabilities described as follows:
Power and flexibility:
VHDL has powerful language constructs with which to write succinct code description of complex control logic. It also has multiple levels of design description for controlling design implementation. It supports design libraries and creation of reusable components. It provides Design hierarchies to create modular designs. It is one language fort design and simulation.
Device –Independent design:
VHDL permits to create a design without having to first choose a device foe implementation. With one design description, we can target many device architectures. Without being familiar with it, we can optimize our design for resource or performance. It permits multiple style of design description.
VHDL portability permits to simulate the same design description that we have synthesized. Simulating a large design description before synthesizing can save considerable time. As VHDL is a standard, design description can be taken from one simulator to another, one synthesis tool to another; one platform to another-means description can be used in multiple projects.
Device–independent design and portability allows benchmarking a design using different device architectures and different synthesis tool. We can take a complete design description and synthesize it, create logic for it, evaluate the results and finally choose the device-a Complex Programmable Logic Device (CPLD) or a Field Programmable Gate Array (FPGA) that fits our requirements.
The efficiency that VHDL generates, allows our product to hit the market quickly if it has been synthesized on a CPLD or FPGA. When production value reaches appropriate levels, VHDL facilitates the development of Application Specific Integrated Circuit (ASIC). Sometimes, the exact code used with the Programmable Logic Device (PLD) can be used with the ASIC and because VHDL is a well-defined language, we can be assured that out ASIC vendor will deliver a device with expected functionality.
4.1 VHDL DESCRIPTION
In the search of a standard design and documentation for the Very High Speed Integrated Circuits (VHSIC) program, the United States Department of Defense (DOD) in 1981sponsored a workshop on Hardware Description Languages (HDL) at Woods Hole, Massachusetts. In 1983, the DOD established requirements for a standard VHSIC Hardware Description Language VHDL, its environment and its software was awarded to IBM, Texas Instruments and Intermetrics corporations.
VHDL 2.0 was released only after the project was begun. The language was significantly improved correcting the shortcoming of the earlier versions; VHDL 6.0 was released in 1984. VHDL 1078/1164 formally became the IEEE standard Hardware Description Language in 1987.
A VHDL design is defined as an ‘entity declaration’ and as an associated ‘architecture body’. The declaration specifies its interface and is used by architecture bodies of design entities at upper levels of hierarchy. The architecture body describes the operation of a design entity by specifying its interconnection with other design entities –‘structural description,’ by its behaviour –‘behavioural description’, or by a mixture of both. The VHDL language groups, sub programs or design entities by use of packages.
For customizing generic descriptions of design entities, configurations are used. VHDL also supports libraries and contains constructs for accessing packages, design entities or configurations from various libraries.
4.2 INTRODUCTION TO XILINX ISE 10.1:
Create a New Project
Create a new ISE project which will target the FPGA device on the Spartan-3 Startup Kit demo board.
To create a new project:
- Select File > New Project... The New Project Wizard appears.
- Type tutorial in the Project Name field.
- Enter or browse to a location (directory path) for the new project. A tutorial subdirectory is created automatically.
- Verify that HDL is selected from the Top-Level Source Type list.
- Click Next to move to the device properties page.
- Fill in the properties in the table as shown below:
- Product Category: All
- Family: Spartan3
- Device: XC3S200
- Package: FT256
- Speed Grade: -4
- Top-Level Source Type: HDL
- Synthesis Tool: XST (VHDL/Verilog)
- Simulator: ISE Simulator (VHDL/Verilog)
- Preferred Language: Verilog (or VHDL)
- Verify that Enable Enhanced Design Summary is selected.
Leave the default values in the remaining fields.
When the table is complete, your project properties will look like the following:
7. Click Next to proceed to the Create New Source window in the New Project Wizard. At
the end of the next section, your new project will be complete.
Create an HDL Source
In this section, you will create the top-level HDL file for your design. Determine the language that you wish to use for the tutorial. Then, continue either to the “Creating a
VHDL Source” section below, or skip to the “Creating a Verilog Source” section.
Creating a VHDL Source
Create a VHDL source file for the project as follows:
- Click the New Source button in the New Project Wizard.
- Select VHDL Module as the source type.
- Type in the file name counter.
- Verify that the Add to project checkbox is selected.
- Click Next.
- Declare the ports for the counter design by filling in the port information as shown below:
7. Click Next, then Finish in the New Source Wizard - Summary dialog box to complete the new source file template.
8. Click Next, then Next, then Finish.
The source file containing the entity/architecture pair displays in the Workspace, and the counter displays in the Source tab, as shown below:
Checking the Syntax of the New Counter Module
When the source files are complete, check the syntax of the design to find errors and typos.
- Verify that Implementation is selected from the drop-down list in the Sources window.
- Select the counter design source in the Sources window to display the related processes in the Processes window.
- Click the “+” next to the Synthesize-XST process to expand the process group.
- Double-click the Check Syntax process.
Note: You must correct any errors found in your source files. You can check for errors in the
Console tab of the Transcript window. If you continue without valid syntax, you will not be able to simulate or synthesize your design.
5. Close the HDL file.
Verifying Functionality using Behavioral Simulation
Create a test bench waveform containing input stimulus you can use to verify the functionality of the counter module. The test bench waveform is a graphical view of a test bench.
Create the test bench waveform as follows:
1. Select the counter HDL file in the Sources window.
2. Create a new test bench source by selecting Project → New Source.
3. In the New Source Wizard, select Test Bench Wave Form as the source type, and type
Counter_tbw in the File Name field.
4. Click Next.
5. The Associated Source page shows that you are associating the test bench waveform
with the source file counter. Click Next.
6. The Summary page shows that the source will be added to the project, and it displays
the source directory, type, and name. Click Finish.
7. You need to set the clock frequency, setup time and output delay times in the Initialize.
Timing dialog box before the test bench waveform editing window opens.
The requirements for this design are the following:
- The counter must operate correctly with an input clock frequency = 25 MHz.
- The DIRECTION input will be valid 10 ns before the rising edge of CLOCK.
- The output (COUNT_OUT) must be valid 10 ns after the rising edge of CLOCK.
The design requirements correspond with the values below.
Fill in the fields in the Initialize Timing dialog box with the following information:
- Clock High Time: 20 ns.
- Clock Low Time: 20 ns.
- Input Setup Time: 10 ns.
- Output Valid Delay: 10 ns.
- Offset: 0 ns.
- Global signal: GSR(FPGA).
Note: When GSR(FPGA) is enabled, 100 ns. is added to the Offset value automatically.
8. Click Finish to complete the timing initialization.
9. The blue shaded areas that precede the rising edge of the CLOCK correspond to the Input
Setup Time in the Initialize Timing dialog box. Toggle the DIRECTION port to define the
Note: For more accurate alignment, you can use the Zoom In and Zoom Out toolbar buttons.
10. Save the waveform.
11. In the Sources window, select the Behavioral Simulation view to see that the test bench
waveform file is automatically added to your project.
12. Close the test bench waveform.
Simulating Design Functionality
Verify that the counter design functions as you expect by performing behavior simulation as follows:
1. Verify that Behavioral Simulation and counter_tbw are selected in the Sources window.
2. In the Processes tab, click the “+” to expand the Xilinx ISE Simulator process and double-click the Simulate Behavioral Model process.
The ISE Simulator opens and runs the simulation to the end of the test bench.
3. To view your simulation results, select the Simulation tab and zoom in on the transitions.
Note: You can ignore any rows that start with TX.
4. Verify that the counter is counting up and down as expected.
5. Close the simulation view. If you are prompted with the following message, “You have an active simulation open. Are you sure you want to close it?” click Yes to continue.
You have now completed simulation of your design using the ISE Simulator.
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