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# Annotated Bibliography on “Cache Power Optimization”

 ✅ Paper Type: Free Essay ✅ Subject: Sciences ✅ Wordcount: 2605 words ✅ Published: 8th Feb 2020
1. Inki Hong, Darko Kirovski, Gang Qu, Miodrag Potkonjak, and Mani B. Srivastava, Power Optimization of Variable-Voltage Core-Based Systems, retrieved from:

This paper discusses about a synthesis technique called Non-Preemptive scheduling which allows us to fully exploit dynamically variable voltage hardware, thereby helping us to determine the processor core and determine the size of data and instruction cache. The basis of selecting Non-Preemptive scheduling heuristic algorithm is that it helps us to get results in solutions which are close to optimal ones in most of the test cases. In this paper static scheduling problem is targeted for which both preemptive and Non-preemptive techniques can be used based on the requirement. In case of Non-preemptive scheduling overhead is considered be negligible or neglected, whereas preemptive technique does not justify high overhead and it has high overhead for runtime scheduling decisions. For various design cases used in this paper Non-Pre-emptive scheduling is used by the neglecting the time taken to reach steady state at new voltage and power consumed by dc-dc converter and results shows that non-pre-emptive yielded superior results in consideration of pre-emption penalty of context switch and voltage changes. The important contribution made by this paper is that it developed scheduling algorithms which treat voltage as variable to be determined in addition to conventional task scheduling and allocation which can be used to handle more general models.

This paper helps us understand various scheduling algorithms and their implementation to solve various scheduling problems.

This paper proposes a simple equation for estimating Static power       consumption at an architectural level and the equation is as follows:

Pstatic= VCC.N.kdesign.I^leak, where kdesign is design dependent parameter and I^leak is a technology dependent parameter. Static power dissipation  due to subthreshold leakage is an important part of overall power dissipation and static power dissipation due to transistor leads to an increase in fraction of total power in semiconductor technologies. Static power can be optimized by reducing the number of devices, turning off unused devices , allowing high bandwidth over low latency and portioning the design for lower supply voltages or less leaky transistors. Various techniques techniques employed to control static power consumption have the problem of controlling dynamic power as well. In order to improve performance in various technologies transistor threshold voltage is reduced. This paper provides the architects the way to estimate static power at architectural level and various ways of limiting it.

This paper helps us to determine static power consumption at an architectural level and it also provides us with various ways to limit it.

1. Reetuparna Das, Asit K. Mishra, Chrysostomos Nicopoulos, Dongkook Park, Vijaykrishnan Narayanan, Chita R. Das, Dept. of CSE, The Pennsylvania State University, University Park, 16801, USA, Ravishankar Iyer, Mazin S. Yousif, Corporate Technology Group, Intel Corporation, Hillsboro, OR 97124, USA.  Performance and Power Optimization through data compression in Network on Chip Architectures, retrieved from:

This paper examines 2 different configurations namely Cache Compression(CC) and Compression in NIC(NC) to examine various combinations of  storage and communication compression and a technique is discussed to mask decompression in latency by overlapping with NOC communication latency. In case of cache compression (CC)

Data is compressed after L 1 before sending to L2.This way it improves memory and system performance and it provides up to 21% of average reduction in Network Latency and power consumption is reduced by 7 % with a maximum of 23%.Incase of Compression in NIC(NC) only network communication traffic is compressed this way we do not require any modification in L 2 cache since data is not compressed and it provides an average reduction in Network Latency of upto 20% with maximum of 32% and reduction in power consumption by 10% with maximum of 24%.

This paper helps us understand various compression techniques that can be employed in various parts of cache design to reduce latency, power consumption and improve performance.

1. Ching-Long Su and Alvin M. Despain, Advanced Computer Architecture Laboratory, University of Southern California, {csu, despain} @usc.edu. Cache Design Tradeoff’s for Power and Performance Optimization: A Case Study, retrieved from:

This case study examines performance, power trade off and energy reduction in various low power cache design techniques and access time is calculated by considering 0.8µm CMOS technology. It is found that direct mapped caches have better cache latency than set associative instruction cache whereas set associative  data cache has better latency than direct mapped data cache. Direct Mapped Instruction and Data cache consume less energy compared to set associative instruction and data cache when implemented in dynamic logic. Set Associative Instruction and Data cache consume less energy compared to Direct Mapped  instruction and data cache when implemented in static logic. It is also found out that caches with sizes 4k to 8k bytes consume less energy.

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In this case study some of the techniques like Gray Code Addressing and cache sub banking are examined. It is also examined that 32% and 12% of bit switches on instruction and data address bus are reduced using Gray code addressing. When the above techniques are applied to 32kbyte four way set associative with 32 byte cache line it  is found out that only 23.11% of total cache energy is consumed without applying the above techniques.

This case study helps us examine the performance of direct mapped and set associative caches in static and dynamic logic and we also found the change in various parameters when various techniques are applied.

1. Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu, Dinesh Somasekhar, and Shih-Lien Lu, Intel Labs, Hillsboro, Oregon, USA. Reducing Cache Power with Low Cost, Multibit Error Correcting Codes, retrieved from:

In this paper HI-ECC technique was proposed in which multibit error correcting codes were included to reduce the refresh rate. In large eDRAM caches with variations in refresh time and cache power consumption there is a significant impact. HI-ECC  technique eliminates the usage of decoder by using strong ECC codes to identify and decode various sections of multibit failures thereby providing an efficient single bit error correction. This technique decreases the storage cost of code over large data words thereby providing an advantage of multibit correction at same storage cost as single bit error correcting code(SECDED) with an overhead of 2%.This technique helps in reduction of refresh power versus a baseline CDRAM cache without ECC by 93% and 66% reduction in refresh power by using SECDED codes.

This paper introduces a new technique called HI-ECC which helps in error correction as well as reducing the power with low cost.

1. Tony D. Givargis, Frank Vahid, Department of Computer Science and Engineering, University of California, Riverside, CA, Jörg Henkel, C&C Research Laboratories, NEC, 4 Independence Way, Princeton, NJ. Interface and Cache Power Exploration for Core–Based Embedded System

This paper developed a comprehensive approach to find out the impact of various interdependencies of design characteristics such as power, performance and area in case of multi core systems and explore the power consumed by cache and interfaces in embedded-data intensive systems. Interfaces play the important role to control or access these interdependencies. Cache parameters and bus configuration of cache buses are the ones that are having utmost impact on power consumption. While implementing techniques for optimizing performance in submicron systems, it doesn’t necessarily mean that power is optimized. Explorations revealed that the interdependencies which we do not explore help us to optimize or adopt interface or caches in low power systems in future.In newer technologies interface power contribution increases there by leading to power or performance trade off due to higher wire or gate capacitance ratio for small feature sizes. In older technologies there is hardly a trade off between power and performance where as in CPU-to-Cache bus configuration optimal configuration of remaining cache or bus parameters minimizes power, performance and size.

This paper helps us understand the impact of interfaces and cache on various parameters of system like power, performance and size.

## 7.     Xin Li, George Mason University, Fairfax, VA, USA, Mian Dong, Zhan Ma, Felix C.A. Fernandes, Samsung Telecommunications America, Richardson, TX, USA. GreenTube: power optimization for mobile video streaming via dynamic cache management, retrieved from:

In this paper a system called Greentube was proposed inorder to alleviate the problem of reduction in battery life in 3G/4G network radios in smartphones. Greentube optimizes the power consumption in the system by selectively scheduling download activities to minimize or reduce unnecessary active periods of 3G/4G networks. This is implemented in the following way. First Greentube system disconnects http server after each downloading session when cache is full and this is done by closing the TCP connection when cache is full. Greentube system estimates the network speed for every second using downloaded data sizes from previous second and based on this Greentube adjusts cache size and set maximal cache size based on users choice and this type of adaptive adjustment is called dynamic cache management. Results have shown that Greentube system achieves  power reductions of more than 70% on 3G/4G radio and 40% for whole system.

This paper helped us to know about  a new system called Greentube which was developed to reduce power consumption by 3G/4G network in smartphone adaptively adjusting the cache size based on previous downloaded data

1. Johnson Kin, Munish Gupta and William H. Mangione-Smith, The Department of Electrical Engineering, UCLA Electrical Engineering. The Filter Cache: An Energy Efficient Memory Structure, retrieved from:

In this paper a new cache called Filter Cache was developed whose size is smaller than the size of  L1 cache  in order to reduce power consumption by compromising performance. Caches consume a significant amount of power in various system but in portable devices low power is of utmost importance compared to performance. Power Consumption can be reduced by filtering cache  references through a smaller L1 cache called Filter Cache. Since filter  cache is smaller than L1 cache it has less access time and an additional clock cycle is required for L1 cache to access filter cache.L2 cache which is similar in and structure of L1 cache is placed near L1 cache in order  to reduce performance loss. Results show that a direct mapped 256 byte filter cache achieves reduction in power of 58% ,performance is reduced by 21% and reduction in energy delay product over conventional design by 51%.

This paper introduced  a new concept called filter cache to reduce power

Consumption and it helps in understanding the tradeoff between power consumption and performance in a system.

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