The Central Processing Unit is the brain of the computer. Control unit is the most important portion of CPU .The control unit design must include logic for sequencing through micro-operations, for executing micro-operations, for interpreting opcodes and making decisions based on ALU flags. There are two different techniques to specify the control unit. They are Hardwired implementation and Microprogrammed implementation. In hardwired control, it is very time consuming and hard to design. The use of microprogramming simplifies the design of the control unit, but it will be slower in speed than a hardwired unit. Hardwired control is difficult to change or extend the design if it wishes to debug or add a new machine instruction. So this paper will find an easy way to design by microprogram and to be translated it to Hardwired one on later. To translate the microprogram into actual hardware, it is needed to specify how each field translates into control signals. A microprogram can be implemented with finite state control or a microcode implementation with an explicit sequencer. The finite state machines are usually represented graphically. In this paper, Verilog software is used to translate microprogram to hardware.
The CPU (Central Processing Unit) is the “brain” of the computer. Its function is to execute the programs stored in the main memory by fetching their instructions, examining them, and then executing them after another. The CPU is composed of several distinct parts. The control unit is responsible for fetching instructions from main memory and determining their type. The control unit also issues control signals internal to the CPU to move data between registers, to cause the ALU to perform a specified function, and to regulate other internal operations. Input to the control unit consists of the instruction register, flags, and control signals from external sources (e.g.; interrupt signals)  .
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To design the control unit for the single-cycle datapath, a set of truth tables specified the setting of the control signals based on instruction class. For the multicycle datapath, the control is more complex because the instruction is executed in a series of steps. The control is to be set in any step and the next step in the sequence .
There are two different techniques to specify the control unit.
The hardwired control is characterized by finite state machines using an explicit next state and represented graphically or through Hardware description language. Microprogramming uses a programming representation that implements the machine instructions in terms of simpler microinstructions.
The use of microprogramming simplifies the design of the control unit, but it will be somewhat slower in speed than a hardwired unit of comparable technology. Hardwired control is difficult to change or extend the design if it wishes to debug or add a new machine instruction. So this paper will find an easy way to design by microprogram and to be translated it to Hardwired one on later. To translate the microprogram into actual hardware, it is needed to specify how each field translates into control signals. The microprogram can be thought of as a text representation of a finite state machine, and implemented in exactly the same way we would implement a finite state machine: using a PLA to encode both the sequencing function as well as the main control. In this paper, the microprogram used in this paper is a control program running on Mic-1 machine which is implemented by IJVM instructions to translate the Microprogrammed control to the high speed hardwired one, using Verilog.
2. Defining the Control
The control is largely defined by the instruction set architecture, the organization, and the datapath design. When it can be defined what control signals are and when they must be asserted, we can implement the control unit. The hardwired control generates the control information and executes the instruction in one pass through the datapath that take smaller number of clock cycles.
A microprogram can be implemented with finite state control or a microcode implementation with an explicit sequencer. The finite state machines are usually represented graphically. The first method to specify the multicycle control is a finite state machine. A finite state machine consists of a set of states and directions on how to change states. The directions are defined by a next- state function, which maps the current state and the inputs to a new state. When a finite state machine is used for control, each state also specifies a set of outputs that are asserted when the machine is in that state. The implementation of a finite state machine usually assumes that all outputs that are not explicitly asserted are de-asserted. Similarly, the correct operation of the datapath depends on the fact that a signal that is not explicitly asserted is deasserted, rather than acting as a don’t care. For example, the RegWrite signal should be asserted only when a register file entry is to be written; when it is not asserted, it must be deasserted  .
When a finite state machine is used as a controller, the output function is often restricted to depend on just the current state. Such a finite state machine is called a Moore machine. If the output function can depend on both the current state and the current input, the machine is called a Mealy machine. These two machines are equivalent in their capabilities, and one can be turned into the other mechanically. The basic advantage of a Moore machine is that it can be faster, while a Mealy machine may be smaller, since it may need fewer states than Moore machine .
In this paper, the instruction set are built by using finite state machine, which translates the microprogrammed control to the high speed hardwired one, using Hardware description language such as Verilog.
2.1. Microinstruction Control: Mic-1
Figure 1 is a detailed block diagram of the complete microarchitecture of IJVM, called Mic-1 .The block diagram has two parts: the data path, on the left and the control section, on the right.
The largest and most important item in the control portion of the machine is a memory called the control store that holds the complete microprogram. It contains 512 words, each word consisting of one 36-bit microinstruction. Actually, not all of these words are needed, but we need address for 512 distinct words .
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The MIR register holds the same six groups as figure. The Addr and J (for JAM) groups control the selection of the next microinstruction. The ALU groups contain the 8 bits that select the ALU function and drive the shifter. The C bits cause individual registers to load the ALU output from the C bus. The M bits control memory operations. Finally the last 4 bits drive the decoder that determines what goes onto the B bus. The 4 to 16 decoder is used as a standard even though only nine possibilities are required .
The datapath is the part of CPU containing the ALU, its input, and its output. While it has been carefully optimized for interpreting IJVM programs, it is fairly similar to the datapath used in most machines. It contains a number of 32-bit registers, to which symbolic names have been described such as PC, SP, and MDR. Most registers can drive their contents onto the B bus. The output of the ALU drives the shifter and then C bus, whose value can be written into one or more registers at the same time .
Implementation of IJVM Using the Mic-1
The design of the microarchitecture level depends on the ISA being implemented, as well as the cost and performance goals of the computer. Executing an instruction may require locating the operands in memory. The sequencing of operations within a single instruction often leads to a different approach to control than that for simple ISAs. For our example ISA, we have chosen a subset of the Java Virtual Machine which contains only integer instruction, IJVM . Each IJVM instruction has a few fields, each of which has some specific purpose. The first field of every instruction is the opcode which identifies the instruction. Many instructions have an additional field, which specifies the operand .
The microprogram that runs on Mic-1 and interprets IJVM is given by . It is a surprisingly short program; only 112 microinstructions total. The microprogram has a main loop that fetches, decodes, and executes instructions from the program being interpreted, in this case, IJVM instructions. Its main loop begins on the line labeled Main1. It starts with the invariant that PC has previously been loaded with an address of a memory location containing an opcode. Furthermore, that opcode has already been fetched into MBR. When we get back to the location, PC has been updated to point to the next opcode to be interpreted and the opcode byte itself has already been fetched into MBR. This initial instruction sequence is executed at the beginning of every instruction, so it is important that it be as short as possible .
In this paper, the microprogram implemented by IJVM in the Mic-1 is used to translate a Microprogram to hardware.
3. Translating to the Finite state machine
Given the data path in Figure 1, we now need to look at what should happen in each clock cycle of the multicycle execution, since this will determine what additional control signals may be needed, as well as the setting of the control signals which implement in table1 given by Ref:. The goal in breaking the execution into clock cycles should be to maximize performance. It can be begun by breaking the execution of any instruction into a series of steps, each taking one clock cycle, attempting to keep the amount of work per cycle roughly equal.
In the single cycle data path, each instruction uses a set of data path elements to carry out its execution. Many of the data path elements operate in series, using output of another element as an input.
The finite state control essentially corresponds to the several steps of execution depending on the instructions of the microprogram. Each state in the finite state machine will take 1 clock cycle. This machine will consist of several parts. Since the first step of execution is identical for every instruction, the initial state of the finite state machine will be common for all instructions. After the execution of the last step for a particular instruction class, the finite state machine will return to the initial state to begin fetching the next instruction.
To fill in the details of the finite state machine, we will first expand the instruction fetch and get next byte, dispatch, and then we will shows the states for the different instruction classes. State 0 is the starting state of the machine. The signals that are asserted in each state are shown within the circle representing the state. After state 0, the signals asserted depend on the class of instruction.
Design of Each instruction
To implement the finite state machine, we must first assign state numbers to the states. In this machine, there is needed 6 bits of state, and thus up to 64states. Each IJVM instruction needs from zero to sixty-one of these steps. Each IJVM instruction can be translated into hardwired one as those instructions.
In this paper, as an example only IADD, ISUB, IAND, IOR, DUP and POP instructions are translated into hardwired design. After translating, the finite state machine design is implemented by hardware description language such as Verilog HDL. This paper is shown the translation between microprogrammed control and hardwired control by using IJVM instructions.
In IADD instruction, the microprogram that runs on Mic-1 and interprets IJVM is the following ;
iadd1 MAR=SP=SP-1; rd
iadd3 MDR=TOS=MDR+H; wr; goto main1
Main1 PC=PC+1; fetch; goto (MBR)
So, Figure 2 is shown the design of finite state machine translating from microprogram.
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In ISUB instruction, the microprogram is the following ;
isub1 MAR=SP=SP-1; rd
isub3 MDR=TOS=MDR-H; wr; goto Main1
So, Figure 3 is shown the design of finite state machine translating from microprogram.
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In IAND instruction, the microprogram is the following ;
iand1 MAR=SP=SP-1; rd
iand3 MDR=TOS=MDR AND H; wr; goto
So, Figure 4 is shown the design of finite state machine translating from microprogram.
In IOR instruction, the microprogram is the following ;
ior1 MAR=SP=SP-1; rd
ior3 MDR=TOS=MDR OR H; wr; goto Main1
So, Figure 5 is shown the design of translation between microprogram and finite state machine. Each design is implemented by hardware description language. Among the languages, Verilog HDL is used in this translation between microprogrammed control and hardwired control.
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Figure 6 shows the finite state diagram for the microprogram for DUP instruction is the following ;
dup1 MAR=SP=SP+1; rd
dup2 MDR=TOS; wr; goto Main1
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Figure 7 is the finite state diagram for the microprogram of POP instruction followed as ;
pop1 MAR=SP=SP-1; rd
pop3 MDR=TOS; wr; goto Main1
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In this paper, Figure 8 is the complete finite state machine for translating a microprogram to hardware in the Mic-1 machine using IJVM instruction set.
In the finite state diagram, there is the first state s0 in which the branch is based on a portion of the opcode. The first step is independent of the instruction class; then the series of sequences that depend on the instruction opcode are used to complete each instruction class. After completing the actions needed for the instruction class, the control returns to fetch a new instruction. Each branch in this figure may represent one to several states. The arc labeled Start marks in which to begin when the first instruction is to be fetched.
4. Output of the Simulation
After the microprogram has translated to hardware by the finite state machine, the finite state machine can be implemented by Verilog HDL , among the Hardware Description Languages. We can write the control in Verilog depending on the states in the finite state machine. We can see the output by using the stimulus in the Verilog. It is shown by the simulation waveform. In the simulation result, the needed signals for the needed instruction are asserted and the others are de-asserted.
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The datapath control outputs depend only on the state inputs. The entries corresponding to input values 11_1110 through 11_1111 are not used, so we do not care what they contain. After state 0, the opcode field must be valid. The example output waveforms for simulation show the result for the output control signals. In Figure 9, the instructions translated are IADD, ISUB, and IAND. The simulation result is good for the output signals in each instruction. When state 0 which is assigned by main 1 is active in the first cycle, next instructions are sequentially active
In Figure 9, Figure 10, Figure 11, there are the sample output simulations for some IJVM instructions. Other instructions will have like these samples, but the asserted control signals are vary depending on the type of IJVM instructions.
This paper tends to realize how each field translates into control signals and be speed up by translating a microprogram to hardware without using actual hardware for the current and further. We can also understand the general structure of a hardwired control unit. Among the two kinds of techniques in the control unit, this technique is useful. This paper is aimed to reduce time consuming and ease to implement.
The Mic-1 CPU also uses the minimum amount of hardware. When IJVM can be implemented in a straight forward way in microcode with little hardware by the finite state machine, it can alternate to the faster implementations reducing the execution path length.
So, this paper gains the successful result. There are many kinds of recognition theories. This paper shows the translating of a microprogram used in IJVM instruction set to hardwired one.
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