The operation of reducing the width of the channel of a transistor is call transistor sizing. It is an effective technique to improve the delay of a CMOS circuit. “From the several recent studies  gate sizing consists of optimizing the power and area under some power and area constraints. The constraints can also include library-specific design rules, such as maximum fan-out load or maximum transition time.”When the width of the channel is increased, the current drive capability of the transistor increases which reduces the signal rise/fall times at the gates output. “The transistor was arranged such that the large p-transistors were above the small n-transistor and vice versa, so that no increase in rectangular area resulted from sizing .”
Transistor sizing to improve circuit performance has been an important design automation application for many years ago. Sizing of transistor is to balance the performance of single inverter. It more on RC time constant, first order approximation of time delays. The width of the channel is increased, the current drive capability of the transistor increases which reduces the signal rise/fall times at the gate output. The transistors on the critical path of a logic circuit are sized to obtain a better power and delay performance. The sizes of transistor are optimized on the critical paths of interest in order to minimize the delay, the power dissipation, and the area of the circuit at particular combinational logic circuit.
“The consideration of an equivalent inverter for a logic circuit is helpful in guiding a sizing process. The derivation of an equivalent inverter for a logic circuit is based on the fact that the effective channel resistance of a MOSFET is proportional to L/W that its length to width ratio. Thus, if a number of MOSFETs having length to width ratios of L1/W1, L2/W2, L3/W3, and so on are serially connected in a current path of the overall current path resistance will be ”
The equation from the book of VLSI Design, M Michael Vai, Ph.D, Boca Raton London New York Washington
Now, if these serially connected MOSFETs are replaced with single MOSFET that has a length to width ratio
The current driving capability will be maintained in the equivalent inverter. Similarly, it can show that the parallel connection of MOSFETs having length to width ratios of L1/W1, L2/W2, L3/W3, and so on can be represented by a single MOSFET of 
1.2 Problem statement
The optimization technique is based on simulated strengthening of the width and length. The optimization algorithm can be customized to proceeds suitable trade-offs between delay, power, and area, depending upon which parameter is more critical for the design under consideration.
These approaches go through from problems that make them difficult or unrealistic to be applied on real-life circuits with a discrete size library. Some methods make crude assumptions on the optimality criterion, assuming that minimizing a weighted power and delay product is the best power or delay tradeoff, while the problem is about constrained optimization. For the cost models, especially for delay and power are not realistic or are over-simplified to fit a specialized optimization technique. With the idea of solving an easier problem and then projecting the continuous solution on a discrete solution, there are some methods continuously sizes the gates. But a projective method does not necessarily yield a feasible solution. Some methods assume that the objective function and the feasible region is convex, which does not hold with accurate delay and power model.
The problem that is faced is:
- Whether or not for transistor sizing will be not all gates need to have the same delay.
- Whether or not for transistor sizing will be not all inputs to a gate need to have the same delay.
- Whether the thickness of the gate oxide and the potential in the substrate will affect the transistor sizing on circuit performance.
- Whether adjust transistor sized will achieve desired delay.
- How to choose perfect result for layout that come out with connected in series or connected in parallel.
- Whether the minimal delay time will drive to the load is shorter or longer.
There are some objectives need to be achieved in order to accomplish this project.
- To improve the output transition characteristic and the switching speed of a particular circuit block on the critical path.
- To provide the logic circuit with a desired performance for an equal current driving capability to both the pull-up and pull-down networks so as to equalize tPHL and tPLH .
- To learn how variation in the physical parameters of MOSFETs will affect circuit performances in low power.
- To analysis formulation of the capacitive and the short circuit power dissipation due to term of transistor sizes.
- To learn how transistor sizing will affect the performance of the circuit determined by the dynamic or transient response.
- To analyze the gate with respect to the different design metrics that due to energy efficiency set by the energy and power consumption.
1.4 Scope of work
The scopes of this project are to design the proper IC for transistor sizing and simulate it. During this project we will know how to design methodology of transistor sizing. The presented approach take marginally more times than the relating to a method of teaching or learning in which we can learn from our own discoveries and familiarities move toward is quite general and has guaranteed meeting properties and can be modified easily to minimize any objective function such as delay, power, or delay-power product. Mentor Graphic software is using to design, simulation and analysis.
“Since standard cell libraries are widely used, it is feasible to have a library of gates with transistors that are previously sized to give good power and delay trade-offs, and then the problem of optimization is to choose the best version of each cell to use. This provides a method with larger granularity, and because of the early binding of transistor widths, a computationally simple method of optimization.”