History Of The Radio Technology English Language Essay

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The radio technology is all the technology used for wireless communication based on transmission and reception of an electromagnetic signal, which may be broadcast, for example the transmission of television signals and GPS, or point-to-point such as WiFi or Bluetooth.

In recent years there has been a rapid spread and evolution of this technology caused by a continuous demand for higher data transfer rates, reliability, service quality, autonomy and mobility of the equipment. With the evolution of photolithography it has been possible to develop radio equipment with low dimensions and reasonable autonomy.

However, due to the great diversity of communication standards and protocols that operate on different radio bands caused the integration in silicon to be complex, and often an individual integrated circuit is used, independently, for each desired communication standard. So, instead of a device having only a universal radio system, it's common to have a large number of front-ends, which compromises the range, reliability and cost of the device.

The incorporation of a large number of radio front-ends raises serious problems to the manufacturers. The most complex is the interference between the radios within the device or with the exterior. To minimize this interference, it is common resort to build analog filters that are constructed so that the radio signal fulfills a given spectral mask. The development of this filters is however complex and expensive, especially if it�s dimensioned for high frequencies.

Another problem is the non-linearity of various electronic components that are used in the radio. These components affect the original signal, and create once again the need to increase the complexity of the radio in order to offset all of these non-linearities.

Thus, the evolution of wireless communications technology will necessarily increase in the digital domain of the radio, as has been taking place in other areas of mobile technology. This evolution will allow to overcome problems such as the quality factor of the analog filters and the creation of phase or heat noise.

1.2 Software Defined Radio

The Software-Defined Radio was first introduced by Joseph Mitola as a concept of the future of the radio [MITOLA-SDR].

To Mitola, a radio would be able to modulate and demodulate any signal entirely in software, regardless of the standard, operating frequency or bandwidth of the signal. The transmitter had, in this vision, the ability to create any waveform, and translates it to any frequency to be later converted to the analog domain, by an DAC, and then amplified and sent. On the other hand the receiver should collect a certain bandwidth of the spectrum, amplify it and convert it to the digital domain,with an ADC, after that conversion the process of detection and demodulation of the signal would be carried by software.

If we assume that the resources needed to implement the Software-Defined Radio are able to work at a satisfactory bandwidth, then we see solved the problems of production costs, power, thermal and phase noise and distortion present in the current solutions. Besides this, an SDR provides a universal front-end, i.e. the same front-end can be used for various standards and can operate in different frequency bands or with different protocols. Moreover, unlike traditional approaches, this radio enables simultaneous reception of several channels. Being another benefit of this type of radio the ability to add any new functionality with a simple software update.

Despite the enormous potential that this concept has, in reality there are some technological problems that affect this implementation, those are the following:

- The antennas need to have a high bandwidth and low losses;

- The amplifiers must have a wide linear dynamic range of operation and low power consumption;

- The A/D and D/A must have a high sample rate, high resolution and dynamic range, a high bandwidth, low cost and low power consumption;

- The digital processing units (DSP) must be capable of operating at high speeds that allow the processing of a wide bandwidth in real time.

There are already in the market devices that are named as "Software-Defined Radios", such as the USRP[ettus] and WARP [WARP]. This systems are primarily directed to research and enable bandwidths of about 100MHz. In its receiver architecture there is a demodulator that translates the signal to an variable intermediate frequency and then the resulting signal is sampled using two ADCs with a sampling frequency of about 160MSamples per second and 16-bit resolution. The processing is performed with a combination of DSPs and a FPGA, thus providing the possibility of reprogramming and reconfigure the system.

1.3 Cognitive Radio

Traditional wireless networks work in a license-free spectrum, with is called the ISM bands, the ISM bands are parts of the radio spectrum used for personal, industrial, scientific and medical uses. As this bands became crowded with all the new uses, as for example WiFi and Bluetooth, the need for a new system is becoming alarmingly important. The expected solution will be the Cognitive Radio.

Cognitive radio is a system based in a Dynamic spectrum access (DSA) from a secondary and unlicensed user. The DSA works by opportunistically accessing a licensed spectrum band owned by the so called �primary users�, this access, nevertheless, is subject to some regulations. The usage of this method would be expected to alleviate the current spectrum use.

Cognitive Radios work by sensing the licensed bands and detecting the occupation of those. If one of those spectrum bands are temporary free then secondary users will occupy it.

However the practical implementation of such devices is surrounded by a lot of challenges both in software and hardware. First, there�s a need of synchronization, when two communicating devices decide to change band, they must synchronize with each other to resume the communication. Therefore, there is a need to create protocols to allow to share information about the available frequency band list in each location of the devices, bandwidth and type of modulation that is going to be used and for the re-sync process.

In the Hardware there is need to sense the entire viable spectrum and detect witch bands are being already used. If the band is not being currently used, the CR should be able to change the frequency of the transmission to allocate into the available band. It should also detect if any of the primary users want to start to use their rightful band and then stop the transition.

1.4 Analog to Digital Converters

The A/D converters are a key component of a Software-Defined Radio and also one of the key elements that hider to implement this type of architecture.

One of the desirable properties of an ADC is the possibility to sample a large frequency spectrum. However, for large bandwidths of operation, in orders of GHz, with the present technology we start to have a low ENOB. The decrease of dynamic range for this bandwidths would create quantization errors that will limit the reception in this type of radio.

Thus the conversion between the analog domain and digital is technological limited by the ADC. It would be desirable that they had:

- A high number of quantization bits in order to induce the smallest possible error;

- A wide dynamic range so that signals with high power will not cause other information with lower values to be lost;

- A large sampling frequency to cover a high bandwidth;

- Reduced price and power consumption. It is not expected that these needs are met in the coming years, so need to find alternatives.

Currently the best ADC in the commercial market is the ADC12D1800 [TI_ADC] from Texas Instruments with 3.6GSPS and 12bit with an ENOB of 9.4bits and a SNR of 58.5dB, and typically consumes 4.4W.

1.5 Author publications

As the result of some work done by the author the following publication in a conference was made:

1. D. Malafaia, �Real Time Front-end for Cognitive Radio Inspired by the Human Cochlea� RWW, Texas, 2012

2 Bio-Inspired front-end

2.1 Cochlear radio

Nature have found a way to create a sampling system that can sample a large bandwidth and without high power signals effecting low power ones thous maintaining the dynamic range of the system[Albuquerque_article].

This was archived through evolution of the auditory system of mammals. Humans can cope with a dynamic range of 120dB and several octaves of bandwidth.

It works as follows, the sound enters in the ear auricle and is guided by the external auditory canal to the tympanic membrane. Struck by the sound-waves, the tympanic membrane oscillates and make the ossicular chain (malleus, incus and stapes bones) reproduce and amplifies the oscillation into the inner ear and later enter in a curled tube located at the inner ear - the cochlea, this is important because it provides the impedance matching between the outer ear and the inner ear. The cochlea then contains several membranous sections, which are filled with watery fluids. The ossicular chain vibrate the fluid, thus making nerve terminations, hair cells, in the basiliar membrane to sense this mechanical vibrations and convert them into electrical pulses. This electrical pulses are sent via the cochlear nerve and travel then trough the nervous system reaching the primary auditory cortex in the brain where they are processed[Hearing_book].

Creating an analogy to RF we can say that the ear auricle works as a antenna, the external auditory canal as a waveguide, the cochlea as a a filter bank, the nerve terminations as mid-end ADCs, the nervous system as a data-bus and the primary auditory cortex is then a DSP.

2.2 Proposal for an SDR front-end based on hybrid filter banks

2.2.1 Front-End proposal

An alternative that would replace a single ADC with the requirements that would be required for a SDR and which are not currently possible to be achieved, and ensuring a high-bandwidth operation, involves the following proposal.

The RF signal coming from the antenna is divided into M contiguous frequency bands, through a bank of analog high-frequency filters. These bands are passed to an intermediate frequency and are then converted to the digital domain with an ADC for each channel. As the spectrum of the input signal is divided into M signals with M less bandwidth, then the sampling rate of ADC becomes M times smaller. Thus it is possible to obtain an even better negotiation with the conversion resolution, which can be increased by \sqrt{M}

bits compared to conventional receivers.

This approach has the following advantages:

- The smaller bandwidth of the M divided signals requires the use of a M time lower sampling frequency for each ADC;

- The need for a lower sampling rate of ADC relaxes the requirements, allowing a better engagement with the resolution conversion, making it possible to improve the it in \sqrt{M}

;

- A higher resolution conversion will lower quantization noise improving the SNR of the system;

- The fact that the bandwidth of the input signals a the ADC is lower, will result in a reduced noise emission of heat improving the SNR of the system;

- The reduced bandwidth of each channel also enables to relax important factors such as the non-linearity of the low noise amplifier;

- Since we are converting small parts of the spectrum in each ADC we will have less problem with jamming signals with a lot of power and centered in other frequencies that would require to change the dynamic range in such way that we would lost signals with less power.

2.2.2 Hybrid Filter Banks

The hybrid filter banks are then one solution to avoid the limitations of the current A/D converters. These allow improving the resolution of the conversion and its dynamic range. However, this approach creates a new problem, the need to ensure perfect reconstruction of the input signal. That is, it is intended that the signal is divided into several bands in analog filter banks and then can be reconstructed in the digital domain without loss or distortion of information.

So, to archive a perfect reconstruction is necessary to very accurately know the characteristics of analog filters in order to be able to generate the digital filters such that the transfer function of all the filter bank is only a delay. However, in practice the perfect reconstruction is impossible due to the nonideality of the elements in the analog filters so that the objective is to obtain very approximate models of reality in order to create a filter bank with almost perfect reconstruction.

2.3 Digital Signal Processing

For any Cognitive-Defined Radio and especially to a cochlear radio because this component will be responsible for the reconstruction and processing of the signal received. The processor will receive the ADC data and reconstruct it to approximately the original signal and then use it for the function needed by the user. Another feature of any cognitive-defined radio is the reconfiguration, to allow the transfer of new software to implement any standard in the receiver or any new functions.

The processor can be a DSP, dedicated ASIC or an FPGA. A DSP can consume a lot of power and works with a serial processing.A ASIC is a very fast hardware that implements any function even parallel ones, and enables a cheap and low power solution for any radio. A FPGA can offer the same performance as a ASIC but usually consumes more power and is expensive, but is reconfigurable.

2.4 Reconfigurable Hardware

2.4.1 FPGA

Though the times many tools have been used to create electronic logic, since SPLDs, PROMs and others.

One on the most recent tools for testing, prototype implementation and even as a final product is an FPGA (field programmable gate array). These circuits contain an array of a large amount of logic blocks that can be programed to interconnect as desired by the user. Each of that block is usually constituted by LUTs, multiplexers, flip-flops (FF) and some other additional logic, and can perform simple tasks, from a simple NOT gate to a synchronous sequential state machine.

In the FPGA that was used in this thesis, a Virtex6[CLB_virtex6], these blocks are called CLBs(configurable logic block), they are grouped in slices and they can be a common ordinary slice or a DSP slice, the DSP slice have another kinds of logic, a more specific logic for DSP operations.

In order to the connections between CLBs to be flexible, those need to be reprogrammable, leading to small frequencies of operation created by large capacities from the multiple possible paths. But as we have access to a lot of logic, we can create complex parallel processing than can allow a higher throughput than for example a pipeline processor, common in a personal computer.

2.4.2 VHDL

To take all the possibilities from a FPGA we require a way to �program it� to do any operations needed by the user, as in a processor a user does not program in machine code, neither in a FPGA we connect directly each block, but a compiler is used for that. A circuit system is then write in hardware description languages (HDL), where the circuit is described as well as the inputs and outputs. HDLs were originally created for simulation and they are still used for such but it started to be used to synthesis real Hardware as well. It's important to note that not every circuit designed as a behavioral simulation may work in a real circuit and the code can have instructions that may be implementable but not behave correctly in reality.

Whit this method of programming we allow parallelism by creating a large amount of independent process running at the same time.

Industry uses majority two HDLs, the VHDL and Verilog, for this thesis VHDL was used to implement the hardware but some blocks not created by the author are written in Verilog, as we can interconnect simply between a Verilog and VHDL blocks, those do not cause any trouble.

2.5 FML605 board based in Virtex6 XILINX FPGA

2.5.1 Integrated synthesis environment

The VHDL code needs to be translated to a configuration data to be loaded into the FPGA. For this use we use the XILINX ISE 12.4/13.3[ISE] that will translate and synthesis the VHDL code into a bit-stream ready for transfer.

When we write a VHDL code in the ISE, it synthesis that code, generating the hardware and connections that implement the behavior of the system created. Syntax errors are then detected at this point and must be corrected before moving anywhere further.

In addiction to the code written in VHDL, the user creates a constraint file. This constraint file has all timing requirements needed in the project and in/out connections of a VHDL port to a pin of the FPGA circuit. The timing requirements permits to ensure that a certain signal or clock have a certain delay and the pins can drive of read a digital signal that is needed for the project.

The constraint file is used in the Implementation phase of the code, this step generates a netlist, from the previous generated hardware, that is mapped into the FPGA that we are using, allocating the resources in specific locations to permit the best routing and also providing the interconnections to that allocation. This creates a FPGA configuration file and a report of the used resources as for a estimation of the power consumption.

This configuration file is then programed intro the FPGA and it's ready for use.

2.5.2 FML605 board

For this thesis a Virtex6 XC6VLX240T-1FFG1156 was used, each slice of this FPGA is constituted by four six-input LUTs, multiplexers, four FlipFlop/Latches and four FlipFlops. The most important characteristics of this FPGA are the follow:

The evaluate board that we use with this FPGA is the XILINX FML605 with the following characteristics[Ml605Caracteristics]:

- FPGA Virtex6 XC6VLX240T-1FFG1156;

- Configuration through USB2.0 or Flash memory;

- Power supplied through transformer;

- DDR3 (512MB) and Flash memories (34MB+16MB+8Mb);

- 200MHz differential oscillator and 16MHz socket clock;

- SMA sockets for external clock or user GPIO;

- LCD display, LEDs, Push-buttons and Switches;

- Communication through RS232, Ethernet, USB2.0, GTX and PCI Express.

2.6 4DSP FMC108 8-ADC 250MSamples board

For the Analog to digital sampling we used a ADC board from 4DSP. 4DSP is a Nevada,USA based corporation that develop and manufacture commercial off the shelf data-conversion boards (ADCs and DACs) and respective FPGA Intellectual Property. Is also member of Xilinx Alliance Program, so the majority of products are developed directly for Xilinx evaluation boards.

The specific board used is a FMC108 is a 4DSP board with 4ADCs, each of which has two channels, as each channel is being used individually 8 analog signals can be sampled at the same time. It also offers a connection for a external clock and another one for a external trigger.

Each ADC channel samples at 14-bit and at max 250Msps, the ADC clocks can be clocked by the internal clock source that offers some level of selectivity freedom of the clock frequency, but it can also be clocked externally by any frequency from 0 to 250MHz.

The ADCs used on the board are TI's ADS62P49 dual channel 14-bit 250Msps ADCs with a DDR LVDS output. The frequency of the analog input signals in this board must be between 3MHz to 650MHz as there is a AC coupling to get a better SNR from the ADCs, the input voltage can go as high as 2Vp-p (10dBm), and the input is tuned at 50ohm impedance.

The clock tree offers some flexibility and some high performance. A AD9510 PPL and clock distribution IC are the base of the clock tree and a VCO is connected to one the clock inputs (the other clock input can be used by a external clock). A external reference 100MHz crystal is then connected to the VCO.

The board also has two ADT7411 devices that monitors the temperature of the ADCs and the clock input frequency for each ADC, each of this devices controls two ADC chips.

The input channels, clock and trigger are connected by a SSMC connectors in the front panel, this connectors are not a standard so SSMC to SMA cables were used to connect to other laboratory equipment.

As the temperatures of the board can reach 85�C during use and to avoid damage a external fan was connected to the board and is powered by the ML605, that allows the FMC108 being used at not more than 50�C.

The board connects via FMC. 4DSP provides with the board the respective firmware based in their high-level �Stellar architecture� written in VHDL and allowing sampling each of the channels individually at each time.

2.7 Matlab simulation of the behavior of a reconstruction filter bank with subsampling

All the simulation process was done using MATLAB(MATrix LABoratory)[MatlabNumInstante] that is an IDE with its own high-level programing language. It�s vocational to matrix numerical calculus, and got functions for plotting,for working with imaginary numbers, Fourier transformations and other tools.

For simplicity, we will study the case where M = 2 or when the hybrid filter bank has only 2 channels.

In this case the analog signal is filtered by the analysis filter bank in two frequency bands which are then passed to the digital domain by an sub-sampling ADC. The signal is then interpolated by the number of bands and then filtered by the synthesis filter bank. After this the 2 signals are then summed giving rise to the reconstructed signal.

The previous system is equivalent to the following bank-digital filters:

Let's now see the output equation of the entire system, after passing through the decimation we get the signals:

\left\{ \begin{array}{c}

V_{0}(z)=\frac{1}{2T_{s}}[X(z^{\frac{1}{2}})\tilde{H}_{0}(z^{\frac{1}{2}})+X(-z^{\frac{1}{2}})\tilde{H}_{0}(-z^{\frac{1}{2}})]\\

V_{1}(z)=\frac{1}{2T_{s}}[X(z^{\frac{1}{2}})\tilde{H}_{1}(z^{\frac{1}{2}})+X(-z^{\frac{1}{2}})\tilde{H}_{1}(-z^{\frac{1}{2}})]

\end{array}\right.

so, the reconstructed signal will then be:

\hat{X}(z)=V_{0}(z^{2})F_{0}(z)+V_{1}(z^{2})F_{1}(z)

ReplacingV{}_{1}

and V{}_{2}

we have:

\hat{X}(z)=\frac{1}{2T_{s}}[\tilde{H}_{0}(z)F_{0}(z)+\tilde{H}_{1}(z)F_{1}(z)]X(z)+\frac{1}{2T_{s}}[\tilde{H}_{0}(-z)F_{0}(z)+\tilde{H}_{1}(-z)F_{1}(z)]X(-z)

define from now onT_{0}

and T_{1}

as:

T_{0}(z)=\frac{1}{2T_{s}}[\tilde{H}_{0}(z)F_{0}(z)+\tilde{H}_{1}(z)F_{1}(z)]

T_{1}(z)=\frac{1}{2T_{s}}[\tilde{H}_{0}(-z)F_{0}(z)+\tilde{H}_{1}(-z)F_{1}(z)]

WhereT_{0}

� is the distortion, which allows to archive perfect reconstruction if only it is a delay or a constant. And T_{1}

is called aliasing and must be 0 in order to have a linear frequency response, this is caused by the decimation of the signal.

The Laplace transform of the output signal is then:

\hat{X}(e^{jw})=\ensuremath{X(e^{jw})T_{0}(e^{jw})}+X(e^{j(w-\pi)})T_{1}(e^{jw})

in matrix form it's:

\left[\begin{array}{c}

e^{-jw_{q}d}\\

0

\end{array}\right]=\frac{1}{2T_{s}}\left[\begin{array}{cc}

\widetilde{H}_{0}(e^{jw_{q}}) & \widetilde{H}_{1}(e^{jw_{q}})\\

\widetilde{H}_{0}(e^{j(w_{q}-\pi)}) & \widetilde{H}_{1}(e^{j(w_{q}-\pi)})

\end{array}\right]\left[\begin{array}{c}

F_{0}(e^{jw_{q}})\\

F_{1}(e^{jw_{q}})

\end{array}\right]

As we want to know the synthesis filters we then have,

F(e^{jw_{q}})=2T_{s}H^{-1}(e^{jw_{q}})T(e^{jw_{q}})

In witch w_{q}

is the arbitrary set of frequencies with q = [0 � Q-1].

Assuming that we want the synthesis filters to be FIR filters which have the advantage of being always stable, although it loses part of the impulse response of the filter compared to the IIR filter implementation. So in order to obtain the response of synthesis filters in the time domain we have to solve,

\left\{ \begin{array}{c}

F_{1}=W^{H}f_{1}\\

F_{2}=W^{H}f_{2}

\end{array}\right.

In witch (.)^{H}

is the conjugate transpose and W_{q}^{H}=[W^{0}W^{-q}...W^{-q(L-1)}]

with W beingW=e^{j\frac{2\pi}{Q}}

and L is the number of coefficients of the FIR filters of the synthesis. Generally, we use a Q greater than or equal to L resulting in an indeterminate system where we can find a minimum L_{2}

.

In order to f we have:

\left\{ \begin{array}{c}

f_{1}=W^{+}F_{1}\\

f_{2}=W^{+}F_{2}

\end{array}\right.

in witch W^{+}

is the pseudo-inverse of the Fourier transformation matrix W , in other words W^{+}

is the product of the inverse matrix W with the identity matrix[reconstruction_hfb].

So implementing this method in Matlab, with two 3rd order symmetric filters bank. The reconstruction to a impulse of 1 amplitude, got the following mean square error.

2.8 Interchannel phase delay effect on HFBs

[Z� Pedro work here].

3 Accurate Analog Filter Bank Measurements

3.1 Development of code in Matlab for interaction with a GPIB Oscilloscope and Signal Generator

The majority of the measurement equipment used in RF communicates trough GPIB (IEEE-488), that is a short-range protocol created on the late 1960s by Hewlett-Packard for use in laboratory equipment and it became the standard. It uses a parallel bus with individual control lines.

All the equipment that we had used had a GPIB connector to interact with them. For use with our personal computer we then used a GPIB adapter to Ethernet or to USB. There are 2 ways to start the serial connection from Matlab the VISA and the RS_CONNECT, we define the IP from the equipment and associate it in Matlab, the equipments both use the Agilent protocols that need to be installed on the computer. A basic command to know if everything is connected is to query for a '*IDN?' GPIB command, if everything is working the equipment should respond with it name. After confirming this we are ready to send any command and receive any response.

3.2 Development of code to interact with the oscilloscope and the signal generator to create a frequency sweep and analyzing the resulting data in a sampled transfer function

So the first step to create a frequency sweep and measuring it result is to connect Matlab with the SMU200A generator and the DPO72004B oscilloscope and query them for a '*IDN?' to see if everything is working as expected. After this we turn off the RF of the generator to change the configurations. We choose the output power, and the initial frequency.

From the oscilloscope we choose to acquire in sample mode and at real time. We then choose the sample rate that is the frequency of sampling, and the record length that is the amount of samples that we are going to acquire. Now this is a tricky selection because only some frequencies are selectable from the rage of the oscilloscope, so after the selection a query should be made to know if the sample rate was successfully changed to what we had previously defined. Then for each of 4 channels we do the following: turn the channel on, choose the DC coupling, 50ohm termination, 0 position and offset, and the scale in volts. Now the scale is very important because different scales can have different behavior, so every channel should have the same scale, this scale can also be changed in mid the measurements but as we are going to see further in thesis this will add additional errors to the measurement.

After this we should choose the AUTO trigger, this allow for the trigger to be a software trigger sent by the PC user.

Then we define the waveform data transfer definitions: �DAT:ENCdg SRIBinary� to define the output data format as a integer and to transfer first the least significant byte, then specify the number of bytes per data data point using �WFMOutpre:BYT_Nr 2�, the we specify the portion of the waveform that we want to transfer using �DATA:START 1� and �'DATA:STOP 'n'� where n is the number of samples that we want to sample.

With all this ready we activate the output of the generator and now it's time to start the sweep.

We run this process 'n' times where n is the number of frequencies of the sweep:

1 - We define the 'n' frequency of the generator;

2 - Wait at least 2ms for the generator to stable the output;

3 - We start sampling with the oscilloscope with 'ACQUIRE:STATE RUN' that will sample a single sequence;

4 - Then for each of the 4 channels we do the following: select the data source to the channel then we run the �CURV?� command and the waveform of that channel is transferred;

5 - We then use that values and run a FFT and save the maximal point and its frequency for each channel and save it.

We now have the transfer function of the frequency interval selected for each channel.

3.3 Characterization of the Oscilloscope

Legitimation with a laboratory experiment that is possible measuring S parameters of a filter bank with a signal generator and an ADC.

With this lab experience we want to obtain the S parameters with a Network Analyser in a frequency interval of a filter bank of 2 channels. This experience will be made using all the system apparatus including the filter bank, a directional coupler e the cables used to connect the components. After the measurement of the S parameters with the Network Analyser the frequency response of the filter bank will be measured using a signal generator and a oscilloscope. This experiment will me made using as input in the filter bank a sinusoid with a determined frequency and observing the output of the filter bank, this way will be able to measure the variation of amplitude and phase that the system provokes in the signal. This procedure will be repeated for every frequency that were analyzed in the Network Analyzer. If the reflections of the circuit are negligible (S11, S12 and S22) then we shall have similar results.

So this experiment is divided in 2. The first one is the measurement with the Network Analyser and the second one is the measurement of the response in frequency with the oscilloscope

3.3.1 Used material

In the first part with measurement of the S parameters with the Network Analyser the material used is:

- Filter bank with 8 channels (50MHz-100MHz)

- ZX30-9-4-S+ (Directional coupler)

- Agilent E8361C (Network Analyser)

- VNA calibration kit

- 6x 50Ohm male SMA Loads and 2x female

- 2x CBL-1.5FT-SMSM+ (Coaxial cable of 50Ohm with 1.5ft length)

- 2x CBL-3FT-SMSM+ (Coaxial cable of 50Ohm with 3ft length)

The second experiment will be the measurement of the frequency response with the oscilloscope and the material used is:

- SMU200A Signal Generator

- Oscilloscope DPO72004B (20GHz) with Ethernet communication

- PC with Matlab to interact between the generator and the oscilloscope

- Filter bank with 8 channels (50MHz-100MHz)

- ZX30-9-4-S+ (Directional coupler)

- 6x 50Ohm Load male SMA

- 3x CBL-1.5FT-SMSM+ (Coaxial cable of 50Ohm with 1.5ft length)

- 2x CBL-3FT-SMSM+ (Coaxial cable of 50Ohm with 3ft length)

3.3.2 Experimental assembly

The experimental assembly of the first experience is the following:

After the calibration, one of the channels of the Vector Analyzer must be connected to the 3ft cable that connects to the directional coupler, another channel should be measuring the 1st and the 2nd channel of the filter bank and the 2nd channel of the directional coupler, every other outputs must have a 50ohm load.

The experimental assembly of the second experience is the following:

Between each connection it appears in feets the length of the cable that we are going to use.

In the filter bank we only be using the 2 channels of the lowest frequency, so to the other channels not to interfere with the result by the fact that they are not adapted to 50ohm then 50ohm Loads must me connected to the output.

The computer must have installed the �Agilent IO Libraries Suite�, that haves the libraries necessary to communicate between Matlab and the equipments.

3.3.3 Procedure to the first experiment

Initially the PNA should be calibrated, the connections of the PNA should be of the same type, sma female, to fit directly on the cables we use.

After this we should measure the S-parameters of the two filters and the second directional coupler output between 50MHz and 65MHz, and sampled at 1501 points spaced frequency of 10kHz (50Mhz, 50.01Mhz, ... , 65MHz).

The data has to be saved with the extension �S2P� (Touchstone format) and loaded on a computer with Matlab to a future analysis .

3.3.4 Procedure to the second experiment

Since filters were designed to have very attenuated reflections is expected that the frequency response in both amplitude and phase are approximately the S21 parameter of the system.

To validate this assumption the following Matlab code was made:

1 - Set the signal generator frequency to 50MHz and generate a sinusoid;

2 - Set the oscilloscope to work at 250MSamples with 50000 samples per measurement;

3 - Acquiring the three channels of the oscilloscope and run a FFT to know the peak value of the FFT that is not the first one, thus to avoid DC input and the FFT image;

4 - Increase the generator frequency by 10kHz;

5 - Repeat steps 2,3 and 4 until we reach the 65MHz.

3.3.5 Result analysis

Let us now try to validate the assumption that the response obtained by Experiment 2 should be approximately the same as the first. To this to happen the values for the 3rd channel (coupler output) must be multiplied by the inverse of the response obtained from the coupler in the VNA, in this way we can obtain with some accuracy what signal was originally injected into the system for each frequency. Then the values obtained for the 1st and 2nd channel filter bank acquired by the oscilloscope are compared to the recovery of the signal injected into the system to obtain the phase shift and amplitude that they caused. So to obtain the response in phase and amplitude of the filter bank we made as follows:

1 - The oscilloscope output from the coupler output is divided by the S21 parameter from the coupler obtained from the Network analyzer for each of the 1501 frequencies. We now have the reconstructed original signals;

2 - The phase response of each channel is measured by subtracting the angle of the oscilloscope output of the 1rst channel and the 2nd by the reconstructed original signal for each of the 1501 frequencies;

3 - The magnitude response of each channel is measured by dividing the of the oscilloscope output of the 1rst channel and the 2nd by the reconstructed original signal for each of the 1501 frequencies.

3.3.6 Results

The results show that the filter bank is non-linear because for different signal powers the response is different, probably the largest supplier of this non-linearity is the inductors that are used in the circuit.

As for the comparison between the data we got from the Network Analyzer and the Oscilloscope the relationship is:

and for the 2nd channel:

So what we can see from the graphs is that out of pass-band of the filters, where the attenuation is very pronounced, we have a large error in measurement, this is due to the poor resolution of the oscilloscope that acquires at 8bit (with a even lower ENOB ).

We also try to write a auto-scale script, that if the signal during the frequency sweep would be to low or to high, the scale would be changed, the results show that we got non-linearity from the auto-scaling.

Anyway the conclusion is that the remaining S-parameters besides the S21 seem to be negligible, and the error we have during the pass band is what would be expected from a low resolution ADC reading from a very attenuated signal.

3.4 Characterization of the cables

Is intended to study the influence of the use of a coaxial cable in the measurements. It would be expected that the effect were approximately a pure delay, to confirm this statement measurements will be made in a Network Analyzer in order to study the results.

3.4.1 Transmission lines

An analog transmission line causes a certain delay of phase which depends on the following equation:

\theta=l\frac{360f_{0}}{vp}

in witch \theta

is the phase delay,l

the length of the line,f_{0}

a the signal frequency, an vp

the propagation velocity in the line.

We will evaluate a coaxial cable with triple shielding from mini-circuits, the cable in question is a CBL-3FT-NMNM+, a 3Feet ( aprox. 0.9144 meters) cable, with a male sma connection in both terminations. This cable will be evaluated in frequency from 50MHz to 100MHz that will be the interval of frequency that we are going to use it in laboratory. The manufacturer tells of a velocity factor ( velocity factor in relation to the speed of light), that is around 0,7.

3.4.2 Experiment

The material used was:

- Agilent E8361C (Network Analyzer)

- 1x CBL-3FT-SMSM+

The Network Analyzer must be configured to use 0dBm of power, with the initial frequency in 50MHz and finishing in100MHz, with a sampling of 5001 points and used an average of 16 points. Then, the Network Analyzer need to be calibrated and then the cable in question measured.

Using the equation (1) we expect to see that we expect to see in theory a phase shift to the frequency 50MHz of,

\theta=0.9144\frac{360*50*10^{6}}{0.7*299792458}=78.43\text{�}

The S parameters results were the following,

It is clear that the parameters S12 and S21 range from 0.98 to 0.99 so the cable passes almost all the power in both directions. The reflections are less than 0.014.

And in phase,

Also lets look at the derivative of the S21,

With a mean of -0.276*10^{-3}rad/Hz

and a variance of 97.167*10^{-9}rad/Hz

.

And the phase of S21 at 50 MHz: -79.1156�, very close of what would be expected.

The theoretical calculated phase is slightly lower than that obtained, this is due to the lack of accurate knowledge of the velocity factor of the cable, but it's sufficient to confirm the values obtained. The cable phase is nearly linear, and different noise is created during the measurement by the equipment. The cable can then be considered an ideal delay without a significant error.

3.5 First tests with the ML605 development board with a Virtex-6 FPGA

3.5.1 Performance and Resource Utilization Benchmark for realtime implementation of FIR filters

As a base requirement in order to have a feasible hardware implementation, the filter bank sampling rate was chosen to be up to 100 MSPS. The number of filters per channel was set to 8 and the number of channels should be less or equal to 8. Moreover, each filter must have between 32 up to 64 reconfigurable coefficients.

Concerning the development tools, the Xilinx Integrated Software Environment (ISE) v13.2 and the Xilinx CORE Generator were chosen in this design and a Virtex6 LX240T was chosen as the target FPGA.

For this implementation, each of the filters is connected to the exterior ports trough register banks. Although this approach requires extra hardware resources, its does also reduce the critical path and therefore enables a increase in throughput.

An FPGA-based implementation containing 64 filters was made. In this implementation, each filter was configured to produce a throughput of 80 MSPS, using a 400 MHz clock reference signal. As can be seen, the implementation using 32 coefficients per filter and 17 bits of precision is the only one that meets the specified operating frequency of 400 MHz.

This table summarizes the main implementation results when is implemented with 64 filters using a 400 MHz reference clock. The main difference from the previous experiment is the lower sampling rate of 50 MSPS and the higher order of the filters. Observing Table 9 it is possible to conclude that all variations excluding the second one that has 64 coefficients per filter and uses full precision are feasible.

The implementation results when is configured to implement 64 filters using a 400 MHz reference clock are summarized in this table. In this implementation, each filter was also configured to produce a throughput of 80 MSPS but using fewer coefficients than the previous experiment. This way, less hardware resources are required (specially the DSP48E1 slices), which in turn alleviates the timing enclosure. The obtained results show that all implementation variations for this experiment are feasible.

The obtained results allow concluding that high order filters, that is, filters with more than 35 coefficients are hard to implement on the target FPGA and are only possible for lower sampling rates. Moreover, if the desired filter bank implementation requires more than 64 filters, this will result in a design that is very hard to implement and is only feasible is the filters have lower orders.

Regarding timing enclosure, the surrounding logic will have a negative impact on it, which means that a full design containing not only the filter banks but also the necessary logic to implement the entire system will have worse figures of merit.

The obtained results also indicate that dense designs occupying more than 60% of the available DSP48E1 slices are only feasible for low sampling rates up to 50 MSPS. At last, the obtained results show that a sampling rate of 80 MSPS when the filters are using a clock signal of 400 MHz seems an interesting implementation relation for both case studies.

3.5.2 Creating firmware to interact with a laptop via serial port for a future change in the coefficients of FIR filters in real-time

To interface with the FIR filters to change thee coefficients of the FIR filters, we used a open core RS-232 interface, as the serial connector from the ML605 emulates in the Operative System a RS-232 port the MATLAB can still use the serial commands to interact with the board.

The RS-232 core have a simple interface, all we need to give is the data in and data in ready, data out and data out ready and a clock, this clock is used to create the baud-rate that can defined in VHDL.

To test the reconfigurable filters, we simulate the system by creating a interface to send values to a FIFO via serial com, to receive them via com, and to change the coefficients.

After the VHDL was done it was then used has a base to the filters in the FMC108 system firmware.

4 Realtime Cochlear Front-End

4DSP provides a reference solution of software and firmware for the ML605 development board. The design flow of this reference solution is based on 4DSP Stellar IP flow, this method of design organizes the firmware in blocks that 4DSP calls:

- Star: for a functional block with a specific task;

- Wormhole: for a connection between two stars. A wormhole comprises of one or more signals in either one or both directions;

- Constellation: A collection of stars that forms the top level of the firmware.

The firmware was written in VHDL with some level of complexity so a previously study of the firmware and reverse engineering was needed for the modification of the VHDL code.

There is also a executable that runs on the personal computer and communicates with the firmware trough the Ethernet port, a source code of the C++ code is provided. C++ is a multi-paradigm and general-purpose programming language. Is one of the most used programming languages, and is a derivation of C with the most important enhancement being the added Classes, so the lexical of C is still applicable.

4.1 Initial tests

To start the test we open the source VHDL code and generate the bit-stream at the 12.3 XILINX ISE but the generation gives an error, some clock signals have a higher settling time than the constraints for this design.

This constraint validation is made with some considerations that varies from FPGA to FPGA and came with an associate incertitude, so even though they were not achieved and as 4DSP says that the firmware works we will ignore this alert given by the tool but we will work with some precautions because we are in the limit, one of the precautions is to have the FPGA with a temperature as low as possible.

After the .bit file generated, we connect the FMC108 to the ML605 and connected the JTAG-USB cable into the PC and also the Ethernet cable.

The FPGA was programmed via iMPACT with the .bit file and a test signal was connected to 1 of the channels of the ADC board. Running the executable in the PC, 8 .txt files were created, each one to each ADC, the samples are written in ASCII and separated by a newline.

The test then made to each channel individually and the conclusion taken was that the system working correctly, the max number of samples for each ADC is of 32768, as the output FIFO in the hardware is of 64Kb and each sample occupies 16bit and each channel had a different DC offset when not in use.

4.2 Creation of a protocol in the C++ software to interact with Matlab

The application has been changed to read from a file, this file is a shared memory space between Matlab and the Application that reads the ADC. When we begin to prepare for sampling, the application is already running and is waiting for share memory to be written by Matlab, it then reads the data, writes in each channel file and when the burst is over it writes in the shared space. Matlab reads detect the change and stores he information. Whenever we want to measure again, all we need is to write into that file again to start the sampling.

To start a frequency sweep we run a Matlab code that does create first a shared memory that can be accessed by the program that will interface directly via Ethernet with our FPGA, this shared memory is called �txrx.txt�, we choose the �txt� extension for easy debugging but it could have any extension or even none. This txt file is going to have always a ASCII char in it, that char is used as semaphore between the two programs, when initialized by Matlab the '9' ASCII char is written, and then the executable that will make the interface with the FPGA is called from the same path that the Matlab workspace. The C++ code initiates the FPGA and start reading in polling the txt waiting for an order to proceed with a sampling. Matlab then, when everything is ready for a ADC sampling erases the communication file and writes a '1'. The C++ program reads the '1', and starts the sampling for the 8 ADCs, when all is ready it then writes a '0' on the commutation file and creates 8 files entitled 'adcX.txt' where X is the ADC channel from the FMC108. The Matlab code interprets the '0', reads the ADC files, save those in memory and when is ready for another sampling then it writes a '1' again and the same happens. If there�s no need for more samplings is written a '2' in the communication file and the C++ program closes and Matlab erases all the files that were created (NOT REALLY s�o apagados no inicio do programa).

4.3 Review and amendment of the code C + + and VHDL to support simultaneous sampling of the 8 ADCs

4.3.1 VHDL

Path between the ADC to the MAC

The ADC samples at 14bits, then after passing trough the Sip_FMC108 it becomes a 16bit value with the 2 least significant bits being 0, then is changed from big-endian to little-endian, 4 samples of each channel reach a FIFO and are then sent in frames of 64bits per channel.

Let's study in detail the hardware that interacts with the ADC's

The data buses that comes from the ADCs work at Low-voltage differential signaling at 2.5V, so for the 1 ADC chip we got 2 channels each channel with a differential bus, we got the channel A with cha_p and cha_n and the channel B with chb_p and chb_n, the same applies to the channel B. Both channels use the same clock as they are converted in the same ADC chip. Is identical to the other 4 ADC chips.

So each channel got a differential bus, in total 14 wires, and connects directly to the FPGA pins, in the FPGA that data passes trough the IBUFDS that converts the differential signal into a single-ended signal. That signal then passes trough the iodelay1, this io recourse from virtex6 permits creating programmable delays as small as 75ps (for the used clock in this project), this makes possible to correct many hardware problems, for example non-sync of the clock of the ADC that reaches the FPGA and the data bus. This data stream operates in DDR (Double data rate), so the data is transferred in both the rising and falling edges of the clock signal, in this case 7 bits of data is transmitted in the rising edge and the other 7 bits of the data sampling (in total 14bit resolution) are sent in the falling edge, we use the IDDR resource from the Virtex-6 to convert it to a regular data rate, where 14bits are available. This conversion is made with the clock of each ADC chip, so the first two channels use the clk_ab, the next two use the clk_cd, the next two the clk_ef and the last two channels use the clk_gh.

Then in a designer choose each sample is shifted 2 bits to the left and the 2 extra bits are padded to 0.

The cha_srd_se signal is then driven to a FIFO, this FIFO changes the clock domain, before the FIFO each 2 channels have their own clock, after the FIFO every channel shares the clk_ab first ADC clock. The write enable of this FIFO is at '0' at the reset and changes to '1' after 32 clock falling edges, this is a measure to avoid any transient state from the clock we will later explain why this is not enough, and why this solution does not work in all situations. The read enable of this FIFO is '0' after reset and '1' after all empty signals of all the 16bit FIFOs became '0', so reads become active when the 16fifos of all channels have been written this avoid a faulty read as each FIFO is written at different times.

This data is then transferred to the next FIFO this is a 16bit IN and 64bit OUT FIFO, the rd_clk of this 64bit FIFO is the system clock, the clocks is derived from the FPGA board that is a 200MHz oscillator with 50ppm, so this FIFO changes the clock domain and the data became completely independent from the ADC board and is ready to be sent by the Ethernet. The write clock of this FIFO is without much surprise the clk_ab as it was the read clock from the previously FIFO. The wr_en signal is only '1' when the software sends a trigger command, this is a bad solution because we still have one previous FIFO being written and this will create problems in the future and was fixed by us later. The same applies to the rd_en signal, is only '1' after the software trigger.

After this FIFO we got a interesting Router, this router can be software defined at any time to select one of the outputs of the eight 64bit FIFOs and send it to a bigger FIFO that is then read by the Ethernet block to send the data to the Ethernet port.

As discovered the reference design permits only to get 1 burst of the 8 ADC with no consistency over time, one channel at a time, without any phase relationship. We contact 4DSP and inquired if it was possible to trigger the 8 ADC at the same time and their response was the follows:

�Sure this is possible but not supported by the standard reference design unfortunately. Quite a few firmware/software modifications are to be expected. Typically the firmware buffering, data routing in the firmware and synchronization in the firmware needs to be changed and then the software should be modified to reflect firmware changes. The standard reference design offloads snapshots without any temporal coherence, one channel after the other, without any phase relation. � [4DSP_8ADCTRI].

So two firmware solutions were explored to enable simultaneous sampling and triggering of a fixed number of samples per channel:

1 - The first solution was more hardware based and it was to remove the Router 8-1 and instead have 8 FIFOs of 8Kb, consequently, it would bear with bursts of maximum size of 4096 samples, they then link to a state machine whose goal is filling the FIFO 64K, first with the values of the 1rst ADC, then with the 2nd ADC, and so on until the 8th ADC. Thus, few modifications of the software will be needed, just a ReadBlock() from where we get bursts from know sizes from the 8ADCs. The 8 FIFOs are trivial FIFOs, Xilinx IP Cores may be used, where the signal READ from the FIFO will connect directly to �chX_dval�. The state machine, expects to fill the FIFO64K when the 1rst FIFO8k is full, then wait for the 2nd and dump it and so forth.

2 - The second solution was simpler on the hardware side and more tricky on the software. The solution was to again remove the Router 8-1 and to connect the output of every channel directly to a modified FIFO 64K. The FIFO is altered to have 8x the previous size to still allow the same sampling size for each channel and the write enable is a 'and' of the writing_enable of the 8adc. The input is now of 8x16bit and the output is still 16bit. In the software side, the C++ code should be modified to receive the samples interleaved for each channel and not first all the samples from the 1rst channel then all from the 2nd and so on.

As any alteration in the VHDL code takes a long time to generate a bit-stream (usually 15min) the 2nd solution was chosen because the debuging was more software oriented, with faster compiling and better tools of debugging that Visual Studio offers.

So after implementation the data is send to the computer the following way:

4.3.2 C++

So focus now into the C++ program written by 4DSP. It does the following:

1 - The Ethernet communication driver is initialized and a reset command is sent to the FPGA to reset the firmware and all the chips in the FMC108 board;

2 - An request is made to the FPGA to know about the memory mapping of the various chips and the �starts� identification;

3 - A command is send to read by SPI the 2 ADT7411, that allows to know the temperature and state of the supply voltages in the circuit;

4 - Thermal limits are defined for a thermal auto-shut if needed;

5 - The clocktree is initialized, the values of the clock division are defined, the PPL is defined to work at 1250MHz , and the 4 clock outputs that will be used are enabled, also we choose if the clock is internal or external;

6 - The ADC is configured to work at high speed, with independent control and the output at complement 2 (parameters like offset correction and gain are not defined);

7 - It's defined the values of each data bus delay. The 8 ADC data-buses are independent and have different lengths when they reach the FPGA, so there's a need to compensate those delays. In this case a unique delay system of Virtex-6 is implemented for each channel, the max delay is of 32 and is started at 16. We can sent increments from software of max 32, above 16 +16 it comes back to 0. For 250MHz clock the delays are of (10, 10, 10, 10, 20, 25, 20, 25). We test other values, and changing them make some of the data input came wrong;

8 - We communicate with the �star� responsible for reading the frequency of each clock;

9 - The N of burst and burst size is configured;

10 - Enable the channel that will be read;

11 - Arm the ADCs;

12 - Software Trigger;

13 - Ethernet FIFO is read and allocated in the PC memory;

14 - The data is written in 8 different files, each one for each.

The code have 2 inputs, the first one to chose if the clock is internal or external(0- internal, 1- external), and other to select the Ethernet port that is used for communication.

Some alterations needed to be made to enable sampling the 8 channels at the same time. Before the step 10 we make a soft sync of the clock tree, this then guarantee that the output clocks are all in phase. In step 10, we enable the 8 channels and not only 1. Step 11 not only now arms all the ADC but also resets the input ADC FIFOs, this will avoid the problems that we were having with sample delays between channels.

Now, there used to be a function to write the data into the files (step 14), this function was erased, and a new one was created. It works the following way:

1 - Each sample come into 2 bytes, the first byte that comes is the least significant byte, and the second is the more significant byte. So a sample is the sum of the first byte with the second byte shifted by 8;

2 - The samples come as discussed before, 4 in 4, so the first 4 samples ( 8 bytes are from the 1rst channel), the next 4 samples are from the 2nd channel and so on;

3 - The function is run until the memory allocation length is archived.

This completes the modifications on the C++ file.

4.4 ENOB of the ADCs

We need to test and characterize the ADC that we got at our disposal in a way that will help us to evaluate the performance of the system. The ADC chip manufacturer details that the number of bits of the ADC that we are using in our project (ads62p49) details that the resolution of the ADC is 14bit. But the number of bits is never the exact resolution that we can get from the ADC, this is due to noise in each sampling that can be due to a variety of factors, it could be due to thermal noise, clock jitter, sub-ranging errors and others. To know the real performance of an ADC a normally used parameter for characterize it is the ENOB (Effective Number Of Bits). The manufacturer once again tell us that the ENOB at 170MHz is 11bits. But this information is not really useful, we only have 1 frequency that was tested, and in the real life we don�t have the ADC board that was used on the test, we got a 4DSP board that uses the same ADC but different components, layout and clock source. So it's important to study more in deep what's ENOB and how to measure it.

4.4.1 ENOB

The ENOB may be considered as the number of bits of a perfect ADC whose quantization noise error would be equal to the total error from all the sources in the ADC under test. The ENOB is calculated by using the relationship for the theoretical SNR of an ideal N-bit ADC: SNR = 6.02N + 1.76 dB. The equation is solved for N, and the value of SNR is substituted for SINAD:

ENOB=\frac{(SINAD-1.76dB)}{6.02}

If our signal does not archive the full rage of the ADC we can then change the equation to:

ENOB=\frac{(SINAD_{MEASURED}-1.76dB+20log(\frac{FullScaleAmplitude}{InputAmplitude}))}{6.02}

SINAD is the Signal-to-Noise-and-Distortion and is the relationship between the signal and amplitude and all others spectral components including noise and harmonics but not the DC component. This parameter is mostly important in audio, and is measured in a certain frequency by generating a tone and measuring the samples to get the wanted signal + noise + distortion. Then a notch filter is used to remove just the exact frequency of the tone generated and the result is measured again, in this case we got only the noise + distortion. The SINAD is then the relationship between both:

SINAD=\frac{Psignal+Pnoise+Pdistortion}{Pnoise+Pdistortion}

How to use then in our setup? We first wrote a simulation code that try to emulate the method used in audio.

1 - We generate a sinusoid at 170MHz and we sampled it at the sampling frequency of our ADCs, 250MSPS;

2 - Then we quantize the signal at N bits to simulate the quantization error of the ADC, as there is no other error in the simulation this will represent the effective number of bits, so we choose 11bit as the manufacturer says the ADC have;

3 - We then run a FFT of the data to get the spectrum of the signal and get rid of the first and last bin that have the DC component;

4 - We find the maximum bin number to know where we got the generated sinusoid;

5 - We determine the power spectrum of the data by squaring the spectrum;

6 - We define a span in bins for the input sinusoid, in that span all the majority of the sinusoid power should be contained (200);

7 - We estimate the noise+distortion floor power by making a mean of the power spectrum without the generated sinusoid span;

8 - In a duplicate of the power spectrum we replace the sinusoid span with the noise floor power;

9 - The signal power is then the sum of all the bins from the generated sinusoid span less the mean of the noise+distortion;

10 - The power of the noise+distortion is the sum of all the bins from the spectral power of the duplicate we modified;

11 - The SINAD is then SINAD = 10*log10(Ps/Pnd);

12 - The ENOB is ENOB = (SINAD-1.76+20*log10(2^(N-1)/(abs(max(data)))))/6.02 .

The result is the following:

The result is that we got a practical ENOB of 10.918bits when we should get 11bits. So it's a quite nice approximation of the ADC ENOB.

We later use the same algorithm in a frequency sweep in the practical and real system the results of the first ADC are the following (the other ADCs have similar results):

4.5 Measurements for analysis of the phase relationships of the 8 channels in order to support real-time DSP

4.5.1 Solve the problems to implement the least possible inter-channel phase

The first problem we have dealt with was that the phase relationship of some channels was near 100 samples more than the rest of the channels. After some review of the datasheets something appear to have a solution to the problem the clock tree AD9510 had a soft sync signal, that put all clocks in the same state and then let them oscillate again. After changing the C++ code to write by SPI to the AD9510, this seemed to solve the problem, and now we had only 10 samples of delay in some channels. But it still were not enough. After more debugging with ChipScope we find out that when we called the C++ program the first command that it would send was to make all the firmware reset as well for all the chips in FMC108 too. When the AD9510 was reset a transient state of the output clocks appeared, not all the clocks started at the same time and some start with a different frequency. As the first line of input FIFOs had the write_enable activated after 32 ADC clocks and each write clock is each ADC clock, some of the FIFOs were being written before the others, this created the delay. This is due that AD9510 does not start all the clocks at the same time. This information is not present on the datasheet of the clocktree.

The solution found was when the C++ program was called, it would make the reset, boot all the system and then when we �arm� the ADC a reset signal was sent only to the input FIFOs. This solved the problem.

There was still a delay in chX and Y, so we introduce a sample delay in those 2 channels. This sample delay was made to be easily changed in the VHDL code, as for different frequencies of ADC clock this delay may be different, this is caused by different paths in the board for each ADC clock input, at different frequencies we may have delays in different channels, this delay is never superior to 1 sample, because if the clock phase relationship between c

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