Field Effect Transistor Depletion And Enhancement

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There are two types of field effect transistor depletion and enhancement that are both available as N-type or P-type devices. Transistor sizing is a classic Computer-Aided Design problem that has received much attention in the literature. The inverter is the simple ways to explain the transistor sizing. “Several recent studies [5] have suggested that the inverter is truly like the nucleus of all digital designs. More intricate structures such as NAND gates, OR gates, XOR gates, full adder, multipliers, and microprocessors can be greatly simplified design once its operation and properties can clearly understood.” In these complex circuits, the electrical behaviour can be almost completely derived by generalizing the results obtained for inverters. The behaviour of more complex gates such as NAND, NOR, or XOR, which in turn form the building blocks for modules such as multipliers and processors can extended to explain the analysis of inverters.

In this chapter, focus on one single inverter gate, being the static CMOS inverter or in the short CMOS inverter. This is certainly the most popular at present, and therefore it can deserve special attention from people. The simplest thing a designer can do to minimize delay is to use minimum channel length for all FET's in the logic gate. This is always done when designing CMOS gates not just in inverter. “For example [6], finding a value for the transistor widths, W that minimizes delay is more difficult. Although the width does not affect the wire delay through the transistor itself but width does have an outcome on the on channel resistance and therefore also affects inverter delay. The inverter delay in simplified switching model is RC which would seem to involve that the delay can be reduced by increasing W to make R smaller.”

2.2 The static CMOS Inverter

A static CMOS inverter operation is like the simple switch model of the MOS transistor. The Figure 2.1 shows the circuit diagram of a static CMOS inverter. “The transistor is nothing more than a switch with an infinite off-resistance, and a finite on-resistance. This leads to the following interpretation of the inverter. The NMOS transistor is on when voltage input is high and equal to VDD, while the PMOS is off end of the line for my research [5].” In Figure 2(a), a direct path exists between voltage output and the ground node, resulting in a steady-state value of 0V. On the other hand, when the input voltage is low, NMOS and PMOS transistor are off and on. In Figure 2(b) is shows that a path exists between VDD and voltage output, yielding a high output voltage.

Other important properties of static CMOS can be derived from the switch-level view:

  • The results can say in high noise margins when the high and low output levels equal VDD and GND or the voltage swing is equal to the supply voltage.
  • The transistors can be minimum size because the logic levels are not dependent upon the relative device sizes which are called ratio less. Logic levels are determined by the relative dimensions of the composing transistors which are in contrast with ratio logic.

2.3 Estimating Width Dependence of Load Capacitance

By changing the capacitance value will changes the transistor widths. Assumed the interconnect resistances to be negligible and the capacitances have been lumped into a single node capacitance which includes parasitic capacitances from the transistors in the driver and transistors in the load as well as the wire connecting the gates together. “To divide the node capacitance into three component, Ci = Cout + Cwire + Cin, where Cout depends on the width of the driver transistors, Cin depends on the width of the load inverter transistors, and Cwire is negligible compared with the other two, it will be convenient the gates together [6].”

This observation suggests that getting CL as small as possible is crucial to the realization of high-performance CMOS circuits. It is hence worthwhile to first study the major components of the load capacitance before embarking onto an in-depth analysis of the propagation delay of the gate. In addition to this detailed analysis, the section also presents a summary of techniques that a designer might use to optimize the performance of the inverter.

2.4 Voltage transfer characteristic (VTC)

“The nature and the form of the voltage-transfer characteristic (VTC) are graphically deduced by superimposing the current characteristics of the NMOS and the PMOS devices [5].” The voltage transfer characteristic of the inverter exhibits a very narrow transition zone. During the switching transient, this result is from the high gain when both NMOS and PMOS are simultaneously on and in saturation. In operation region, a small change in the input voltage results in a large output variation. All these observations translate into the VTC of Figure 2.3. Before going into the analytical details of the operation of the CMOS inverter, a qualitative analysis of the transient behavior of the gate is appropriate as well.

2.4.1 Threshold and transfer characteristics

“Figure 2.3 shows the transfer characteristics for three different values for βnp. As βnp is reduced the threshold voltage creeps up in value so that a larger input voltage is required to make the output fall [7].”

“Figure 2.4 shows the effect of increasing threshold voltage on timing. The figure depicts the output transition as a function of time for three differently T-sized inverters. The timing measurements are all made at the intercept of the output traces with the optimum gate threshold voltage for a design library in which βn/βp = 1 [7].”

2.5 NMOS/PMOS Ratio

Calculate the ratio βnp

From the equation below, for

NMOS, βn= μnεoxtox(WnLn) (2.1)

PMOS, βp= μpεoxtox(WpLp) (2.2)

The Ln=Lp, then βnβp=μnμpWnwp (2.3)

Typically µn= 1200 cm2/Vs and µp= 450 cm2/Vs for silicon so µn/µp ≈ 2.7

This trick of making the PMOSFET larger to compensate for the lower holes mobility is universally used in silicon design. However, making the PMOSFETs 2.7 times larger than the NMOSFETs leads to large circuits that occupy large areas of silicon for little extra benefit [7].”

The motivation behind this approach is to create an inverter with a symmetrical VTC, and to equate the high-to-low and low-to-high propagation delays. However, this does not imply that this ratio also yields the minimum overall propagation delay. The reasoning behind this statement is that, while widening the PMOS improves the tpLH of the inverter by increasing the charging current, it also degrades the tpHL by cause of a larger parasitic capacitance.

From this analysis can conclude that variation in transistor size not only affects the performance of single gates, but that it also affects the relationship between gates. The picture only becomes more complicated when consider the gates that have more transistors than an inverter and some care is taken in T-sizing all gates to ensure that they have the same switching characteristics. If this is not done, timing prediction becomes impossible hence synthesis and digital design automation is not feasible.

2.6.1 Operation region

A transistor in a circuit will be in one of three conditions

  • Cut-off Region - In this region the gate voltage is less than the pinch-off voltage Vp and therefore very few current flows through.
  • Triode Region/Linear Region - In this mode the devices is operating below pinch-off and is effectively a variable resistor. ROUT is linear but only over a small range of VDS.
  • Saturation Region - This is the main operating region for the device. The drain voltage has to be greater than the gate voltage less the pinch-off voltage. The curves in the saturation region can be extrapolated to a point 1/λ, where λ is known as the ‘channel length modulation parameter'

2.7 Performance of CMOS inverter

2.7.1 The Dynamic behavior

“The theory was first put forward in [5] the qualitative analysis presented earlier concluded that the propagation of the CMOS inverter is determined by the time it takes to charge and discharge the load capacitor CL through the PMOS and NMOS transistors.” Be sure that to get the CL as small as possible is crucial to the realization of high-performance CMOS circuits. Before embarking onto an in detail analysis of the propagation delay of the gate, it is useful to study the main components of the load capacitance. Furthermore to this detailed analysis, the section also presents a summary of techniques that might use to optimize the performance of the inverter.

2.7.2CMOS inverter propagation delay

“Several recent studies [8] have suggested that the dynamic of performance of a logic-circuit family is characterized by the propagation delay of its basic inverter. The inverter propagation delay (tp) is defined as the average of the low-to-high (tPLH) and the high-to-low (tPHL) propagation delays:

tP=tPLH+tPHL2 (2.4)

Propagation delays tPLH and tPHL are defined as the times required for output voltage to reach the middle between the low and high logic level. Figure below illustrates the definition of the propagation delays.”

The propagation delay of the CMOS inverter that is loaded only with its own output capacitance COUT is called intrinsic delay:

tPo=tPLH+tPHL2 (2.5)

In the simplified analysis the NMOS and PMOS transistors can be replaced by equivalent resistance RN and RP when charging and discharging the COUT resulting into:

tPLH≈0.69.RP.COUT (2.6)

tPHL≈0.69.RN.COUT (2.7)

This it is assumed that PMOS acts as a RN when COUT is charged to VDD when output is switched from low-to-high and NMOS acts as RN when COUT is discharged when output is switched from high-to-low.

Propagation delay of the loaded inverter can be expressed through intrinsic delay:

tP=tPo.(CIN+CwCOUT) (2.8)

The values of the equivalent resistance and even CL can depend on VDD thus the propagation delay is affected by power supply voltage (being smaller for higher VDD). It should be noted, however, that this dependence of the propagation delay on power supply voltage is less pronounced in MOSFETs with short channels where drain current saturation is achieved due to velocity saturation rather than due to channel pinch-off at drain.


“Gates of the critical paths were downsized where possible. As the example, Figure 2.7 shows the details of the effect of sizing on the path-delay distribution, while also for Figure 2.8 shows the normalized active energy and leakage power for the sized design against the baseline design. In essence, most gates off the critical path are minimum size [9].”

Several people use mathematical optimization techniques to solve the transistor sizing problem. In this approach, the problem is formulated as a constrained nonlinear mathematical program and a timing analyzer or a circuit simulator SI is used to evaluate the delay constraints. The advantages of this approach are:

  1. It can optimize random objective (cost) functions such as power consumption or total chip area;
  2. It can produce better results through interfacing to timing analyzers or circuit simulators with more accurate delay models
  3. It can start from arbitrary transistor sizes, if robust algorithms such as the feasible directions method are used. “The transistor sizes using Mathematical Optimization approach to categorize into gate-level sizes and transistor-level sizes.
    1. Gate-level sizes associate with each logic gate a scale factor that is treated as a design parameter in the optimization algorithm; all transistor sizes within the gate scale up or down in proportion to that factor.
    2. In contrast, transistor-level sizes treat the size of each transistor as a design parameter. In general, gate-level sizes work faster than transistor-level sizes because of the smaller number of design parameters. However, since it is necessary for optimum design to size a transistor according to its position within a gate, a transistor-level size is needed for high-performance designs [10].”

Transistor widths are adjusted once more to the nearest grid positions after the algorithmic optimization stage. The user can specify upper and lower limits for the transistor widths. Area optimization is better suited for a specific delay requirement than pure delay or power optimization. “There will have large changes in the transistor sizes when pure delay optimization leaded. A large transistor may not make as many transistors as a small transistor, which frequently changes state and renders any power optimization ineffective [11].”

2.9 Power, Energy, and Energy-Delay

Static CMOS is the almost complete deficiency of power consumption in steady-state operation mode. It is this combination of strength and low static power that has made static CMOS the technology of choice of most existing digital designs. The power dissipation of a CMOS circuit is instead dominated by the dynamic dissipation resulting from charging and discharging capacitances.

2.9.1 Dynamic Power Consumption

Dynamic Dissipation due to charging and Discharging Capacitances

“As power dissipation becomes an increasingly important issue, accurate power estimation models are needed. A fast and efficient way of estimating power are produced a development of probabilistic techniques which is proportional to the average switching probability of a node [12].” The power dissipation of a gate is approximated by the change in energy for charging and discharging the output capacitance of the gate. Since a gate does not necessarily switch at every clock cycle, the frequency of switching is estimated by the clock frequency multiplied by the expected number of switches per cycle. Since gate capacitance is proportional to transistor width, the statistical method of power estimation provides a simple way of examining power dissipation in term of sizing.

“At the several studied [5] when the capacitance CL was charged each time through the PMOS transistor, its voltage rises from 0 to VDD and a certain amount of energy is drawn from the power supply.” Part of this energy is dissipation in the PMOS device, while the remainder is stored on the load capacitor. This capacitor is discharged and the stored energy is dissipated in the NMOS transistor during the high-to-low transition.

2.9.1 The rise/fall time of the input signal

All the expressions were derived under the assumption that the input signal to the inverter suddenly changed from 0 to VDD or vice-versa. Only one of the devices is assumed to be on during the discharging process. In reality, PMOS and NMOS transistors conduct simultaneously and the input signal changes slowly and momentarily. This affects the total current available for discharging and impacts the propagation delay.

While it is possible to derive an analytical expression telling the relationship in between input signal slope and propagation delay, the result tends to be complex and of limited value. From a design perspective, the limited driving capability of the preceding gate which is it more precious to relate the impact of the finite slope on the performance straight to its cause. If the latter would be considerably strong, its output slope would be zero and the performance of the gate under theory test would be impassive. The major advantage of this approach is that it realizes that a gate is never designed in isolation, and that its performance is both affected by the fan-out, and the driving strength of the gates feeding into its inputs. This leads to a revised expression for the propagation delay of an inverter in a chain of inverters.