Addressing Modes In The Central Processing Unit English Language Essay

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Design of Central Processing unit is designed, Addressing modes is one of the most crucial aspects. The addressing modes defines how machine language instructions in that architecture identify the operands of each instruction. It specifies how to the effective memory address of an operand is calculated.

In computer programming, addressing modes are primarily of interest to compiler writers. Different computer architectures vary greatly as to the number of addressing modes they provide in hardware. The different addressing modes of 8086 microprocessor are

Register Addressing

This mode transfers a byte or word from source register or memory location to the destination register or memory location. In this mode the source register does not change, but the destination does.

Example:-

MOV AX,BX Copies the word from register BX to AX

Immediate Addressing

This mode shows that the actual operand is stored in the address field of the instruction. Generally, immediate operands represent constant data. Since no memory access is needed, it is called immediate addressing.

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MOV AX,22H Moves 22 hexadecimal into AX

Direct Data Addressing:

This mode is different from the immediate addressing in that the location following the instruction opcode hold an effective memory address (EA) instead of data. This effective address is the 16-bit offset of the storage location of the operand from the current value in the DS register.

Example:-

MOV BX,FFFF Moves the contents at memory location FFFFH into BX

Register Indirect Addressing Mode

This mode is similar to the direct addressing in that an effective address effective address resides in either a pointer register or an index register.

The direct addressing method lends itself to applications where the value of Effective Address is a constant. The register indirect addressing can be used when the value of Effective address is calculated and stored. That is, it is a variable.

Example:- MOV AX,[SI]

Moves the contents of the memory location offset by the value of effective address in SI from the beginning of the current data segment to the AX register

Based Addressing Mode

The PA of the operand is obtained by adding a direct or indirect displacement to the contents of either base register BX or base pointer BP and the current value in DS or SS respectively.

Example MOV [BX]+BETA, AL

This instruction uses base register BX and direct displacement BETA to derive the EA of the destination operand. The based addressing mode is implemented by specifying the base register in brackets followed by a + sign and the direct displacement. The source operand in this example is located in byte accumulator AL.

Index Addressing Mode

This mode works identically to the based addressing, however it uses the contents of one of the index registers, instead of BX or BP, in the generation of the physical address.

Example: MOV AL,[SI]+ARRAY

Based Indexed Addressing Mode

This mode, combining the based addressing mode and the indexed addressing mode together, results in a new, more powerful mode. This type of addressing uses one base register (BP or BX) and one index register (DI or SI) to indirectly address memory.

Example: MOV DX,[BX+DI]

This instruction transfers a copy of word from location [BX+DI] into the register DX

Register Relative Addressing

This mode of addressing is similar to base-plus-index addressing. The data in a segment of memory are addressed by adding the displacement to the content of a base or an index register.

Example:-

MOV AX[DI+100H] The word content of the data segment memory location addresses by DI plus 100H is copied into register AX.

Base Relative-Plus-Index Addressing

The base relative plus index addressing is similar to the base-plus-index adressing mode, but adds a displacement besides using a base register and an index register to form the memory address. In, other words this mode addresses a two dimensional array of memory address.

Example: MOV DH,[BX+DI+20H]

DH is loaded with the data present in the address given by [BX+DI+20H]

String Addressing

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This is specific mode of addressing when string related instructions are being used. This mode uses index registers. SI register is used to point the first byte or word of the source string and the DI is used to point the corresponding first word of destination string.

Operations Satisfied:

This sections aims at exploring various operations supported by the 8086 microprocessor. These operations are broadly classified into 3__ categories

Data Transfer Operations:

Data transfer operation is one of the most common operation within any subroutine of a program. A set of Data transfer instructions are defined which move single bytes, words and double words between memory and registers AL or AX and Input/output ports.

These data transfer instructions are broadly segregated as

1 General Purpose Data Transfers :

MOV destination, source This instruction transfers a byte or word from the source operand to the destination operand.

PUSH source PUSH instruction decreases the stack pointer by two and transfer a word from the source operand to the top of the stack.

POP destination It transfers the word at the current top of stack to the destination operand and increases stack pointer by two.

XCHG translate-table It switches the contents of the source and destination operands

XLAT It replaces a byte in the AL register with a byte from a 256-byte, user coded translation table. It is generally useful for translating characters from one code to another.

Input/Output

IN accumulator,port It transfers a byte or word from an input port t the AL register or the AX register respectively. The port is either specified or obtained from DX register

OUT port,accumulator It transfers a byte or a word from the AL register to an output port.

Address Object Transfers

These are instructions generally used to the address of variables rather than the contents and are useful for list processing an string operations. The instructions used for this are

LEA destination, source Load Effective Address transfers the offset of the source operand to the destination operand. The source operand needs to be a memory operand and the destination operand must be a 16-bit general register.

LDS destination, source Load pointer using DS, transfers a 32-bit pointer variable from the source operand to the destination register and register DS. The offset word of pointer is transferred to destination operand and segment word of the pointer to the register DS.

LES destination, source Load pointer using ES, transfers a 32-bit pointer variable from the source operand to the destination operand and register ES

Flag Transfers

LAHF Load Register AH from flags copies SF,ZF,AF,PF and CF into bits 7,6,4,2 and 0 respectively, of register AH. The flags are not affected in the transfer

SAHF Store Register AH into flags transfers bits 7,6,4,2 and 0 from register AH into SF,ZF,AF,PF and CF respectively, replacing the previous flags

PUSHF It decreases the SP by two and then transfers all flags into the word at the top of the stack pointed by it.

POPF It transfers specific bits from the word at the current top of stack into flags replacing the previous flags. PUSHF and POPF allow a procedure to save and restore a calling program's flags..

Arithmetic Instructions

Arithmetic Operations involve mathematical manipulations on data. These manipulations can be made on four types of numbers namely unsigned binary, signed binary, unsigned packed decimal and unsigned unpacked decimal. Arithmetic instructions post certain characteristics of the result of the operation to six flags namely Carry Flag, Auxiliary Flag, Sign Flag, Zero Flag, Parity Flag, Overflow flag.

Various mathematical operations that can be performed are:

ADDITION

ADD destination, source

The sum of two operands, which may be bytes or words, replaces the destination operand. Both operands may be signed or unsigned binary numbers. All the flags are appropriately updated.

ADC destination, source

Add with carry sums the operands, which may be bytes or words, and adds 1 if Carry flag is set, and replaces the destination operand with result. Since the carry is taken care of, numbers longer than 16 bit also can be added using routines.

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INC destination

INC adds one to the destination operand . All the flags except the Carry flag are appropriately changed.

AAA

ASCII adjust for addition manipulates the contents of register AL into a valid unpacked decimal number. The higher order half-byte is zeroed. AAA updates AF and CF. Rest of the flags are undefined.

DAA

Decimal adjust for addition corrects the result of previously adding two valid packed decimal operands. It changes the contents of AL to a pair of valid packed decimal digits.

SUBTRACTION

SUB destination, source

The difference of two operands, which may be bytes or words, replaces the destination operand. Both operands may be signed or unsigned binary numbers. All the flags are appropriately updated.

SBB destination, source

It subtracts the source from the destination and subtracts 1 if Carry flag is set, and replaces the destination operand with result. Since it incorporates a borrow from previous operation, it can be used to subtract numbers longer than 16 bit also.

DEC destination

DEC subtracts one from the destination operand . the operands may be signed or unsigned binary numbers. All the flags are appropriately changed except the Carry flag.

NEG destination

This instruction negates the result to the destination. This forms the 2's compliment of the number, effectively reversing the sign of the integer. All flags are updated except the carry flag, which is always set except when the operand is zero where it is cleared.

CMP source

Compare subtracts the source from the destination but does not return a result. the operands are unchanged but the flags are updated and can be tested using a conditional jump function. The comparison reflected in the flags is that of the destination to the source.

AAS

ASCII adjust for subtraction corrects the result of previous subtraction of two valid unpacked decimal operands. The higher order half-byte is zeroed. AAS updates AF and CF. Rest of the flags are undefined.

DAS

Decimal adjust for subtraction corrects the result of previously adding two valid packed decimal operands. It changes the contents of AL to a pair of valid packed decimal digits and updates all the flags except the OF which is undefined.

MULTIPLICATION

MUL source

It performs an unsigned multiplication of the source operand and the accumulator. If the source is a byte it is multiplied by AL register and the double length is returned in AH and AL. If the source operand is a word, then it multiplied by register AX and the double length is returned to DX and AX. When CF and OF are set they indicate that AH and DX contains significant digits of results. Rest of the flags are undefined

IMUL source

Integer multiply performs a signed multiplication of the source and the accumulator. It performs similar operation of MUL. The CF and OF are set if the upper half of result is not the sign extension of the lower half of result.

AAM

ASCII adjust for multiplication of previous multiplication of two valid unpacked decimal operands. The higher-order half-bytes of the multiplied operands must have been 0H for AAM to produce a correct result.

DIVISION

DIV source

divide performs an unsigned division of the accumulator by the source operand. If the source is a byte it is divided into the double-length dividend assumed to be in register AH and AL. If the source operand is a word, then it divided into the double length dividend in DX and AX. If the quotient exceeds the capacity of register a type 0 interrupt is generated. Non-integer quotients are truncated to integers and the remainder has same sig as dividend.

IDIV source

Integer division performs a signed division of the accumulator by the source operand.. It performs similar operation of DIV. The content of all flags are undefined.

AAD

ASCII adjust for Division modifies the numerator in the AL before dividing two valid unpacked decimal operands so that the quotient is also a valid unpacked decimal number. The higher-order half-bytes of the multiplied operands must have been 0H for AAM to produce a correct result. AH must be zero for subsequent DIV to produce the correct result.

CBW

Convert byte to word extends the sign of the byte in register AL throughout register AH. CBW does not affect any flags. CBW can be used to produce a double length dividend from a byte prior to performing byte division.

CWD

Convert word to double-word extends the sign of the word in register AX throughout register DX. CWD does not affect any flags.

Bit Manipulation Instructions

Three groups of instructions are available for manipulating bits within both bytes and words

LOGICAL

The logical instructions include the Boolean operators. The flags are appropriately affected by the instructions. The OF and CF are always cleared by logical instructions, and the contents of AF is always undefined following execution of logical operation.

The SF, ZF, and PF are always posted to reflect the result of the operation and can be tested by conditional jump instruction. The interpretations are same as arithmetic instructions.

NOT destination

It inverts the bits using the one's complement of the byte or word operand. It has no effect on the flags

AND destination, source

It performs the logical AND of the two operands and returns the result to the destination operand. A bit in the result is set if both corresponding bits of the original operands are set.

OR destination, source

It performs the logical inclusive OR of the two operands and returns the result to the destination operand. A bit in the result is set if either or both corresponding bits of the original operands are set.

XOR destination, source

It performs the logical exclusive OR of the two operands and returns the result to the destination operand. A bit in the result is set if the corresponding bits of hee original operands contain opposite values.

TEST destination, source

It performs the logical "and" of the two operands, updates the flags, but does not return the result. A JNZ is generally used to check if there are any ones is either operands.

SHIFTS

The bits in bytes and words may be shifted arithmetically or logically. Arithmetic shifts may be used to multiply and divide binary numbers by powers of two. they are also used to isolate bits in bytes and words

AF is always undefined following a shift operation. CF always has the value of the last bit shifted out of the destination operand. The contents of OF is always undefined following a multi-bit shift. In a single-bit shift OF is set if the high-order bit was changed by the operation.

SHL/SAL destination, count

Shift logical left/ Shift arithmetic left perform a bit shift to left by the number of times specified in the count operand. Zeros are shifted in on the right. If the sign bit retains its original value, then OF is cleared.

SHR destination, source

Shift local right shifts the bits in the destination operand to right by the number of bits specified in the count operand. zeros are shifted in on the left. If the sign bit retains its original value, then OF is cleared.

SAR destination, count

Shift arithmetic right shifts the bits in the destination operand to right by the number of bits specified in the count operand. Bits equal to the original high order bit are shifted in on the left, preserving the sign of the original value/

ROTATES

Bits in bytes and words can be rotated. bit rotated out of an operand are not lost as in a shift but are circled back into the other end of the operand. As in the shift instructions, the number of bits to be rotated is taken from the count operand, which may specify either a constant 1, or the CL register.

Rotates affect only the carry and overflow flags. CF always contains the value of the last bit rotated out.

ROL destination, count

Rotate left rotates the destination byte or word by the number of bits specified in the count operand.

ROR destination, count

"Rotate right" operates similar to ROL except that the bits in the destination byte or word by the number of bits specified in the count operand to the right.

RCL destination, count

Rotate through carry left rotates the bits in the byte or word destination operand to the left by the number of bits specified in the count operand. The CF is treated as 'part-of' the destination operand.

RCR destination, count

Rotate through carry right operates exactly like RCL except that the bits were rotated right instead of left.