# Vedic Multiplier For DSP Applications Engineering Essay

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Vedic Mathematics is widely in use today, for performing computations in the areas of Digital Signal Processing, and Embedded Systems mainly because of its ability to perform fast. This paper is dedicated to the design of Vedic Multiplier. The Vedic multiplier is designed using Urdhva Tiryakbhyam Algorithm, as it is found to operate with a minimum delay. Alongwith, operating with minimum delay, it is also found to be consuming less area. This work mainly evaluates the speed and area used by a Vedic Multiplier, when compared to the other multipliers, such as Array's and Booth's multipliers. The proposed Vedic Multiplier is synthesised using Altera's QuartusII 9.1 sp2-Web edition.

Keywords: Urdhva Tiryakbhyam Algorithm, partial products, high speed, area and power consumption..

## I. INTRODUCTION:

Arithmetic is one of the oldest branches in Mathematics[1]. It is also widely used by everyone in their day to day life applications, such as, in counting machines, scientific calculations, etc. As the demand, for faster computation is increasing day by day, there is a necessity to use mathematical methods, which can solve such computations in lesser time. The work presented in this paper, uses Vedic Mathematics, in which a Vedic Multiplier is designed to perform fast computations. A trade-off is achieved in terms of total time taken, overall area consumed and the total power consumed[5].

The four basic Arithmetic operations are-Addition, Subtraction, Multiplication, and Division.The need for fast multiplication arises very much in applications pertaining to Digital Signal Processing and also in Microprocessors. Hence, Vedic Mathematics based Multiplication Algorithms are being used to solve multiplications faster. His Holiness Jagadguru Shankaracharya Bharthi Teerthaji Maharaja(1884-1960) constructed 16 sutras[2]. These sutras are mainly used in Arithmetic, Trigonometry, Plain and solid geometry. Section II deals with the designing of the 2x2 Vedic Multiplier. Section III presents the designing of the 4x4 multiply block. Section IV deals with the designing of the 8x8 multiply block. The analysis,and the results is presented in Section V.The conclusion presented in Section VI. Finally, the work is concluded in Section VII.

The work uses Urdhva Triyagbhyam Algorithm,a sutra brought by His Holiness Jagadguru Shankaracharya Bharathi Teerthaji Maharaja for multiplying two 8-bit numbers. Urdhva Triyaghbhyam means-vertically and crosswise. In this type of multiplication, partial products are generated concurrently. Hence, the multiplication process is much faster when compared to the other multiplication methods. Coming to the area, as the partial products are generated concurrently, parallel processors can be laid, thereby reducing the overall area of consumption [5].

Illustrating the multiplication process of two numbers by starting, with multiplying two,2 digit numbers,12 and 12 in decimal form, using step by step procedure.

i) The units digit of each of the two numbers are multiplied, to give the Least significant bit(LSB) in the result.In this case, it is (2*2=4).

ii) The next upper bit is, obtained in the result as,[(MSB of the first number*LSB of the second number)+(MSB of the second number*LSB of the first number(as written in the order))].In this case it is given as, ((1*2)+(1*2)=4).

iii) The most significant bit(MSB) is,obtained in the result as, the MSB of both the numbers are multiplied. In this case,it is (1*1=1). The Fig(1) shows the way the multiplication process is carried out between two decimal numbers.

i) 1 2 ii) 1 2 iii) 1 2

X1 2 X 1 2 X 1 2

4 4 4 144

( Fig. (1) The figure shows the multiplication process using Urdhva Triyagbhyam method for two digit numbers in the decimal form)

## II. DESIGN OF 2X2 VEDIC MULTIPLIER:

The design of 8x8 bit Vedic Multiplier can be achieved by breaking the two,8-bit binary numbers into chunks of 2x2 multiplier blocks and 4x4 multiplier blocks [4]. This procedure is followed and the resultant bits are fed into the addition tree.

## Realization of 2x2 Multiplier Block:

The logical expression is derived for a 2x2 Multiplier Block. The multiplier block multiplies two-bit binary numbers and performs the multiplication using Urdhva Triyagbhyam Algorithm. Considering two numbers, 'a' and 'b', each of bit length,2, where a[0], b[0], represent the least significant bits(LSB) of 'a' and 'b' respectively. a[1] and b[1] represent the most significant bits(MSB). The output data is a 3-bit data,where, y[0] forms the least significant bit, y[1] forms the middle digit, and y[2] forms the most significant bit(MSB).The logical expressions with the logical diagram is given in the Fig.(2).

Logical expressions:

y[0]=(a[0].b[0]),

y[1]=(a[0].b[1])+(a[1].b[0]),and

y[2]=(a[1].b[1])

a[0] y[0]

b[0]

a[1]

b[0]

a[0] y[1]

b[1]

a[1] y[2]

b[1]

## III. DESIGN OF 4X4 VEDIC MULTIPLIER:

The 4x4 bit multiplier is constructed using four 2x2 bit multiplier blocks. The four bit input data is broken down into chunks of 2x2 bit input data, and the multiplication is performed in the similar way, as it is performed for 2x2 bit multiplier blocks. The procedure of how the 4x4 bit multiplier works, is illustrated with an example as shown in Fig(3). This gives the order in which the multiplication is performed. The schematic of the block diagram is given in fig(4). The final result obtained is of maximum bit length of eight.

Considering 2 inputs-a and b, which are 4 bits each, where a=1011, and b=1000.

i)1 0 1 1 ii) 1 0 1 1 iii) 1 0 1 1 iv) 1 0 1 1

x x x x

1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0

(Fig(3)- An illustration of how 4x4 bit multiplication is performed)

## Schematic of a 4x4 Multiplier Block:

b[3:2] a[3:2] b[3:2] a[1:0] b[1:0] a[3:2] b[1:0] a[1:0]

2x2 multiply block

2x2 multiply block

2x2 multiply block

2x2multiply block

D3{[3:0],0,0} D2{0,0,[3:0]} D1[3:0] D0[3:0]

{0,0,[3:2]} [1:0]

adder

adder

adder

Q[7:2] Q[1:0]

(Fig (4)-Block diagram of a 4x4 multiplier block)

## Addition Tree:

The partial products that are formed are fed into the addition tree. The lower 2 bits of the partial products formed are given as the least two bits to the result,i.e. in this case,D0[1:0], is passed to directly to the final result.The rest of the bits in the result are formed from the addition tree, as explained in the Fig(4).

## \

Inputs to the adder tree

D3 X X X X

D2 X X X X

D1 X X X X

D0 X X X X Lower two bits are passed directly to the result

X X X X X X X X

(Fig (4)-Addition of the partial products obtained in a 4x4 multiply block)

## IV.DESIGN OF 8X8 MULTIPLY BLOCK:

The 8x8 multiplier is formed using four 4x4 multiplier blocks. The 8 bit input data is broken down into chunks of 4x4 bit input data, and the multiplication is performed in the similar way, as it is performed for 4x4 bit multiplier blocks. The procedure of how 8x8 bit multiplier works,is illustrated with an example,shown in fig(5). The schematic of an 8x8 multiplier block is as shown in fig(6). This gives the order in which the multiplication is performed [4].Considering 2 inputs a and b,which are 8 bits each, where a=10000000,b=111110000.

i) 1 0 0 0 0 0 0 0 ii) 1 0 0 0 0 0 0 0

x 1 1 1 1 1 0 0 0 x 1 1 1 1 0 0 0 0

iii) 1 0 0 0 0 0 0 0 iv) 1 0 0 0 0 0 0 0

x 1 1 1 1 1 0 0 0 x 1 1 1 1 0 0 0 0

(Fig (5)-Illiustration of multiplication of two 8-bit numbers)

## Schematic of an 8x8 Multiplier Block:

b[7:4] a[7:4] b[7:4] a[3:0] b[3:0] a[7:4] b[3:0] a[3:0]

4x4 multiply block

4x4 multiply block

4x4 multiply block

4x4 multiply block

Q4[7:0],0000 {0000,Q3[7:0]} Q2[7:0] Q1[7:0]

{0000,[7:4]} [3:0]

adder

adder

adder

Y[15:4] Y[3:0]

(Fig(6)- Block diagram of 8x8 multiply block)

## Addition Tree:

The partial products that are formed are fed into the addition tree. The lower 4 bits of the partial products formed, are given as the least four bits to the result,ie Q1[3:0] are passed directly to the result. The rest of the bits in the result are formed from the addition tree, as explained in the Fig(7).

Q4 X X X X X X X X Inputs to the addition tree

Q3 X X X X X X X X

Q2 X X X X X X X X

Q1 X X X X X X X X Four bits directly passed to the result

X X X X X X X X X X X X X X X X

(Fig(7)- Addition of partial products in an 8x8 multiply block)

## V. RESULTS:

Simulation waveform of Vedic Multiplier:

(Fig(8)- shows the simulated waveform of the 8x8 bit Vedic Multiplier)

## VI.CONCLUSION:

DELAY OBTAINED:

## Array

## Multiplier

## Booth

## Multiplier

## Vedic Multiplier(Urdhva Tiryakbhyam Sutra)

39 ns

42 ns

17.475 ns

(Fig (9)- Table comparing the delays of different multipliers)

From Fig(9), it can be inferred that the delay achieved for Urdhva Multiplier is much lesser than

Array and Booth multipliers. Hence, in this way,a faster multiplication is achieved.

Thus,the Vedic Multiplier is time-efficient.

2)TOTAL AREA CONSUMED:

Total number of logic elements: 62.

The number of components used in this design is very less when compared to other multipliers(<1%).

Thus,Vedic Multiplier is area-efficient.

3)TOTAL POWER DISSIPATED:

Total power dissipated:70.46mW.

The power dissipated in the Vedic Multiplier is minimal.

## VII. REFERENCES:

[1] www.wikipedia.org

[2] Jagadguru Swami Sri Bharati Krishna Tirthji Maharaja, "Vedic Mathematics", Motilal

Banarasidas, Varanasi, India, 1986.

[3] Himanshu Thapliyal and M.B.Srinivas, "An efficient method of elliptic curve encryption using

Ancient Indian Vedic Mathematics", IEEE, 2005.

[4] Abhijeet Kumar, Dileep Kumar, Siddhi, "Hardware implementation of 16*16 bit Multiplier and

square using Vedic Mathematics", Design Engineer, CDAC, Mohali.

[5] Amandeep Singh, "Design and Hardware realization of 16 bit Vedic Arithmetic unit".

[6] Ramachandran S, Kirthi S. Pande,"Design,Implementation and performance analysis of an

integrated Vedic Multiplier Architecture",ISSN : 2250-3005

[7]B. Balatripurasundari and T.Padmanabhan," Design through Verilog HDL",IEEE press, A John

Wiley and Sons, Inc,Publication.