The Unified Power Flow Controller Engineering Essay

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A recent technological development in electrical power systems is the Flexible alternating -current transmission systems (FACTS It is built on the advances achieved in various technologies such as high-current semiconductor device digital control and signals conditioning. The commissioning and operation of high voltage direct current (HVDC) like a static VAR compensator (SVC) systems have provided the thrust to explore more into the benefits of upcoming power electronic equipment and techniques in order to counter long standing operational problems in both high voltage transmission and low voltage distribution systems. [1]

Phase-shifting and tap-changing transformers branch of the power electronic constituted the new progress in the FACTS technology. Together with the electronic series compensator, they constituted the first generation of FACTS equipment. The recent advancements include the unified power flow controller, the static compensator, and the interphase power controller. When compared to the first generation controllers, they provide precise control capabilities and perform more accurate functions. They constitute the second generation of FACTS equipment. The operating conditions of Shunt-connected thyristor-switched capacitors and thyristor-controlled reactors, as well as high-voltage direct-current (DC) power converters, are similar to those of FACTS controllers in spite of being in use for a long period of time. [2]

Configurations of a number of FACTS controllers have taken place. Steady state and transient operation working are the important function implemented by these controllers but to achieve transient operation working is the main function of some of the controllers.

FACTS controllers intended for steady state operations are as follows:

Thyristor-controlled phase shift (PS): It provides a rapidly varying phase shift angle and is an electronic phase-shifting transformer adjusted by thyristor switches.

Load tap changer (LTC): if the tap changes are controlled by thyristor switches it may be considered to be a FACTS controller

Thyristor controlled reactor (TCR): partial conduction control of the thyristor valve varies the effective reactance of this shunt-connected, thyristor-controlled reactor.

Thyristor-controlled series capacitor (TCSC): smooth variable series compensation is achieved by a series capacitor placed in parallel with a thyristor controlled reactor.

Interphase power controller (IPC): it is subjected to separate phase shift voltage magnitudes provided by a series connected controller consisting of two parallel branches of an inductor and a capacitor. The two phase-shifting sources and the two variable reactances is used for active power control which is not dependent on reactive power control.

Static compensator (STATCOM): connected in shunt with the AC system is this solid-state synchronous condenser. The nodal voltage magnitude or the reactive power injected at the bus is controlled by varying the output current.

Solid state series controller (SSSC): connected in series with the AC system is this controller which is identical to the STATCOM. The nodal voltage magnitude or the reactive power injected at the bus is controlled by varying the output current.

Unified power flow controller (UPFC): this consists of a static synchronous series compensator (SSSC) and a STATCOM, connected in such a way that they share a common DC capacitor. The UPFC, by means of an angularly unconstrained series voltage injection, voltage magnitude, and the active and reactive power through it. It may also provide independently controllable shunt reactive compensation. [3]

1.2 Benefits from Facts Technology

Control of power flow over the TX routes

Reduces loop flows

Reduces reactive power flows, thus allowing the lines to carry more active power

Increases the loading capability of lines to their thermal capabilities

Increases the TX capability of AC line

Control of power flow as ordered

CHAPTER 2

UNIFIED POWER FLOW CONTROLLER

2.1 Introduction

Fast-acting reactive power compensation on high-voltage electricity transmission networks is provided by an electrical device called the Unified Power Flow Controller (or UPFC). Active and reactive power flows in a transmission line are controlled by this diverse controller. It provides functional flexibility, generally not attainable by conventional thyristor controlled systems and with the use of solid state controllers it is possible to handle all power flow control and transmission line compensation problems. The UPFC is a combination of a static synchronous compensator (STATCOM) and a static synchronous series compensator (SSC) coupled via a common DC voltage link. The parameters such as voltage, impedance and phase angle are simultaneously or selectively controlled by this controller. [4]

Unified Power Flow Controller (UPFC) is the last generation of FACTS devices. All three parameters of line power flow (line impedance, voltage and phase angle) can be simultaneously controlled by the UPFC. The features of two "old" FACTS devices are combined together in these "new" FACTS devices: the Static Synchronous Compensator (STATCOM) and the Static Synchronous Series Compensator (SSSC). In practice, these two devices are two Voltage Source Inverters (VSI's) connected respectively in shunt with the transmission line through a shunt transformer and in series with the transmission line through a series transformer, connected to each other by a common dc link including a storage capacitor. The balance of the real power flow exchanged between the series inverter and the transmission line and voltage regulation at the point of connection injecting an opportune reactive power flow into the line is done by the shunt inverter. The real and reactive line power flow inserting an opportune voltage with controllable magnitude and phase in series with the transmission line is controlled by the series inverter. Reactive shunt compensation, active and reactive series compensation and phase shifting are some of the functions fulfilled by the UPFC. Stability control to suppress power system oscillations improving the transient stability of power system is a second but important function performed by the UPFC. There is a corresponding need for reliable and realistic models of these controllers to investigate the impact of UPFC controllers, as there use is expected to grow in the future. [5]

2.2 UPFC Characteristics

A basic UPFC functional scheme is shown in Fig.2.1. Two voltage source inverters (VSI's) sharing a common dc storage capacitor, and connected to the system through coupling transformers are the basic components of the UPFC. One VSI is connected in series through a series transformer while the other one is connected in shunt to the transmission system via a shunt transformer. [6]

Fig. 2.1: UPFC Functional Scheme

A symmetrical three phase voltage system, vse, of controllable magnitude and phase angle in series with the line to control active and reactive power flows on the transmission line is injected by controlling the series inverter. Active and reactive power with the line will be exchanged by the inverter. The active power is transmitted to the dc terminals and the reactive power is electronically provided by the series inverter. The demand for dc terminal power (positive or negative) from the line keeping the voltage across the storage capacitor Vdc constant is done by the operation of the shunt inverter. The losses of the two inverters and their transformers are equal to the net real power absorbed from the line by the UPFC. A voltage regulation at the connection point is achieved by the remaining capacity of the shunt inverter and by exchanging reactive power with the line. The working of the two VSI's is independent of each other by separating the dc side. Thus the series inverter is operating as SSSC that generates or absorbs reactive power to regulate the current flow, and hence the power flows on the transmission line and the shunt inverter is operating as a STATCOM that generates or absorbs reactive power to regulate the voltage magnitude at the connection point. Various operating modes of the UPFC are possible. A controllable current ish into the transmission line is injected by the shunt inverter. The two components of this current with respect to the line voltage are: the real or direct component ishd, which is in phase or in opposite phase with the line voltage, and the reactive or quadrature component, ishq, which is in quadrature. The requirement to balance the real power of the series inverter automatically determines the direct component. Within the capability of the inverter, the quadrature component can be independently set to any desired reference level (inductive or capacitive) to absorb or generate respectively reactive power from the line. The possible control modes are: [7]

VAR control mode: inductive or capacitive var request is the reference input;

Automatic Voltage Control mode: the maintenance of the transmission line voltage at the connection point to a reference value is the goal. The voltage vse controllable in amplitude and phase angle in series with the transmission line, injected by the series inverter, influences the power flow on the transmission line.

Direct Voltage Injection mode: the phase angle of the series voltage and the reference inputs are directly the magnitude;

Phase Angle Shifter Emulation mode: the phase displacement between the sending end voltage and the receiving end voltage is the reference input;

Line impedance emulation mode: impedance value to insert in series with the line impedance is the reference input;

Automatic Power flow Control mode: are values of P and Q to maintain on the transmission line despite system changes are the reference inputs.

Generally the series inverter will be operated in Automatic Power Flow Control mode and general the shunt inverter in Automatic Voltage Control mode. [8]

Fig. 2.2: Phasor Representation of the UPFC

2.3 UPFC Model

2.3.1 Instantaneous Power Flow Delivered by a VSI Into a Power System

Three symmetrical sinusoidal voltage sources can be used to represent an inverter connected to a power system, which is capable of power exchange between the power system and the dc storage capacitor. A synchronously-rotating orthogonal system can be used to represent a symmetrical three-phase system. Rotating at the synchronous angular speed of the fundamental network voltage w, new coordinate system is defined on the basis of the d-q transformation. In Fig 2.2 a VSI is supplied by a voltage system vxa, vxb, vxc, R and L are respectively the transformer equivalent resistance and inductances. [9]

Fig. 2.3: Equivalent Circuit of a VSI Connected to a Power

Neglecting transformer losses and assuming fundamental frequency and balanced conditions, the instantaneous active and reactive power flowing into the power system delivered by the VSI are:

p(t) = 1.5 * vxd * ixd q(t) = 1.5 * vxd * ixq

2.3.2 Series and Shunt Inverter Control

Connected respectively in series and in shunt to the transmission line, two ideal controllable voltage sources have been chosen as a UPFC model as shown in Fig.2.3 to represent respectively the series and the shunt inverters. To evaluate the amplitude and the phase angle of these two voltage sources on the basis of operating functions of the required UPFC the two UPFC control systems must be developed in such a way. To obtain the active and reactive power flows desired at the receiving end, the amplitude and phase angle of the equivalent series voltage source are determined assuming the series inverter is operating in Automatic Power Flow Control mode. To control the voltage on the connection point (v1) or to generate or absorb a specific reactive power at this point respectively and naturally to supply or absorb the active power demanded by the series inverter, the amplitude and phase angle of the equivalent shunt voltage source are calculated assuming that the shunt inverter is operating in Automatic Voltage Control or in VAR Control mode. Assuming vrd equal to the receiving end voltage amplitude vr and vrq=0 on the basis of (3) the instantaneous power flow at the receiving end results:

p(t) = 1.5 * vrd * idline q(t) = 1.5 * vrd * iqline

where idline and iqline are respectively the values of the d-q line current components. So, it's possible to calculate the reference values of the d-q line current components as follows:

i*dline = 2/3 * p* r/ vrd i*qline = 2/3 * q* r/ vrd

The instantaneous active and reactive power flow required the receiving end are p* r and q* r. The instantaneous active and reactive power flows provided by the shunt inverter at the connection point in the same way are:

p(t) = 1.5 * v1d * idsh q(t) = 1.5 * vld * iqsh

assuming v1d equal to the sending end voltage amplitude v1 and v1q=0 and with idsh and iqsh the d-q current components injected by shunt inverter into the transmission line. So, the reference values of these two current components are evaluated as follows:

i*dsh = 2/3p*sh / vld i*qsh = 2/3q*sh/ v1d

where p* sh and q*sh are the instantaneous active and reactive power flow required to the shunt inverter. In the report these control systems are based on the classical "decoupled watt-var algorithm" using the d-q axis decomposition

Fig. 2.4: UPFC Equivalent Circuit

For the independent control of active and reactive power at the receiving end (pr, qr) of the power system, the input values for the series inverter control system are: instantaneous values of the sending and receiving end voltages and the line current, and the reference values p* r and q* r.

To control the active and reactive power flow provided to the sending end (psh, qsh) in VAR control mode the input values for the shunt inverter control system are: instantaneous values of sending end voltage v1, the instantaneous value of the current injected by shunt inverter ish into the transmission line, the reference value q*sh and the value of the active power p*sh evaluated so to balance the active power exchange between the series inverter and the transmission line. [10]

2.3.3 Inverter Control Technique

To control the GTO switching of an inverter, there are two basic strategies that can be utilized. Multi-connected out of phase inverters with a common dc source and coupled through appropriate magnetic circuits is one method. Use of PWM switching techniques is another method.

Fig. 2.5: UPFC - Series Inverter Control Scheme

Fig. 2.6: UPFC - Shunt Inverter Control Scheme

2.3.4 DC-Side Control

The dc voltage across the dc storage capacitor Cdc must be kept constant for normal operation of two VSI's in an UPFC. The result of this is that the active power exchanged between the UPFC and the power system is zero at steady state operation:

pse + psh = 0

that is, the active power exchange between the series inverter and the transmission line, pse is equal to the active power delivered by the shunt inverter psh . To keep Vdc constant by taking the actual value of Vdc as the feedback signal against a dc reference signal V* dc ,a dc voltage control system must be realized as shown in Fig.2.4. To the pre-value of the active power exchanged between the series inverter and the transmission line, p* se evaluated on the basis of the reference value of d-q line current components, is added the resulting dc voltage error processed by a proportional controller. [8]

Fig. 2.7: dc Voltage Regulator Scheme

The reference value for the active power which must provided by the shunt inverter, p* sh is the output signal of this control system.

CHAPTER 3

NUMERICAL EXAMPLE

The five bus network as shown in Fig 3.1 is modified to include the transmission line linking bus Lake and bus Main. The UPFC is used to maintain active and reactive powers leaving the UPFC, towards MAIN , at 40 MW and 2 MVAR respectively. Moreover, the UPFC shunt converter is set to regulate the nodal voltage magnitude at Lake at 1 p.u.

Table 3.1: Maximum Power Mismatches in the Bus System and UPFC

Itearation

Buses

UPFC

∆P

∆Q

∆Pmk

∆Qmk

PcR + PvR

1

7.745e-1

1.410e-1

5.0e-04

4.0e-02

0

2

1.89e-2

1.001e-2

5.1e-03

6.5e-02

5.7e-03

3

3.8e-03

5.1e-04

3.7e-03

5.0e-04

8.6e-05

4

1.2e-07

1.6e-06

1.2e-07

1.6e-6

1.2e-07

5

1.3e-12

1.9e-13

1.2e-12

1.8e-13

1.3e-14

CHAPTER 4

CONCLUSION

The basic working principles of FACTs controllers was studied in detail and the advantages of FACT controllers were understood. FACTs technology helps in controlling power flows, reduces loop flows and also helps in reducing reactive power flows thus allowing transmission lines to carry more active power.

The working of a Unified Power Flow Controller (UPFC) was understood and its characteristics studied. A UPFC model was developed and its control schemes such as series and shunt inverter control, and d.c side control were studied.

A program was written in MATLAB code to incorporate the Unified Power Flow Controller (UPFC) model with the Newton-Raphson power flow algorithm.

APPENDIX

Program written in MATLAB to incorporate the Unified Power Flow Controller (UPFC) model with the Newton-Raphson power flow algorithm

%---Main UPFC Program

PowerFlowsData; %Function to read network data

UPFCdata ; %Function to read the UPFC data

[ YR,YI ] = YBus ( t1send, t1rec, t1resis, t1reac, t1suscep, t1cond, nt1, nbb );

[ VM, VA, it, vcr, Tcr, Vvr, Tvr ] = UPFCNewtonraphson (to1, itmax, ngn, nld, nbb, bustype, genbus, loadbus, PGEN, QGEN, QMAX, QMIN, PLOAD, QLOAD, YR, YI, VM, VA, NUPFC, UPFCsend, UPFCrec, Xcr, Xvr, flow, Psp, Psta, Qsp, QSta, Vcr, Tcr, Vcrlo, VcrHi, VVr, Tvr, VvrLo, VvrHi, VvrTar, Vvrsta);

[ PQsend, PQrec, PQloss, PQbus ] =PQflows ( nbb, ngn, ntl, nld, genbus, loadbus, t1send, t1rec, t1resis, t1reac, t1cond, t1suscep, PLOAD, QLOAD, VM, VA );

[ UPFC_PQsend, UPFC_PQrec, PQcr, PQvr ] = PQUPFCpower ( nbb, VA, VM, NUPFC, UPFCsend, UPFCrec, Xcr, Xvr, Vcr, Tcr, Vvr, Tvr );

%Print results

it %Number of iterations

VM %Nodal voltage magnitude (p . u. )

VA=VA*180/pi %Nodal voltage phase angles (deg )

Sources= [ Vcr, Tcr*180/pi, Vvr, Tvr*180/pi ] %Final source voltage parameters

UPFC_PQsend %Active and reactive power in sending bus ( p. u . )

UPFC_PQrec %Active and reactive power in receiving bus ( p. u . )

% End of MAIN PROGRAM

%Carry out iterative solution using the Newton-Raphson method

function [ VM, VA, it, Vcr, Tcr, Vvr, Tvr ] = UPFCNewtonRaphson ( to1, itmax, ngn, nld, nbb, bustype, genbus, loadbus, PGEN, QGEN, QMAX, QMIN, PLOAD, QLOAD, YR, YI, VM, VA, NUPFC, UPFCsend, UPFCrec, Xcr, Xvr, Flow, Psp, PSta, Qsp, QSta, Vcr, Tcr, VcrLo, VcrHi, VvrTar, VvrSta );

% GENERAL SETTINGS

flag = 0;

it = 1;

% CALCULATE NET POWERS

[ PNET, QNET ] = Net Powers ( nbb, ngn, nld, genbus, loadbus, PGEN, QGEN, PLOAD, QLOAD );

while ( it < itmax & flag ==0 )

% CALCULATE POWERS

{ PCAL, QCAL ] = CalculatedPowers ( nbb, VM, VA, YR, YI );

%CALCULATED UPFC POWERS

[ PspQsend, PspQrec, PQvr, PCAL, QCAL ] = UPFCcalculatedpower ( nbb, VA, VM, NUPFC, UPFCsend, UPFCrec, Xcr, Xvr, Vcr, Tcr, Vvr, Tvr, PCAL, QCAL );

% POWER MISMATCHES

[ DPQ, DP, DQ, flag ] = PowerMismatches ( nbb, to1, bustype, flag, PNET, QNET, PCAL, QCAL );

%UPFC POWER MISMATCHES

[ DPQ, flag ] = UPFCPowerMismatches (flag, to1, nbb, DPQ, VM, VA, NUPFC, Flow,Psp, PSta, Qsp, QSta, PspQsend, PspQrec, PQcr, PQvr );

if flag == 1

break

end

% JACOBAIN FORMATION

[ JAC ] = NewtonRaphsonJacobian ( nbb, bustype, PCAL, QCAL, DPQ, VM, VA, YR, YI );

%MODIFICATION OF THE JACOBIAN FOR UPFC

[ JAC ] = UPFCJacobian ( nbb, JAC, VM, VA, NUPFC, UPFCsend, UPFCrec, Xcr, Xvr, Flow, PSta, QSta, Vcr, Tcr, Vvr, Tvr, VvrSta );

%SOLVE JACOBIAN

D = JAC\DPQ ;

%UPDATE THE STATE VARIABLES VALUES

[ VA, VM ] = StateVariablesUpdating ( nbb, D, VA, VM, it );

%UPDATE THE TCSC VARIABLES

[ VM, Vcr, Tcr, Vvr, Tvr ] = UPFCUpdating ( nbb, VM, D, NUPFC, UPFCsend, Psta, QSta, Vcr, Tcr, Vvr, Tvr, VvrTar, VvrSta );

%CHECK VOLTAGE LIMITS IN THE CONVERTERS

[ Vcr, Vvr ] = UPFCLimits ( NUPFC, Vcr, VcrLo, VcrHi, Vvr, VvrLo, VvrHi );

it = it + 1;

end

%Function to calculate injected bus power by the UPFC

function [ UPFC_PQsend, UPFC_PQrec, PQrec, PQcr, PQvr, QCAL ] = UPFCCalculated power ( nbb, VA, VM, NUPFC, UPFCsend, UPFCrec, Xcr, Xvr, Vcr, Tcr, Vvr, Tvr, PCAL, QCAL );

for ii = 1 : NUPFC

Bkk = -1/Xcr ( ii )-1/Xvr ( ii );

Bmm = -1/Xcr ( ii );

Bmk = 1/Xcr ( ii );

Bvr = 1/Xvr ( ii );

for kk = 1 : 2

A1 = VA ( UPFCsend ( ii ) )-VA ( UPFCrec ( ii ) );

A2 = VA ( UPFCsend ( ii ) )-Tcr ( ii );

A3 = VA ( UPFCsend ( ii ) )-Tvr ( ii );

% Computation of Conventional Terms

Pkm = VM ( UPFCsend ( ii ) )*VM ( UPFCrec ( ii ) )*Bmk*sin ( A1 );

Qkm = -VM ( UPFCsend ( ii ) )^2*Bkk - VM ( UPFCsend ( ii ) )*VM ( UPFCrec ( ii ) )*Bmk*cos( A1 );

%Computation of Shunt Converters Terms

Pvrk = VM ( UPFCsend ( ii ) )*Vvr ( ii )* Bvr*sin ( A3 );

Qvrk = -VM ( UPFCsend ( ii ) )*Vvr ( ii )* Bvr*cos ( A3 );

if kk == 1

%Computation of Series Converters Terms

Pcrk = VM ( UPFCsend ( ii ) )*Vcr ( ii )*Bmk*sin ( A2 );

Qcrk = -VM ( UPFCsend ( ii ) )*Vcr ( ii )*Bmk*cos ( A2 );

%Power in bus k

Pk = Pkm + Pcrk + Pvrk;

Qk = Qkm + Qcrk + Qvrk;

UPFC_PQSEND ( ii ) ) = Pk + Qk*I;

PCAL ( UPFCsend( ii ) ) = PCAL ( UPFCsend ( ii ) + Pk;

QCAL ( UPFCsend( ii ) ) = QCAL ( UPFCsend ( ii ) + Qk;

%Power in Series Converter

Pcr = Vcr ( ii ) )*VM ( UPFCsend ( ii ) )*Bmk*sin ( -A2 );

Qcr = -Vcr ( ii ) )^2*Bmm - Vcr ( ii )*VM ( UPFCsend ( ii ) )*Bmk*cos ( -A2 );

%Power in Shunt Converter

Pvr = Vvr ( ii )*VM ( UPFCsend ( ii ) )*Bvr*sin ( -A3 );

Qvr = Vvr ( ii )^2*Bvr - Vvr ( ii )*VM ( UPFCsend ( ii ) )*Bvr*cos ( -A3 );

PQvr ( ii ) = Pvr + Qvr*i;

else

% Computation of Series Converters Terms

Pcrk = VM ( UPFCsend ( ii ) )*Vcr ( ii )*Bkk*sin ( A2 );

Qcrk = -VM ( UPFCsend ( ii ) )*Vcr ( ii )*Bkk*cos ( A2 );

%Power in Bus m

Pcal = Pkm + Pcrk;

Qcal = Qkm + Qcrk;

UPFC_PQrec ( ii ) = Pcal + Qcal*I;

PCAL ( UPFCsend ( ii ) ) = PCAL ( UPFCsend ( ii ) ) + Pcal;

QCAL ( UPFCsend ( ii ) ) = QCAL ( UPFCsend ( ii ) ) + Qcal;

%Power in Series Converter

Pcr = Pcr + Vcr ( ii )*VM (UPFCsend ( ii ) )*Bkk*sin ( -A2 );

Qcr = Qcr - VM (UPFCsend ( ii ) )*Vcr ( ii )*Bkk*cos ( -A2 );

PQcr ( ii ) = Pcr + Qcr*I;

end

send = UPFCsend ( ii );

UPFCsend ( ii ) = UPFCrec ( ii );

UPFCrec ( ii ) = send;

Beq = Bmm;

Bmm = Bkk;

Bkk = Beq;

end

end

%Function to compute power mismatches with the UPFC

function [ DPQ, flag ] = UPFCPowerMismatches ( flag, to1, nbb, DPQ, VM, VA, NUPFC, Flow, Psp, PSta, Qsp, QSta, UPFC_PQsend, UPFC_PQrec, PQcr,, PQvr );

iii = 0;

for ii = 1 : NUPFC

index = 2*(nbb + ii ) + iii;

if PSta( ii ) == 1

if Flow ( ii ) == 1

DPQ ( index-1 ) = Psp ( ii ) - real (UPFC_PQsend ( ii ) );

else

DPQ ( index-1 ) = -Psp ( ii ) - real (UPFC_PQrec ( ii ) );

end

else

DPQ ( index-1) = 0;

end

if QSta ( ii ) == 1

if Flow ( ii ) == 1

DPQ ( index ) = Qsp ( ii ) - imag ( UPFC_PQrec ( ii ) );

else

DPQ ( index ) = -QSP ( ii ) - imag ( UPFC_PQrec ( ii ) );

end

else

DPQ ( index ) = 0;

end

DPQ ( index + 1 ) = -real ( PQcr ( ii ) + PQvr ( ii );

iii = iii + 1;

end

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