The Analogue Video Format Engineering Essay

Published: Last Edited:

This essay has been submitted by a student. This is not an example of the work written by our professional essay writers.

The Analogue video format has been dominant in the video world; until recently digital television was restricted to the professional video editing fields due to the cost factor. The bulk expansion of the digital video market has led to reducing cost; hence more consumers have access to the digital video. This leads to the need for bridging the gap between analogue video and digital video.

Evolution of Video

Analogue video began with the grayscale (black and white) information; RGB (Red, Green, and Blue) system was initially the primary color transmission system used. This technique occupied three times more bandwidth than grayscale and was superseded by the YUV color information system. The YUV system is more preferable over the RGB system as it uses one signal rather than three separate signals to represent color. This composite video signal is what the PAL video standards are based on today.

FM Radio

A Radio is a device capable of receiving, filtering, demodulating and amplifying the received signal to re-produce quality sound transmitted by radio broadcasting stations. The radio is the most commonly used device by people today for information and entertainment on the move.

Technology today is constantly evolving in order to stay abreast with the rising need from the consumer, hence enhanced and superior products are being created to efficiently perform tasks that were deemed difficult if not impossible.

Cool FM Picture Radio

Cool FM Picture over radio is the new age device that is capable of receiving audio signals along with picture. This is done by modulating the audio and picture on a carrier signal of a designated frequency.

The project is divided into several tasks, where mine focuses primarily on the video capture, processing and display. There are some overlapping areas with the other tasks as well such as the design of the receiver.

The Picture involved in this project is received from a standard Analogue video Cam, in a format known as PAL.

Phase alternating line (PAL) is a universally know video format with is used is several countries across the world. It is highly preferred compared to the other such as NTSC or SECAM because of its higher number of frame lines which offers the viewer a higher detail.


2.1 Composite PAL Video Signal

A video is a series of still images (Frames) changing at a sufficient rate in order to give an illusion on continuity. Each image is comprised of individual lines of data.

The composite video signal consists of a camera (image) signal corresponding to the desired picture information, blanking pulses to make the retrace invisible, and synchronization pulses to synchronize transmitter and receiver scanning [2].

Vertical Sync is required to specify the start of an image. A single image is composed a sequence of data lines that occur successively down the display screen, these data lines are referred to as scan lines. The Horizontal Sync is required to specify the start of each scan line. The Efficiency of the picture signal transmission is kept high by maintaining the same amplitude for both horizontal and vertical sync. However, the duration (width) of a single pulse is different for separating them at the receiver [2]. Sync pulses are sent on time division basis, as they are required consecutively in the composite video signal.

Displays three different brightness lines of an image. The video signal is limited to vary in certain amplitude limits. The greatest brightness of an image will correspond to the peak white level. This is maintained at 10 to 12.5 percent of the maximum value of the signal, while the black level is at 72 of the maximum signal. The sync pulses are embedded in the composite video signal at the blanking level, 75 percent of the maximum value of the signal. The Pedestal is the difference between the black level and blanking level.

Bandwidth of a PAL signal

BW= (W/H) x Nx (n/2)Hz

Aspect ratio = W/H (4:3)

N=625 (number of horizontal scan lines)

N=25 (Frames per sec)

The details of the image will determine the bandwidth. The important information is embedded in low frequencies; overall color signal is limited to 2 MHz [color television: Theory and Practice by BALI Pg. 36].

Composite video signal DC component

Individual images will cause a variation (AC component) in the amplitude of the composite video signal; however the composite video signal also has a DC component matching to the average brightness of the image. The DC component will aid the receiver in determining the changes in brightness, an example of such is grey picture in a black background would generate the same signal as a white picture on a grey background [3, Gulati]. The DC component changes from image to image, and does not change between scan lines of an image.

The Sync Pulses

The composite video signal contains both picture signal and synchronization pulses. The picture signal is confined between 12.5 -65 percent of the amplitude of the carrier signal while the upper 25 percent is occupied by the sync pulses [3, Gulati].

Horizontal Line Sync Pulse

The single composite video horizontal scan line is 64s long. The horizontal blanking period is 12 s. The horizontal synchronization pulses are embedded in to the composite video signal, during the horizontal blanking period.

The Horizontal scan line blanking period is composed of three components. These are the Front Porch, the Line synchronization pulse, and the Back Porch.

Front Porch

The front porch duration is 1.5s and is inserted in the horizontal scan line blanking period between the end of the image signal and the rising edge of the horizontal sync pulse as seen in Figure 3.1. This period permits the receiver to clear the voltage remained from the end image signal to the blanking level to prevent any interruptions for the horizontal sync pulse which follows immediately after the front porch[3, Gulati].

Horizontal Sync Pulse

The Horizontal Sync Pulse duration is 4.7 s and immediately follows the front porch during the horizontal blanking interval as seen in Figure 3.1. The TVP5150AM1 PBS is responsible for the separation of the horizontal Sync pulses from the blanking interval. These pulses are utilized to keep the received images in sync with the transmitted ones.

Back Porch

The Back porch duration is 5.8 s, and occurs after the horizontal line sync pulse during the horizontal blanking interval as seen in Figure 3.1. The Back porch provides sufficient time between horizontal scan lines to prevent merging from occurring.

Vertical Sync Pulse

The Vertical Sync Pulse is added at the end of both even and odd fields as shown in Figure 3.4(Gulati). The width of the vertical sync pulse supersedes the width of the horizontal sync pulse by 2.5 to 3 times [3.3, Gulati]. The field sweep oscillator uses the width of the pulse to distinguish between horizontal and vertical sync, and triggers on a vertical sync.

In the PAL 625 Line system, the vertical sync pulses occur every 2.5 lines period (2.5 X 64s= 160s) [3.3 , Gulati]. According to the Figure 3.4 a vertical sync pulse occurs commences at the 1st Half of 313th Line (field 1 end) and terminates at the end of 315th Line [3.3, Gulati]. Figure 3.4 Part B shows another vertical sync pulse occurring at the 1st Line (field 1 beginning) and terminates at the 1st Half of the 3rd Line[3.3, Gulati]. The horizontal sync pulse maintains its punctuality every 64s except during vertical sync pulse, where it apparently shifts by 32 s [3.3 Gulati].

Composite Video Signal sync pulse separation and generation of vertical and horizontal sync pulses

The composite video signal contains both horizontal and vertical sync information. The horizontal sync pulse is extracted from the composite by using differentiation. This is done using a high pass filter.

The vertical sync pulse is extracted from the composite by using integration, the low pass filter.

The Time- Constant for the high pass filter (Differentiator) is selected such that when the trailing edge arrives, the pulse due to the leading edge has just about decayed [3.3, Gulati]. The Negative going triggering pulses can be extracted by using a diode as horizontal sweep oscillator requires only the positive going pulse in locking.

The horizontal sync pulses are present during both active and blanking line regions; however no horizontal sync pulses are present during the vertical blanking interval (2.5s).

Equalizing Pulses

These are five narrow pulses which are added to the start and end of the vertical sync pulse. These are called pre-equalizing and post-equalizing pulses, each will take up 160s before and after the vertical sync pulse. The pre-equalizing pulses are used to discharge the capacitor (Low Pass Filter) to zero voltage, before the arrival of the vertical sync pulses.

Post-equalizing pulses are very crucial in order to fast discharge the capacitor (Low Pass Filter) and to guarantee an appropriate time triggering of the vertical oscillator. Absence of the post-equalizing pulses will yield a slow discharge, this would result in the vertical oscillator triggering on the trailing edge which may be far away from the leading edge, and thus a triggering error would occur [3.3 pg 45, Gulati].

An integrating circuit with a large time constant (RC) would correct this problem, as the horizontal sync pulse would not be able to charge the capacitor; however a reduction in the integrator (Low Pass Filter) output would be significant problem and would require the use of a vertical sync amplifier.

Shown in Figure 3.10 are the equalizing pulse trains for both fields.

Summary PAL composite video signal progression details

Shown below is a progression timing summary table for the various components (discussed earlier) in the composite video signal.

Period Time(s)

Total horizontal line 64

Horizontal blanking interval 123

Horizontal synchronization pulse 4.70.2

Front porch 1.50.3

Back porch 3.80.3

Visible line time 52

Table 1

PAL Digital Decoding

Luminance and chrominance components in a PAL video signal are combined. The first step in digitally decoding the PAL composite video signal is to digitise the complete composite video signal using an analogue to digital converter (ADC). The video input of the decoder circuit has a 39? AC-DC input impedance and is AC- Coupled, as a result of this we need to DC restore every scan line during the horizontal synchronisation in order to set the sync peaks to a know voltage value.

Composite video signal possesses high frequency components; these may lead to aliasing and require to be removed using a low pass filter.

The consumer market offers a variety of amplitudes ranging from 0.25X to 2X. The PAL digital decoder is required to be able to handle 100% of the colours received in the composite video signal although only 75% of the colours may be broadcast.

DC restoration

Clamping is the process used to remove the DC offset from composited video signal. During each Horizontal Synchronisation time, the luminance (Y) video signal is DC restored to the reference voltage of the analogue to digital converter, thus the analogue to digital converter generates a code of 0 during the sync level [pg406, Video demystified]. The chrominance (Cb, Cr) video signal is DC restored to half the reference voltage of the analogue to digital converter. The ADC generates a code of 512 during blanking level [pg406, Video demystified].

Automatic Gain Control

Automatic Gain Control (ACG) is an adaptive system that uses the feedback method to adjust the gain to the desired value. The analogue to digital converter is required to generate a fixed value for the blanking level; hence the ACG is required to ensure the constancy. If the blanking level is too high or low the video signal is attenuated or amplified to the required level.

Upon completion of the DC restoration and the ACG processing an offset value is added to the digitized luminance and chrominance signals to match the levels used by the decoder.

Determination of Blank Level

A low pass filter is used determine the blanking level. The video signal passes through the low pass filter; this causes the subcarrier information and noise to be removed. Multiple sampling of the back porch (see description) is used to determine the average blank level. The result is averaged over 3-32 scan lines in order to limit line to line variations and clamp streaking[pg406, Video demystified].

Sync Amplitude AGC

The difference between the measured and ideal blanking level is used to determine how much to increase or decrease the gain of the entire video [pg407, Video demystified].

This mode of automatic gain control is used where the characteristics of an unknown video signal.

Burst Amplitude Automatic Gain Control

This method of automatic gain control utilizes the colour burst amplitude. It is used when the active video amplitude is unrelated to the sync amplitude. Blanking level is adjusted to the ideal value by summing or subtracting a DC offset value from the video amplitude, not considering the sync peak position. The burst amplitude output is averaged over 3-32 scan lines to obtain an accurate value. The amount of increase or decrease in gain required by the video signal is the difference between the measured and the ideal burst amplitude [pg409, Video demystified].

2.2 Luminance and Chrominance separation

Luminance and Chrominance

The Luminance component of the video system is responsible for the brightness of an image, edge information and contrast, while the two chrominance components represent the colour difference. The human eye is less sensitive to the colour acuity of an image, while very sensitive to the brightness of an image. This restricts the luminance to full detail (most bandwidth allocated to it) in order to convey sharp and crisp images, while chrominance may be reduced by sub sampling as the human eye would not be able to point out the reduction in colour acuity; thus conserving bandwidth.

Chrominance information is a quadrature modulated on to the luminance. The chrominance signal is modulated on to a carrier which resides at 4.43MHz for PAL signals and a typical bandwidth ranging from 0.6MHz to 1.3MHz. The YUV colour coordinate system is utilised by the chrominance modulation, where the hue and saturation is in vector format.

The decoding of the PAL composite video signal requires two main processes in sequential order.

Firstly the luminance (Y) and the chrominance (C) are separated from the PAL composite video signal. This however is a challenging task to separate the luminance from chrominance as the luminance information shares a mutual bandwidth from 2MHz to 5MHz with the chrominance.

Secondly to demodulate the chrominance (colour information signal) in to the original colour difference signals.

The synchronisation information is also embedded in the PAL composite video signal (see PAL composite video above) along with the colour reference bursts signals.

The luminance(Y) and chrominance(C) must be separated when decoding a PAL composite video signal. There are several techniques used to do this:

Technique 1: Low pass/ high pass filter separation

Low pass/ high pass filter separation technique is one of the first techniques used to separate the luminance (Y) and the Chrominance (C) signals from the PAL composite video signal. Luminance is extracted by using a low pass filter with a cut-off frequency of 2 -2.5 Hz. The chrominance signal is extracted by using a high pass filter with a band pass characteristic of 2.5MHz to 5MHz. The Figure 3 shows the frequency spectrum for this technique, this technique work as the chrominance information is centred on the 4.43MHz for PAL and extends down to 2.5MHz [AN9644 OCT2006, Pg3-4, Application Note].

The drawback for this technique is that a significant amount of detail is lost as the edges of an object in a scene contains a very high frequency information, and loss of such frequencies will result in an unclear picture [AN9644 OCT2006, Pg3-4, Application Note].

The comparison of an ideal multi-burst waveform with a low pass/ high pass filter separation technique is shown in Figure 10a&b.

10(a) 10(b)

11(a) 11(b)

In the Figure 11a, it is noticeable that the frequencies at 2 MHz- 5 MHz have been attenuated. The Figure 11b displays the severity of alteration of the multi burst line.

Technique 2: Colour Trap Filter Separation Technique

This technique employs a notch filter centred chrominance subcarrier frequency of 2.5MHz to 4.5MHz. The frequency spectrum is shown in figure 12.

This technique has two major problems. The primary problem being that chrominance is band limited to 2.5MHz 4.5MHz; however chrominance signal may range from 2.1MHz. This causes loss of colour information. The secondary problem being that as the chrominance is band passed, a small percentage of luminance also gets band passed through the notch filter. This results in the contamination of the chrominance signal, leading to unwanted colours. Pictures that contain closely packed black and white lines will be affected the most.

The comparison of an ideal multi-burst waveform with a colour trap separation technique is shown in Figure 13 & 14.

(a) (b)

Figure 13a&b shows the ideal waveform from a video generator [Retrieved from AN9644 OCT2006, Pg 6, Application Note].

(a) (b)

In Figure 14a, attenuation is noticeable at frequencies of 3.58MHz -5MHz. The

Technique 3: Comb Filter Separation Technique

The digital comb filter employs a line store memory. The temporal spectrum on a still image collapses in to discrete lines; hence it is feasible to perform luminance and chrominance separation using a comb filter which is based on field delays. The primary advantage of the comb filter is that it produces full bandwidth, ensuring a very crisp luminance and very minute amount of cross colouring [AN9644 OCT2006, Pg 5, Application Note].

The PAL video standard requires of a 4- line adaptive comb filter as a 2- line comb will not be sufficient enough to separate the luminance and chrominance. The chrominance in PAL video standard is interleaved at every quarter line offset. The comb filter separation technique adds and subtracts two lines of the image to separate the PAL composite video into luminance and chrominance. The quarter line offset and the phase shift of the chrominance V component leads to the 2- line comb to be insufficient. The chrominance signal is moved from the quarter line spectral spacing to the half line spacing using a correction factor [AN9644 OCT2006, Pg 5, Application Note]. The figures 15(a-d) are retrieved from AN9644 OCT2006

2.3 Colour difference processing

Chrominance(C) demodulation

The chrominance demodulator receives input from the luminance/Chrominance separation module. The input signal received is converted to the YCbCr colour space. The digital chrominance signal is demodulated using sine and cosine subcarrier data resulting in CbCr [pg 409, Video Demystified].

The frequency used for the consecutive formulae is:

?= 2?Fsc

Fsc=4.43361875MHz for PAL

PAL chrominance (C) signal is represented in the YCbCr Colour space by the following formulae:

(Cb 512)(0.533)(sin ? t) (Cr 512)(0.752)(cos ? t)

The Cb is obtained by multiplying the PAL chrominance (C) signal by [2 sin ? t]

(Cb 512) (0.533) (sin ? t) (Cr 512) (0.752) (cos ? t)( 2 sin ? t )

= (Cb 512)-((Cb 512) cos 2? t)) ((Cr 512) sin 2? t))

The Cr is obtained by multiplying the PAL chrominance (C) signal by [2 cos ? t]

(Cb 512)(0.533)(sin ? t) (Cr 512) (0.752) (cos ? t) ( 2 cos ? t)

= (Cr 512)-((Cb 512) sin 2? t)) ((Cr 512) cos 2? t))

The low pass filter will remove the 2?t component. The Cb and Cr will be extracted by the demodulation multipliers and will limit the signal to the maximum and minimum boundary values. The Cb and Cr are rounded to 8-bits, and low pass filtered [pg410, video demystified].

Low pass filter

The low pass filter is required after the demodulation multipliers. The low pass filter is used to provide a steeper roll of in order to ensure sufficient suppression of the sampling alias components [pg411, video demystified].

The low pass filter used will depend on a compromise between several factors. A 1.3MHz low pass filer with a pass band greater than 1.07MHz should be sufficient for this application. The low pass filter provides gain for frequencies between 0.6MHz and 1.3MHz, this compensates for the loss in the upper sidebands of chrominance. The figure 9.26 shows a frequency spectrum of 1.3MHz low pass filter.

2.4 Luminance processing

The data from the luminance and chrominance separation module will have the synchronisation and blanking information removed by the luminance processing, along with the black level. A notch filter with a 4.43MHz centre frequency is used to remove any remaining chrominance information [pg411, video demystified].

2.5 Genlocking (GCLO)

The Genlocking circuitry is responsible for the recovery of the sample clock and the timing signals from the video signal. The recovery of the timing signal will include the horizontal synchronization signal, vertical synchronisation signal and the colour subcarrier.

The sample clock is generated by multiplying the horizontal line frequency with the required number of samples per line using a phase lock loop [pg418, video demystified].

Horizontal synchronization detection

The comb filter will be used to determine the midpoint of the leading edge of the sync pulse. There are two types of horizontal sync locks:

Coarse horizontal sync locking

High frequency information which includes noise and colour subcarrier information is removed by putting the digitized video put through a 0.5MHz low pass filter. Sync detection is carried out in the low pass filtered data and in if fast sync edges are present edge shaping can occur [pg413, video demystified].

The sample clock causes the horizontal counter to be incremented. The counter is reset to 001H after counting reaching the total number of samples per line. The value of 001H on the horizontal counter indicates the expected beginning of a horizontal sync [pg416, video demystified].

The recovered sync information is detected only when the sync gate is enabled. The sync gate is enabled when the number of samples per line is 64. In the event of a detection of five consecutive missing sync signals the sync gate is disabled, until the horizontal counter reaches a count of 64 again. This aids in the filtration of equalizing pulses and noise [pg420, video demystified].

Equilibrium based horizontal sync locking

The reference point of the 0.5MHz low pass filtered signal is set to zero. This is done by subtracting the one half of the amplitude of the low pass filtered signal.

A series number of weighted samples are summed up from a region in the sync edge; this determines the horizontal sync edge [pg421, video demystified].

The Amplitude spectrum for weighted samples is shown in Figure6.0a and Figure 6.0b.

[Retrieved from pg422, video demystified].

Vertical synchronization detection

High frequency information which includes noise and colour subcarrier information is removed by putting the digitized video put through a 0.5MHz low pass filter. The 8-bit vertical counter counts from 001H to 625, and is reset back to 001H. The vertical counter is incremented by a horizontal sync signal.

001H specifies the beginning of a vertical sync for a particular field. The vertical counter is reset back to 001H when the end of a vertical sync is detected [pg422, video demystified].

The horizontal sync is monitored, if the recovered horizontal sync occurs more than 64 times and if it is less than half the number of samples per line, the vertical counter is not incremented [pg422, video demystified].

3. Implementation

3.1 Hardware Implementation

The following flowchart gives an overview of the entire implementation process.

The PIC16F877a Microcontroller Interface Board

The PIC16F877a is an 8bit microcontroller with reduced instruction set computing (RSIC) architecture. The PIC16F877a consist of several processing blocks. The central processing block is responsible for retrieving the instruction from the program memory, decoding it and finally executing it. The arithmetic and logic unit is responsible of the mathematical functions (adding, subtracting, multiplying) and the logic operations of the PIC16F877a.

The program is written and stored in a FLASH memory; this makes it very suitable for development boards as it can be cleared more than once. The EEPROM memory offers a permanent storage for data this makes it ideal for various applications. The PIC16F877a Microcontroller requires only two pins for data transfer using the ICSP port. This allows the microcontroller to be updated effortlessly.

The purpose of the PIC16F877a microcontroller in the project is that it provides the necessary tools for the manipulation of the output data produced by the PAL decoder circuit. The digital video signal is produced in 8 bits (YCbCr 4:2:2) from the output bus lines of the PAL decoder, along with timing output waveforms (HSYNC, VSYNC). The HSYNC indicates the beginning of each scan line and VSYNC indicates the end and beginning of a new frame (image).

The PIC16F877a microcontroller will provide the user with a main interface with the functions capture, erase and transmit. The user can select the desired task by using the keypad to enter the respective number for that task.

The capture feature will allow the user to start data input upon the detection on a digital 1 in the VSYNC and stop upon the detection of another digital 1 which indicates the end of previous frame (image) start of the next frame (image). The data received will be input in to the parallel Port C (RC0-RC7) of the PIC16F877a microcontroller. The VSYNC is input to the RA3 which is set as input (low) and HSYNC is input to the RA4 which is set as input (low). When Capture is pressed and RA3 waits until it detects a digital 1. When RA3 detects a digital 1 it enables the PORT Cs to accept input and store them to the PIC EEPROM Memory. The Capture stops when another digital 1 is detected on the RA3.

The erase feature will allow the user to delete the existing data in the EEPROM memory of the microcontroller.

The Transmit feature will transfer the data saved in the EEPROM memory to the output ports.

The PIC16F877a microcontroller has reset and memory clear push buttons. The rest button is used to set the microcontroller into a preset stable condition. The memory clear push button will erase the entire program memory of the PIC16F877a microcontroller, and can only be reprogrammed using the ICSP port with a USB programmer.

Assigning specific ports to be either input or output will depend on the TRISX register, where X being the name of the port (A, B, C or D). Setting the register to a digital 1 will cause it to behave as an input while setting it to a digital 0 will cause it to behave as an output.

The PIC16F877a microcontroller is made up of basic components, these are:

4X4 Matrix Keypad

16 pin dual controller LCD

External clocking circuit

Power supply

The following pages will describe the workings of the individual components of the PIC16F877a in order to achieve its goal as a microcontroller interface for the TVP5150AM1 PBS PAL decoder.

4X4 Matrix Keypad

The matrix keypad is the input for the PIC16F877a microcontroller. The matrix keypad has 16 push to make button switches. The matrix keypad uses a simple row and column co-ordinate system to identify the key pressed, when no key is pressed there is no connection between the rows and columns. Figure X below shows the row and column structural composition of a 4x4 matrix keypad.

Keypad Scanning

The key pressed is detected by scanning (continuous polling) the keypad. The matrix keypad is connected to the PORT D of the PIC16F877a. As seen in Figure x2, the PORTD pins RD0 to RD3 are set to output (low) and are connected to row1 to row4, while PORTD pins RD4 to RD7 are set to input (low) and are connected to column1 to column4. The PIC16F877a scans the keypad by sending an output high signal in specific sequence through the rows of the keypad, while awaiting an input high signal from the column inputs. While the PIC16F877a is scanning (continuous polling) and SW11 (Key 6) is pressed. The column 3 will detect and input high signal due to the connection established with row 2 through the SW11 (Key 6). This will be the element array co-ordinates (2,4) for the keypad matrix in the PIC16F877a microcontroller program and the key pressed will be retrieved from the array, for this instance will be number 6.

Figure 22 4X4 matrix keypad connection diagram with PIC16F877a

LCD Display

The main user interface will be displayed on the 16 pin dual controller LCD which will be the primary output device. The 16 pin dual controller LCD can support over 80 characters, the 2 line display will aid in a more presentable user interface.

Pin Description

Pin No. Pin Name Connection Description

1 VSS 7805 Voltage regulator (GND)

2 VDD 7805 Voltage regulator (+5V)

3 VEE Display contrast (+5V Full Brightness)

4 RS Data input configuration enabled(+5V or digital 1)

5 R/W Write input configuration enabled (GND or digital 0)

6 EN Enable signal(Unused)

7 D0 Data bus line 0 (Unused)

8 D1 Data bus line 1 (Unused)

9 D2 Data bus line 2 (Unused)

10 D3 Data bus line 3 (Unused)

11 D4 Data bus line 4 (Connected to RB4)

12 D5 Data bus line 5 (Connected to RB5)

13 D6 Data bus line 6 (Connected to RB6)

14 D7 Data bus line 7 (Connected to RB7)

15 BKL LCD Diode Backlight (+5V)

16 BKL LCD Diode Backlight (GND)

Table 2

The LCD will be interfaced with the parallel port of the PIC16F877a on the PORTB (RB4, RB5, RB6 and RB7). PORTB will be initialized as the output only port as the input from the LCD is not required in this application. The Read/ Write pin will be hard wired to ground as there is only write mode operations conducted in the LCD and it will prevent any conflicts on the data lines. The problem posed by output only ports is that the busy flag (indicator) which reports the completion of the processing of last instruction will not be read back in to the PIC16f877a microcontroller. The problem is overcome by placing known delay intervals.

The power supply for the LCD is derived from the capacitor decoupled 7805 voltage regulator (see voltage regulator).

The data sent from the PIC16F877a microcontroller is sent to the LCD. The display data RAM (DDRAM) stores the data in 8-bit character codes, and displays them on the LCD screen. The 2 line display will only allow 16 characters per line. The excess data will be stored in the DDRAM however will not be visible to the user, due to the limited viewing area.

Characters are displayed in the LCD using character generator ROM (CGROM). The CGROM permit the creation of custom characters on the LCD.

The busy flag indicator monitors the processing commands. The busy flag will be set to 1 when a command is executed on the LCD and will change back to 0 upon completion of the program.

The initialization of the LCD has to be done before data can be written. The Figure X5 shows the flow chart for initialization.

Power Supply Circuit (LM78M05CT Voltage Regulator)

The LM78M05CT is the three terminal voltage regulator. The voltage regulator accepts 9V as the input voltage and provides a smooth 5V output voltage.

A 50V 100nF capacitor is connected between the output and the ground. This is responsible for providing a smooth ripple free output voltage which is distributed to the PIC16F877a Chip and the 16X2 LCD. The output voltage is also used for the reset and memory clear push buttons for the PIC16F877a. A slide switch is tilizes to turn on or off the PIC microcontroller circuit and light emitting diode is used indicate power supply turned on.

Crystal Oscillator (20MHz)

The crystal oscillator is the external clock source for the PIC16F877a Microcontroller. The oscillator is connected along with two 22pF capacitors to the OSC1/CLKIN (PIN13) and OSC2/CLKOUT (PIN14). Figure X10 shows the crystal oscillator connections.

ICSP Programming Bus Port

The In Circuit Serial Programming (ISCP) port is used to program the PIC16F877a microcontroller. The PIC is programmed via USB using the PICkit 2 V.261 programming software, which burns the program on to the PIC in Hexadecimal format. The ICSP port is a bi directional port that also allows the reading of the PIC memory.

TVP5150AM1 PBS PAL Decoder Circuit

The TVP5150AM1 PBS is a 32 pin surface mounted device. This device is capable of decoding PAL, NTSC and SECAM analogue composite video signals, however for this project it is required to decode an analogue PAL composite signal. The input for the decoder is from an analogue video camera. The output expected from the decoder is a parallel 8-bit ITU-R BT.656 format. The parallel 8-bit ITU-R BT.656 output format is commonly known as the YcbCr 4:2:2 component video format.

The decoder tilizes a 9-bit analogue to digital converter to sample the analogue PAL composite video signal at a sampling frequency of 27MHz. The 27MHz is generated from the 14.31818MHz crystal oscillator.

The justification of the use of TVP5150AM1 PBS is that it is designed to work on ultralow power supply; this will tremendously increase the battery life in mobile applications for this project. Another advantage of this decoder is its ability to lock very weak and noisy signals.

The TVP5150AM1 PBS contains a four line adaptive comb filter along with a colour trap filter both of which will significantly aid in the prevention of cross chroma and cross luma.

The TVP5150AM1 PBS is divided in to several modules, the ones used in this project are:

Analogue to digital converter processor

Synchronisation signal detector

4 line adaptive comb filter (Luminance and chrominance separator)

Chrominance processor

Luminance processor

The terminal assignments for the TVP5150AM1 PBS are shown in figure X2. The terminal functions are listed in the table below:

Terminal Number Terminal Name I/O Functional Description

1 AIP1(A) I Composite video input.

2 AIP2(A) I Composite video input 2 (Unused).

3 PLL_AGND I PLL ground. Connected to analogue ground.

4 PLL_AVDD I PLL supply. Connected to analogue 1.8V supply.

5 XTAL1 I External clocking circuit. A single 14.31818MHz Crystal Oscillator PIN 1

6 XTAL2 O External clocking circuit. A single 14.31818MHz Crystal Oscillator PIN 2

7 AGND I Connected to Analogue Ground

8 RESETB I Active low rest. This is only trigger when PDN is a digital 1

9 PCLK/SCLK O System Clock/Pixel Clock

10 IO_DVDD I 3.3V digital supply voltage

11 YOU7 O MSB of the YCbCr 4:2:2 output

12-18 YOUT[6:0] O Decoded output YCbCr 4:2:2 with discrete sync

19 DGND I Digital ground.

20 DVDD I 1.8V digital supply voltage

21 SCL I/O I2C serial clock (Unused)

22 SDA I/O I2C serial data (Unused)

23 FID/GLCO O Vertical field indicator Lock/frequency control (Unused)

24 VSYNC O Vertical synchronization signal

25 HSYNC O Horizontal synchronization signal

26 AVID O Active video indicator, high during horizontal active time

27 VBLK O High during the vertical blanking interval

28 PDN I Power down terminal

29 REFP I Analogue to digital reference supply

30 REFM I Analogue to digital ground

31 CH_AGND I Analogue ground

32 CH_AVDD I 1.8V Analogue supply voltage

Table 3

The TVP5150AM1PBS chip being surface mounted requires the creation of a PCB board in order to be connected to the circuit. The schematic circuit of the decoder is designed in OrCAD Capture.

After the creation of the schematic the net list and connectivity check is conducted. The successful completion of the schematic error checks will lead to the start of the PCB creation process.

The PCB process is done by routing the copper tracks on both sides of the circuit board, the cross over from the top side to the bottom side is done using a thru hole tap. Every attempt is made in minimising the circuit board space used. The track width has to be minimized as the TVP5150AM1 PBS pin to pin spacing is very narrow. The error check is conducted after the completion of the copper routing. The errors detected are rectified and error check is conducted again. The successful completion of error checking marks the end of the PCB design.

The Gerber file along with the thru hole tap, top, bottom and net list files are submitted to the faculty office in order to print the PCB. The screenshots are seen in the images to follow.

The components are soldered on to the PCB along with the bus port connectors. The connectivity test is carried out to ensure the circuit is flawless.

3.2 Software Implementation




[1] H. Alrutz, B. Butera, K. Caesar, F. Lebowsky, S. Rohrer, and G. Stoffel, A SINGLE CHIP VIDEO FRONT END DECODER, ITT Intermetall Freiburg, Germany, 1993.

[2] Application Note: AN10, Digital Creation Labs Incorporated 2004, RETRIEVED FROM

[3] C. Poynton, Digital Video and HDTV Algorithms and Interfaces, Elsevier Science (USA), 2003.

[4] Poynton, Charles, Digital video and HDTV algorithms and interfaces, San Francisco: Morgan Kaufmann, 2003.

[5] L. STENGER, Digital Comb-Filter Demodulation of PAL Color-Television Signals, IEEE Transactions On CommunicationS, VOL. COM-27, NO. 10, October 1979

[6] K. Jack, Video Demystified, A Handbook for the Digital Engineer, Elsevier Inc., 2005

[7] J. Watkinson, The Engineers Guide to Decoding & Encoding, Snell & Wilcox Ltd, 1994.

[8] J. WANG, Y.i SONG, Hardware Design of Video Compression System in the UAV Based on the ARM Technology,

[9] Poz, Cortelazzo and Manduch, An Improved Quality PAL Decoder, IEEE Transactions on Consumer Electronics, Vol. 36, No. 3, AUGUST 1990.


[11] D G Thompson, Modern Consumer Pal Decoding Technology, The Institution of Electrical Engineers Savoy Place, London WCPR OBL, UK, 1994.

[12] Y. Suzuki, T. Gai, M. Y., and H. Sugiura, NTSC/PAL/SECAM Digital Video Decoder

with High-Precision Resamplers, IEEE Transactions on Consumer Electronics, 288 Vol. 51, No. 1, FEBRUARY 2005.

[13] R. R. Gulati, Monochrome and Colour Television, New Age International Publishers, 2005.

[14] P. Singh and S. Malik, G-143, Naraina :New Delhi-110028.

[15] J. 0. Drewery, The Clean Pal Concept And Its History, Savoy Place, London WCPR OBL. UK, The Institution of Electrical Engineers, 1994.

[16] Stephen G. LaJeunesse, Application Note, AN9644 - Composite Video Separation Techniques, IntersilTM.