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Abstract-Employing Field Programmable Gate Array (FPGA) to realize SVM can be a solution to boost system performance. Although there are a lot of literatures in application of three-phase SVM based on FPGA, but most of these are in conventional SVM and the design is complicated. This paper will present a simple approach to realize 5-segment discontinuous SVM based on FPGA, in which the judging of sectors and the calculation of the firing time is simpler and low switching losses. The proposed SVM has been successfully designed and implemented to drive on a three phase inverter system with 1.5 kW induction machine as load by using APEX20KE Altera FPGA.
Keywords: electric drives, FPGA applications, motor controls, power converters, space vector pulse width modulation (SVPWM)
The Space Vector Pulse Width Modulation (SVM) method is an advanced PWM method at which it is possibly the best among all the PWM techniques for variable frequency drive applications, since SVM can provide a better fundamental output voltage, better harmonic performance and easier be implemented [1-13]. In recent years, this method gradually obtains widespread applications in the power electronics and the electrical drives due to its superior performance characteristics. By Comparing with the Sinusoidal Pulse Width Modulation (SPWM), SVM is more suitable for digital implementation whereby the obtainable DC voltage utilization ratio can be highly increased. As the result, a better voltage total harmonic distortion factor can be obtain [1, 2, 10-12, 14]. The comparison of switching losses PL, junction temperature of the IGBT TJ, and weighted THD of the different modulation schemes are shown in Table I . From the comparison, the discontinuous SVM result in lowest switching losses and lowest junction temperature of IGBT compared with the SPWM and conventional SVM although it gives a slightly higher of weighted THD compared with conventional SVM method.
The comparison of switching losses, temperature, and weighted THD of the different modulation schemes 
Switching losses PL (per-unit of SPWM)
Weighted THD (%)
In most engineering practice, the SVM algorithm is mainly implemented using software based on microcontroller or digital signal processors (DSP) [16-18]. Designers have to perform the control procedure sequentially by exploiting their mathematically oriented resources. That is the instructions of different procedures need to be executed one after the other. Thus, the purely software-based technique is not an ideal solution. The Field Programmable Gate Array (FPGA) is an appropriate alternative over analog and software solutions (DSP and microcontroller) [19-24] and its architecture offers a significant integration density  within a flexible programmable environment. Designers can get a new degree of freedom by applying FPGA in SVM since their dedicated hardware architectures that match all the requirements in terms of control performance and implementation constraints can easily be realize . Employing of FPGA in SVM strategies provides a lot of advantages, such as: shorter design cycle, fair cost, rapid prototyping, simpler hardware and software design, and higher switching frequency. It is different from software implementation, whereby the FPGA performs the entire procedures with concurrent operation (allow parallel processing by means of hardware mode and not occupying) by using its reconfigurable hardware. With the powerful computation ability and flexibility, an FPGA is quite mature for electrical drive application and it is considered as a solution to boost system performance of a digital controller including a SVM algorithm [6, 19, 26-29].
The digital hardware FPGA-based solutions have been successfully used in many control applications, including SVM realization [6, 19, 26-29]. However, these conventional SVM suffers from the drawbacks like computational burden, inferior performance at high modulation indices and high switching losses of the inverters. Hence to reduce the switching losses and to improve the performance in high modulation region, several discontinuous SVM methods have been proposed [5, 15, 30-32].
Although in the literatures the implementation for three-phase conventional SVM and discontinuous SVM based on FPGA is not lacking, however all these designs are based on the conventional SVM without considering hardware-resource saving and complexity to implement using FPGA. In this paper, we design and implement a FPGA based SVM with a new approach, in which the judging of sectors and the calculation of the firing time to generate the SVM waveform is simple, low switching losses, and hardware-resource saving. A novel 5-segment discontinuous SVM design based on the basic idea from  and  is proposed and the scheme with lower switching losses, simpler algorithm is be implemented through APEX20KE Altera FPGA.
Novel Method of SVM Algorithm
The conventional principle of SVM algorithm which is relied on judging of sectors, firing time (duration of active vectors) calculation, and switching sequence generating method are considered too complex, so that in this work, the principle of symmetrical 5-segment discontinuous switching sequence which is not yet been revealed yet is proposed as the novel method of SVM algorithm.
Proposed SVM switching Pattern (5-segment discontinuous switching sequence)
There are lot of discontinuous SVM patterns have been reported [5, 6, 30, 31, 34]. However, these patterns performed in higher switching losses, complicate algorithm and not easy be implement based on FPGA. In this paper, a novel symmetric 5-segment discontinuous SVM is proposed and the design was referred to the basic idea from  and . The pattern has been successfully implemented by Yu based on DSP . From the result, this pattern resulted in lower switching losses, simpler algorithm and easily be implemented. Therefore, this paper will focus on implementation of discontinuous SVM pattern based on FPGA in order to boost system performance. In this proposed pattern, there is always a leg staying constant for the entire PWM period. The state sequence in this pattern is X-Y-Z-Y-X, where Z=1 in sector I, III and V, and Z=0 in the remaining sector. So, the number of switching time for this pattern is less than the conventional pattern and the obvious result is reduced in switching losses.
Proposed identification of the sector
There are lots of different methods to judge the sector that the reference space voltage vector lies in. Zhi-pu  compares the reference space vector's angle with 00, 600, 1200, 1800, 2400, and 3000 to obtain the number of the sector that the Vref in. In other references, Yu , Jiang  and Xing  obtain the sector number by analyzing the relationship between and. To determine the sector, calculation of the projections, andof andin (a,b,c) plane is needed by using inverse Clark transformation, as follow:
Then, based on equation (4), N=sign(Va) + 2*sign(Vb) + 4*sign(Vc) and map N to the actual sector of the output voltage reference by referring to the following relationship:
In , Zeliang had adopt two new intermediate vectors and whereby and . By decompose the conventional SVM, it will properly counteract the redundant calculations to identify sector location, but it result in complicated matrix calculations. In this paper, by analyzing on the principle of SVM in [7, 36-38] and to reduce burden of computation, a new method to determine the sectors of voltage vectors based on comparison between and 0 as shown in Fig. 1 is proposed. Through the comparison, sectors of voltage vectors as shown in Table I can be determine.
The plotting of wave
The proposed identification of the sectors
1: satisfy, 0: not satisfy
Determination of the duration of active vectors
The space vector technique synthesizing a desired vector Vref from two adjacent actives, VÎ± and VÎ² (among V1 and V2, as shown in Fig.1) during time interval, Ta and Tb. The null vectors (V0 and V7) are also applied to reduce the inverter switching frequency. In the proposed design, only one null vector is inserted in a PWM period, whereby V7 for odd sector and V0 for even sector.
Vref=VÎ± + jVÎ²= (5)
switching time of the active vector for each sector
Hence, the half PWM period T is composed of the switching time Ta, Tb and T0. The total time of the null vectors can be expressed as
In this design, the switching time of the active vectors for each sector can be calculated as shown in
Proposed SVM switching sequence generating method based on calculation of the duration of active vectors
In this paper, a new method of SVM switching sequence is proposed, whereby the PWM signal for odd sectors are realized through comparison between the triangle waveform with , and . High signal will be generate when the triangle waveform is higher than signal A or B, and another leg is always set to 1. While for the even sectors, the generation of PWM signal is complement with the odd sectors. Whereby signal will set high when the triangle waveform is lower than signal A or B and another one leg is set to 0.
Proposed SVM switching sequence generating method
To simplify the design process, the termwill set to 1so that y will be always equal to x (x==Ta then y= x=Ta, and if x= then y=). Obviously if x=then y=. Therefore, the generation of PWM for Sb and Sc legs in sector I can be obtained by comparing the triangle waveform with, and respectively and Sa Leg is set to 1 due the odd sector position.
FPGA Implementation of A Proposed Novel SVM
After discussed on the principle of SVM generation, this section will focus on implementation of FPGA in SVM. The overall proposed SVM design is shown in Fig. 3. From this figure, it consists of 5 blocks or modules, namely ajust_freq, Vbeta_Valfa, find_sector, SVM_generator and deadtime_sytem module. Each of these modules is explained as follow:
Overall of the proposed SVM design
First Module "ajust_freq"
From Fig. 3, the function of ajust_freq is to generate a suitable clocking frequency. Whereby in this proposed SVM design, this module work as a frequency divider by generating a carrier frequency of 20 kHz and a fundamental frequency of 50 Hz from the FPGA board which have a clocking signal of 33.33Mhz. Since the triangle signal generator in this design is sampled to be 32 times per period, hence in order to get a 20kHz of carrier frequency, the main clock generator from FPGA board need to be divided by 13 (33.33MHz:(13 x32 )=20kHz).
Second Module "Vbeta_Valfa"
In this research, Valfa and Vbeta are generated based on sine and cosine functions through the look up table (LUT) with memory mapping of 360 addresses. There have three lines which categories as lower, base and upper that represented with 96, 224 and 352 respectively into 9 unsigned bits. With the memory mapping of 360 addresses, the counter mod-360 will used to count LUT of Valfa and Vbeta.
Third Module "find_sector"
Due to the different of switching time equations, a reference voltage sector is necessary. The SF (sector finder) module in this design is used to judging on the reference vector sector by referring to Table 2. This module determines the number of sectors and simplifies the truth table by comparing the results above.
Fourth Module "SVM_generator"
This module was divided into 4 sub modules, namely Triangle, Duration_Ta, Duration_TaTb, and SVM pattern module. Triangle module is functioned as triangle signal generator. In this proposed SVM design, one period of triangle signal generator is sampled into 32 times, and is represented in the digital number of 9 unsigned bit, with lower (in this case is same with base number) and upper number each are 224 and 352 respectively. For the Duration_Ta and Duration_TaTb module, these modules are digital solution for each second and fourth column respectively. Lastly, the SVM pattern module is used to generate the SVM sequence as described in section II.D.
Fifth Module "deadtime_system"
A dead-time of at least 2 ms is required to avoid short circuit within a leg. Pair of 16-bits counter and 16 bits comparator is used to construct the dead time generator for each leg.
Results and Discussions
In this research, the proposed SVM generator design with different carrier frequencies were successfully been carried out by using APEX20KE Altera FPGA. Fig. 4 shows the results from hardware implementation with this proposed SVM generating method at carrier frequency of 20 kHz. The probe 1, 2 and 3 in Fig. 4 (a) and (b) are represented as switching state of Sa, Sb, and Sc respectively, whereby the probe M is (Sa+Sb) line-to-line switching state and with its frequency spectrum. The harmonics due to the 20 kHz switching frequency are clearly visible in Fig. 4 (b).
The similar condition is shown in Fig. 5. In this case, carrier frequency is set to 40 kHz; although the result in Fig. 5 (b) showed a 38.5 kHz (an error of 3.75%). A three phase inverter system together with an induction machine of 1.5 kW is used to test on the performance for the proposed SVM generator based FPGA design.
Fig. 6 shows the practical result for output stator current (Ia), output phase-to-phase voltage (Vab), frequency spectrum, output three phase current and output voltage line-to-neutral (Van). From the results, it showed that this proposed SVM generator based FPGA design is successful be implemented in through hardware platform.
(a) the switching state and its line-to-line
(b) The signal gating and its frequency spectrum
Hardware implementation of proposed SVM generator at carrier frequency 20 kHz.
(a) the switching signals and line-to-line switching
(b) The signal gating and its frequency spectrum
Hardware implementation of proposed SVM generator at carrier frequency 40 kHz.
Output current Ia
Output voltage Vab
(a) output current and voltage
(c) output three phase current
Output current Ia
Output voltage Vab
(b) frequency spectrum
Output voltage line-to-neutral (Van)
(d) output voltage line-to-neutral
The performance of FPGA based proposed SVM generator design.
Further, the comparison of current and voltage THD between the proposed SVM and other SVM is shown
Table IV. From the table, proposed SVM shown a low percentage in current and voltage THD compared with other SVM.
Comparison of current and voltage THD between the proposed SVM and other SVM
Current THD (%)
Voltage THD (%)
Proposed SVM based on FPGA
Rising-edge aligned sequence scheme (SVM1)
Falling-edge aligned sequence scheme (SVM2)
Symmetric aligned sequence scheme (SVM3)
Alternative sequence scheme (SVM4)
Three-zone hybrid PWM
Five-zone hybrid PWM
Seven-zone hybrid PWM
Hybrid Type I
Hybrid Type IV
This paper mainly presents the design and realization of a simple 5-segment discontinuous SVM based on the application of FPGA. The judging of sectors and the calculation of the firing time to generate the SVM waveform become simpler, and switching losses can also be reduce by using this new approach of SVM base FPGA design. The proposed SVM scheme has been successfully designed and implemented by using APEX20KE Altera FPGA without compute the number and angles of each sector as well as the commutation pattern. A three phase inverter system loaded by an induction machine with1.5 kW is successful drive by the proposed design by using a carrier frequency up to 40 kHz. Results have proved that by employing FPGA in SVM provides advantages such as: shorter design cycle, simpler hardware and software design, higher switching frequency and reduce in switching losses.