Power electronic converters and pulse width modulation inverters

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Power electronic converters are a family of electrical circuits which convert electrical energy from one level of voltage/current/frequency to another using semiconductor-based electronic switch. The essential characteristic of these types of circuits is that the switches are operated only in one of two states - either fully ON or fully OFF - unlike other types of electrical circuits where the control elements are operated in a linear active region.

As the power electronics industry has developed, various families of power electronic converters have evolved, often linked by power level, switching devices, and topological origins. Application areas of power converters got huge improvements in semiconductor technology, which offer higher voltage and current ratings as well as better switching characteristics. On the other hand, the main advantages of modem power electronic converters, such as high efficiency, low weight, small dimensions, fast operation, and high power densities.

The process of switching the electronic devices in a power electronic converter from one state to another is called 'modulation'. Each family of power converters has preferred modulation strategies associated with it that aim to optimize the circuit operation for the target criteria most appropriate for that family. Parameters such as switching frequency, distortion, losses, harmonic generation, and speed of response are typical of the issues which must be considered when developing modulation strategies for a particular family of converters [1].

In modern converters, PWM is a high- speed process ranging depending on the rated power from a few kilohertz (motor control) up to several megahertz (resonant converters for power supply). Therefore firstly we discuss about the principle and different topologies regarding PWM.


The Pulse width modulated (PWM) inverters are among the most used power-electronic circuits in practical applications. These inverters are capable of producing ac voltages of variable magnitude as well as variable frequency. The quality of output voltage can also be greatly enhanced, when compared with those of square wave inverters. The PWM inverters are very commonly used in adjustable speed ac motor drive loads where one needs to feed the motor with variable voltage, variable frequency supply. For wide variation in drive speed, the frequency of the applied ac voltage needs to be varied over a wide range. The applied voltage also needs to vary almost linearly with the frequency. PWM inverters can be of Single phase as well as three phase types. Their principle of operation remains similar. [2]

Principle of Pulse Width Modulation (PWM):

The dc input to the inverter is chopped by switching devices in the inverter. The amplitude and harmonic content of the ac waveform is controlled by the duty cycle of the switches. The fundamental voltage v1 has max. Amplitude = 4Vd/p for a square wave output but by creating notches, the amplitude of V1 is reduced.

Usually, the ON and OFF states of the power switches in one inverter leg are always opposite. Therefore, the inverter circuit can be simplified into three 2-position switches. Either the positive or the negative dc bus voltage is applied to one of the motor phases for a short time. Pulse width modulation (PWM) is a method whereby the switched voltage pulses are produced for different output frequencies and voltages. A typical modulator produces an average voltage value, equal to the reference voltage within each PWM period. Considering a very short PWM period, the reference voltage is reflected by the fundamental of the switched pulse pattern. [3]

There are several different PWM techniques, differing in their methods of implementation. However in all these techniques the aim is to generate an output voltage, which after some filtering, would result in a good quality sinusoidal voltage waveform of desired fundamental frequency and magnitude. For the inverter topology considered here, it may not be possible to reduce the overall voltage distortion due to harmonics but by proper switching control the magnitudes of lower order harmonic voltages can be reduced, often at the cost of increasing the magnitudes of higher order harmonic voltages. Such a situation is acceptable in most cases as the harmonic voltages of higher frequencies can be satisfactorily filtered using lower sizes of filters and capacitors. Many of the loads, like motor loads have an inherent quality to suppress high frequency harmonic currents and hence an external filter may not be necessary. To judge the quality of voltage produced by a PWM inverter, a detailed harmonic analysis of the voltage waveform needs to be done [2].

In fact, after removing 3rd and multiples of 3rd harmonics from the pole voltage waveform one obtains the corresponding load phase voltage waveform. The pole voltage waveforms of 3-phase inverter are simpler to visualize and analyze and hence the harmonic analysis of load phase and line voltage waveforms is done via the harmonic analysis of the pole voltages. It is implicit that the load phase and line voltages will not be affected by the 3rd and multiples of 3rd harmonic components that may be present in the pole voltage waveforms.

Nature of Pole Voltage Waveforms Output By PWM Inverters:

Unlike in square wave inverters the switches of PWM inverters are turned on and off at significantly higher frequencies than the fundamental frequency of the output voltage waveform. The typical pole voltage waveform of a PWM inverter is shown in . 1 over one cycle of output voltage. In a three-phase inverter the other two pole voltages have identical shapes but they are displaced in time by one third of an output cycle. Pole voltage waveform of the PWM inverter changes polarity several times during each half cycle. The time instances at which the voltage polarities reverse have been referred here as notch angles. It may be noted that the instantaneous magnitude of pole voltage waveform remains fixed at half the input dc voltage (Edc). When upper switch (SU), connected to the positive dc bus is on, the pole voltage is + 0.5 Edc and when the lower switch (SL), connected to the negative dc bus, is on the instantaneous pole voltage is - 0.5 Edc. The switching transition time has been neglected in accordance with the assumption of ideal switches. It is to be remembered that in voltage source inverters, meant to feed an inductive type load, the upper and lower switches of the inverter pole conduct in a complementary manner. That is, when upper switch is on the lower is off and vice-versa. Both upper and lower switches should not remain on simultaneously as this will cause short circuit across the dc bus. On the other hand one of these two switches in each pole (leg) must always conduct to provide continuity of current through inductive loads. A sudden disruption in inductive load current will cause a large voltage spike that may damage the inverter circuit and the load.

The following are some major concerns when comparing different PWM techniques:

* Good utilization of DC power supply, that is to deliver a higher output voltage with the same DC supply;

* Good linearity in voltage and or current control;

* Low harmonics contents in the output voltage and or currents, especially in the low-frequency region;

* Low switching losses.

There are several other PWM techniques, the important ones are:-


In many industrial applications, sinusoidal Pulse width modulation (SPWM), also called sine coded pulse width modulation, is used to control the inverter output voltage. SPWM maintains good performance of the drive in the entire range of operation between zero and 78 percent of the value that would be reached by square wave operation. If the modulation index exceeds this value, linear relationship between modulation index and output voltage is not maintained and the over-modulation methods are required.

Sinusoidal PWM refers to the generation of PWM outputs with sine wave as the modulating signal. The ON and OFF instants of a PWM signal in this case can be determined by comparing a reference sine wave (the modulating wave) with a high frequency triangular wave (the carrier wave) as shown in . 3. Sinusoidal PWM technique is commonly used in industrial applications and is abbreviated here as SPWM. The frequency of the modulating wave determines the frequency of the output voltage. The peak amplitude of modulating wave determines the modulation index and in turn controls the RMS value of output voltage. The RMS value of the output voltage can be varied by changing the modulation index. This technique improves distortion factor significantly compared to other ways of multi-phase modulation. It eliminates all harmonics less than or equal to 2p-1, where "p" is defined as the number of pulses per half cycle of the sine wave. The output voltage of the inverter contains harmonics. However, the harmonics are pushed to the range around the carrier frequency and its multiples.

fs = frequency of pulse width modulation (triangular wave)

f1 = frequency of fundamental wave (control wave))

The pole voltage VA0 is +Vdc/2, when Vcontrol > Vtri and -Vdc/2 when Vcontrol < Vtri. The line voltage VAB= VAO-VBO

Amplitude modulation ratio (ma):

Frequency modulation ratio (mf):

Ø mf should be an odd integer

* if mf is not an integer, there may exist sub harmonics at output voltage

* if mf is not odd, DC component may exist and even harmonics are present at output voltage

Ø mf should be a multiple of 3 for three-phase PWM inverter

* An odd multiple of three and even harmonics are suppressed.

The advantages of SPWM for the converter application are drawing sinusoidal line currents with low harmonic contents, high power factor, dc link voltage regulation, and possible bidirectional power flow [ ].

Ranjan K. Behera at al., [ ] presented generalized analytical solutions for different multilevel pulse width modulations strategies like In-phase Sinusoidal Pulse Width Modulations (IPSPWM), Phase Opposite Sinusoidal Pulse Width Modulation (POSPWM) and dipolar modulation techniques for three-level NPC inverter. They identified that IPSPWM has a superior spectral performance compared to other two modulation schemes.

Giuseppe Carrara et al., [ad] analyzed the multilevel modulation processes with a powerful and mathematically rigorous method that provides the analytical expressions of the output phase voltages of the inverter. The improvements in the harmonic contents due to the increased number of levels were highlighted. However, several considerations on the actual structure of the inverter and on the system in which it has to be employed should be done case by case to determine the practical convenience of this solution. On the other hand it is worth noting that the multilevel approach is the only permissible when both reduced harmonic contents and high power are required.

Lazhar Ben-Brahim at al., [ ] described a new PWM control methods based on 1) adding a bias to the reference, and 2) switching pattern for GTO minimum on-pulse compensation which improved the output waveforms without increasing the switching losses. These methods had contributed to the improvement of the characteristics of a GTO based NPC inverter.

Adrian Schiop [ ] presented a method based on the sinusoidal PWM for modeling and simulation of the single-phase diode clamped multilevel inverters and capacitor clamped multilevel inverters. The models presented are used to perform a harmonic analysis of the output voltage of these multilevel inverters.

P. K. Chaturvedi at al., [ ] investigated the concepts of sinusoidal pulse width modulation, optimized harmonic stepped waveform, and selective harmonic elimination techniques. These techniques considerably reduced the lower order harmonics in three phase three-level and five-level diode clamped inverters.

Joachim [ ] evaluated the state of the art in pulse width modulations for ac drives fed from three-phase voltage source inverters. He described feed forward and feedback pulse width modulation schemes for industrial applications and described secondary effects such as transients in synchronized pulse width modulation schemes and adequate compensation methods.


The SVPWM method is an advanced, computation intensive PWM method and is possibly the best among all the PWM techniques for variable frequency drive applications. Because of its superior performance characteristics, it has been finding wide spread application in recent years.


The space vector pulse width modulation (SVPM) technique is more popular than conventional technique because of the following excellent features:

* It achieves the wide linear modulation range associated with PWM, third-harmonic injection automatically.

* It has lower base band harmonics than regular PWM or other sine based modulation methods, or otherwise optimizes harmonics.

* 15% more output voltage then conventional modulation, i.e. better DC-link utilization.

* More efficient use of dc supply voltage

* SVM increases the output capability of SPWM without distorting line-line output voltage waveform.

* Advanced and computation intensive PWM technique.

* Higher efficiency.

* Prevent un-necessary switching hence less commutation losses.

* A different approach to PWM modulation based on space vector representation of the voltages in the α-β plane.

F. Profumo et al., [ac] focused a general overview of the SPWM and SVPWM techniques. Particular emphasis has been done on PWM problems due to the secondary effects. The complete analysis and the obtained simulation results have been reported. The sinusoidal PWM waveforms have cleaner spectra than the space vector PWM, but the quality factors are higher with respect to the space vector PWM having the same peak value of the voltage reference. As a consequence, if the switching frequency is high enough, the losses due to the harmonics can be almost neglected, and the Space Vector PWM seems to be the best solution in terms of output voltage, harmonic losses and number of switching per cycle.

Zhenyu Yu at al., [ ] described and reviewed the three commonly used PWM techniques, sinusoidal PWM technique, space vector PWM techniques and hysteresis PWM techniques. They implemented these techniques with digital processor such as TMS320C240 and presented the better utilization of DC supply and reduction of harmonics of space vector PWM vs. sinusoidal PWM.

Keliang Zhou at al., [ ] investigated the relationship between the carrier-based PWM and space-vector modulation. They described the relationships between the modulation signals (include fundamental signals and zero-sequence signal) and space vectors, between the modulation signals and space-vector sectors, and between the switching pattern of space-vector modulation and the type of carrier.

Abdul Hamid Bhat et al., [ab] described an improved performance three phase, neutral-point clamped bidirectional rectifier with simplified control scheme. A complete mathematical model of the rectifier using PWM controller is developed. A comparative analysis of two-level and three-level converter is evaluated. They discussed the merits and demerits of both types of converters.

Variable voltage and frequency supply to ac drives is invariably obtained from a three-phase voltage source inverter (VSI). A number of Pulse width modulation (PWM) schemes are used to obtain variable voltage and frequency supply. AtifIqbal et al., [bb] presented a step by step development of Matlab/Simulink model to implement SVPWM for three phase VSI. A brief review of VSI model is also reported based on space vector representation.

Jang-Hwan Kim at al [ ] analyzed the relationship between the space vector PWM and the carrier-based PWM method, and they proposed a novel carrier-based PWM strategy to balance the neutral point potential. They analytically described the voltage error of the modulation caused by the unbalance of the neutral point potential.


The concept of space vector is derived from the rotating field of AC machine which is used for modulating the inverter output voltage. In this modulation technique the three phase quantities can be transformed to their equivalent two-phase quantity either in synchronously rotating frame (or) stationary frame. From this two-phase component the reference vector magnitude can be found and used for modulating the inverter output. The process of obtaining the rotating space vector is explained in the following section, considering the stationary reference frame.

2.3.1 Principle of Space Vector PWM

The SVPWM treats the sinusoidal voltage as a constant amplitude vector rotating at constant frequency. This PWM technique approximates the reference voltage Vref by a combination of the eight switching patterns (V0 to V7). A three-phase voltage vector is transformed into a vector in the stationary d-q coordinate frame which represents the spatial vector sum of the three-phase voltage.

2.4 Space Vector PWM for two level INVERTER:

The circuit model of a typical three-phase voltage source PWM inverter is shown in .2.2. S1 to S6 are the six power switches that shape the output, which are controlled by the switching variables a, a′, b, b′, c and c′. When an upper transistor is switched ON, i.e., when a, b or c is 0 the corresponding lower transistor is switched OFF, and when a′, b′ or c′ is 1 the corresponding upper transistor is switched OFF. Therefore, the ON and OFF states of the upper transistors S1, S3 and S5 can be used to determine the output voltage.

As illustrated in .2.2, there are eight possible combinations of ON and OFF patterns for the three upper power switches. The ON and OFF states of the lower power devices are opposite to the upper one and so are easily determined once the states of the upper power transistors are determined.

To implement the space vector PWM, the voltage equations in the abc reference frame can be transformed into the stationary d-q reference frame that consists of the horizontal (d) and vertical (q) axes as depicted in . 2.3

As described in . 2.3, this transformation is equivalent to an orthogonal projection of [a, b, c] onto the two-dimensional perpendicular to the vector [1, 1, 1] (the equivalent d-q plane) in a three-dimensional coordinate system. As a result, six non-zero vectors and two zero vectors are possible. Six nonzero vectors (V1 - V6) shape the axes of a hexagonal as depicted in 2.4 and feed electric power to the load. The angle between any adjacent two non-zero vectors is 60 degrees. Meanwhile, two zero vectors (V0 and V7) are at the origin and apply zero voltage to the load. The eight vectors are called the basic space vectors and are denoted by V0, V1, V2, V3, V4, V5, V6, and V7. The same transformation can be applied to the desired output voltage to get the desired reference voltage vector Vref in the d-q plane. The objective of space vector PWM technique is to approximate the reference voltage vector Vref using the eight switching patterns. One simple method of approximation is to generate the average output of the inverter in a small time period T, to be same as that of Vref in the same time period.

2.5 DETERMINATION OF Switching States

Let us consider a state say V0.This state at which all of the upper devices are in the ON position. So in this state all of the gate pulses are given to the upper devices of the inverter circuit, i.e., S1, S3, S5. So the resultant output voltage will be zero. The wave form will be at the zero level. This can be illustrated as shown in the below .2.5.

So from the above ure all the three upper switches are in the ON state and the lower ones are in the OFF state. Similarly all the other states can be represented in the diagrammatical manner as shown .2.6

STATE 1: (1 0 0)

, ,

STATE 2: (1 1 0)


STATE 3: (0 1 0)

, ,

STATE 4: (0 1 1)

, ,

STATE 5: (0 0 1)

, ,

STATE 6: (1 0 1)

, ,

STATE 7: (1 1 1)

, ,

STATE 8: (0 0 0)

, ,

Representing all the above mentioned eight voltage vectors in space, the SVPWM for two level inverter is built. The space vector locations for a two-level inverter form the vertices of a regular hexagon, forming 6 sectors as shown in . 2.7. For the states (000) and (111) the motor phases are short-circuited and therefore are not connected to the source. These states are called the Zero states or null states during which there is no power flow from the source to the motor. Hence, by controlling the duration of these zero state intervals, one can control the magnitude of the output-voltage. It is worth noting that in six-state mode of operation, such intervals of zero state switching do not exist. Consequently, controlling the input DC link voltage controls the magnitude of the output voltage in an inverter operating in a square wave mode. The rest of the vectors 1 through 6 are called the active vectors.

2.6 Calculation of switching times

Switching times of the SVPWM based inverter can be calculated by using volt-sec relation. .2.8 represents the calculation based on the voltage-sec relation of the reference vector Vsr. The volt-seconds produced by the vectors V1, V2 and V7 orV0 along d and q axes are the same as those produced by the reference vector Vsr.

2.7 Optimized Switching Sequence

In order to minimize the number of switching in the inverter, the following optimized switching pattern is selected [15].




(ON sequence)


(OFF sequence)
























Upper switches

(S1, S3,S5)

Lower switches



S1 = T1 + T2 + T0 /2

S3 = T2 + T0 /2

S5 = T0 /2

S4 = T0 /2

S6 = T1 + T0 /2

S2 = T1 + T2 + T0 /2


S1 = T1 + T0 /2

S3 = T1 + T2 + T0 /2

S5 = T0 /2

S4 = T2 + T0 /2

S6 = T0 /2

S2 = T1 + T2 + T0 /2


S1 = T0 /2

S3 = T1 + T2 + T0 /2

S5 = T2 + T0 /2

S4 = T1 + T2 + T0 /2

S6 = T0 /2

S2 = T1 + T0 /2


S1 = T0 /2

S3 = T1 + T0 /2

S5 = T1 + T2 + T0 /2

S4 = T1 + T2 + T0 /2

S6 = T2 + T0 /2

S2 = T0 /2


S1 = T2 + T0 /2

S3 = T0 /2

S5 = T1 + T2 + T0 /2

S4 = T1 + T0 /2

S6 = T1 + T2 + T0 /2

S2 = T0 /2


S1 = T1 + T2 + T0 /2

S3 = T0 /2

S5 = T1 + T0 /2

S4 = T0 /2

S6 = T1 + T2 + T0 /2

S2 = T2 + T0 /2

Space Vector PWM is considered a better technique of PWM implementation owing to its associated advantages mentioned below

* better fundamental output voltage

* better harmonic performance

* Easier implementation in Digital Signal Processor and Microcontrollers.

The two-level inverters are having certain drawbacks.

* These are not suitable for high power levels.

* High DC link voltage requires series connection of devices.

* Difficult in dynamic voltage during switching.

Multi-level topology has been applied in several situations, such as high voltage AC drive, FACTS, SVC and so on. Multi-level topology has advantages over traditional two-level topology as following:

* The voltage blocked by the power device is decreased tremendously,

* Multilevel inverters produce low harmonic distortion for ac currents even when operated at moderate switching frequency.

* The switch losses are lower than two-level inverters.


Multilevel inverter technology has emerged recently as a very important alternative in the area of high-power medium-voltage energy control. And the Main features of multi level inverter are

* Ability to reduce the voltage stress on each power device due to the utilization of multiple levels on the DC bus

· Important when a high DC side voltage is imposed by an application (e.g. traction systems)

· Even at low switching frequencies, smaller distortion in the multilevel inverter AC side waveform can be achieved (with stepped modulation technique)

Jae Hyeong Seo at al., [ ] proposed new simplified space-vector pulse width modulation (SVPWM) method for three-level inverter based on the simplification of the space-vector diagram of a three-level inverter into that of a two-level inverter the remaining procedures necessary for the three-level SVPWM are done like conventional two-level inverter. They developed three-level IGBT inverter system was applied to the steel making factory of Pohang Steel Corporation (POSCO).

H. Pinheiro at al., [ ] described a unified approach of the space vector modulations for voltages source inverters and applied to single-phase full-bridge, three-phase three-wire, three-phase four-wire, three-phase four-leg and three-phase three-level inverters. Switching vectors, separation and boundary planes in the inverter output space as well as decomposition matrices and possible switching sequences are derived.

A. Koochaki at al., [ ] proposed a single phase application of space vector pulse width modulation for shunt active power filters. In conventional SVPWM, all of the phase's currents are controlled together, but in this method, they controlled each of phase currents independently from the measured currents of other phases and they demonstrated that proposed method has good performance in generation of all types of compensation currents by active power filters.

Zeliang Shu at al., [ ] developed a compact algorithm of space vector pulse width modulation for three-phase inverter. The conventional SVPWM is decomposed in to fast integer operations entirely by using an intermediate vector, which will properly counteract the redundant calculations of the remaining procedures. This has examined only in two level inverter applications.

Subrata K. Mondal at al., [ ] proposed the space vector PWM algorithm for a three-level voltage-fed inverter has been extended to over modulation range thy proposed that the over modulation strategy easily blends with the under modulation algorithm so that the inverter can operate smoothly from low speed to the extended speed range.

A significant problem with neutral-point-clamped three-level inverters is the fluctuation in the neutral point voltage. Rangarajan at al., [ ] developed capacitor voltage balancing technique for carrier-based three-level PWM. It was shown that the method is applicable to both dipolar and unipolar modes, and that the inverter outputs characteristic three-level waveforms even in voltage correction mode.

Prasad N. Enjeti at al., [ ] utilized the switching function approach to derive relevant analytical expressions for input/output variables. They proposed optimal power control strategies for an NPC inverter employing programmed PWM patterns. With the proposed PWM pattern, the frequency of the first significant harmonic component at the inverter output is at least 3 p.u. for a switching frequency of 1 p.u.

R. Sommer at al., [ ] presented a new range of medium voltage motor drives with a three-level neutral point clamped inverter using high voltage IGBTs. Their control is based on field-oriented vector control and an optimized PWM modulator, so that switching losses and current harmonics are minimized and efficiency is optimized.

Satoshi Ogasawara at al., [ ] analyzed the neutral point potential variation of the NPC voltage source PWM inverter for ac motor drives and static var compensations, with the focus on the current flowing out of or in to the neutral point of dc link.

Generally, the balancing of the DC-link voltage degrades at very low operating frequencies of the inverter. Most proposed methods of neutral point balancing techniques result in an increase of the switching losses of the inverter. To solve this problem, Lazhar Ben-Brahim [ ] proposed a new energy saving PWM method which results in a significant reduction of the fluctuation of the neutral point voltage of NPC inverters. That method incorporated techniques to the inherent minimum ON-OFF pulse width limitation in a GTO without increasing the switching losses of the devices.

Imbalance of the neutral-point potential in three-level neutral point-clamped converter may appear in some operating conditions. Jan-Hwan Kim at al., [ ] analyzes the voltage distortion caused by the imbalance of the neutral point potential in a three-level neutral-point-clamped converter, and also describe the PWM method to generate the low-frequency harmonics-free output voltages even under the imbalanced condition. In the proposed method they used the three voltage vectors near to the reference vector, which has advantages in terms of the high-frequency harmonics reference vector are used.

Ramon C. Portillo at al., [ ] described an analytical strategy to model a back-to-back three-level converter. And different incorporated to the overall model. This model pays special attention to the unbalance in the capacitors voltage of three-level converters, including the dynamics of the capacitors voltage.

Zeliang Shu at al., [ ] developed a compact algorithm of space vector pulse width modulation for three-phase inverter. The conventional SVPWM is decomposed in to fast integer operations entirely by using an intermediate vector, which will properly counteract the redundant calculations of the remaining procedures. This has examined only in two level inverter applications.

S. Brovanov at al., [ ] described a SVPWM feed forward technique that taken in to account the DC voltage unbalance. They showed that duty cycle of space vector have taken limitations that depends on the value of the unbalance DC voltage.

There are three main topologies for multi level inverter




Panagiotis Panagis at al., [ ] performed a comparison between existing state of the art multilevel inverter topologies. The topologies examined are the Neutral Point Clamp Multilevel inverter (NPCMLI) or Diode-Clamped Multilevel Inverter (DCMLI), the Flying Capacitor Multilevel Inverter (FCMLI) and the Cascaded Cell Multilevel Inverter (CCMLI). They compared of these inverters is based on the criteria of output voltage quality (Peak value of the fundamental and dominant harmonic components and THD), power circuitry complexity, and implementation cost.


Diode-clamped multilevel inverter (DCMI) is an Extension of neutral point clamped, and it is based on concept of using diodes to limit power devices voltage stress Structure and basic operating principle Consists of series connected capacitors that divide DC bus voltage into a set of capacitor voltages

* A DCMI with n number of levels typically comprises (n-1) capacitors on the DC bus.

* Voltage across each capacitor is VDC/(n -1)

(N nodes on DC bus, n levels of output phase voltage, (2n -1) levels of output line voltage)

* Output phase voltage can assume any voltage level by selecting any of the nodes.

* DCMI is considered as a type of multiplexer that attaches the output to one of the available nodes.

* Consists of main power devices in series with their respective main diodes connected in parallel and clamping diodes.

* Main diodes conduct only when most upper or lower node is selected.

* Although main diodes have same voltage rating as main power devices, much lower current rating is allowable.

* In each phase leg, the forward voltage across each main power device is clamped by the connection of diodes between the main power devices and the nodes.

* Number of power devices in ON state for any selection of node is always equal to(n -1).

For example three-phase six-level diode-clamped inverter is shown in ure 1. Each of the three phases of the inverter shares a common dc bus, which has been sub divided by five capacitors into six levels. The voltage across each capacitor is Vdc, and the voltage stress across each switching device is limited to Vdc through the clamping diodes. Table 31.1 lists the output voltage levels possible for one phase of the inverter with the negative dc rail voltage V0 as a reference. State condition 1 means the switch is on, and 0 means the switch is off. Each phase has five complementary switch pairs such that turning on one of the switches of the pair require that the other complementary switch be turned off. The complementary switch pairs for phase leg 'a' are (Sa1, Sa'1), (Sa2, Sa'2), (Sa3, Sa'3), (Sa4, Sa'4), and (Sa5, Sa'5). Table 1 also shows that in a diode-clamped inverter, the switches that are on for particular phase legs are always adjacent and in series. For a six-level inverter, a set of five switches is on at any given time.

Voltage Vao

Switching states











V5 = 5Vdc











V4 = 4Vdc











V3 = 3Vdc











V2 = 2Vdc











V1 = 1Vdc











Vo = 0











Table 1. Diode-clamped six-level inverter voltage levels and corresponding switching states

· General features

* For three-phase DCMI, the capacitors need to filter only the high-order harmonics of the clamping diodes currents, low-order components intrinsically cancel each other.

* For DCMI employing step modulation strategy, if n is sufficiently high, filters may not be required at all due to the significantly low harmonic content.

* Ifeach clamping diode has same voltage rating as power devices, for n-level DCMI.

* Number of clamping diodes/phase = (n-1) x (n-2).

* Each power device blocks only a capacitor voltage.

· Advantages:

* All of the phases share a common dc bus, which minimizes the capacitance requirements of the converter. For this reason, a back-to-back topology is not only possible but also practical for uses such as a high-voltage back-to-back inter-connection or an adjustable speed drive.

* The capacitors can be pre-charged as a group.

* Efficiency is high for fundamental frequency switching.

· Disadvantages:

* Real power flow is difficult for a single inverter because the intermediate dc levels will tend to overcharge or discharge without precise monitoring and control.

* The number of clamping diodes required is quadratically related to the number of levels, which can be cumbersome for units with a high number of levels.

After general description of all famous solutions, the focus is paid on Diode Clamped Multilevel Inverters (DCMI) and Flying Capacitor Multilevel Inverters (FCMI). The comparison of topological structure differences and control strategies were presented by Oleg Sivkov at al., [ ]. The special focus is paid to balancing of voltages on capacitors. Switching states and their transitions of three-level inverter allow balancing the capacitor voltages in both types of inverters. The advantages and disadvantages of DCMI and FCMI are compared for the same output power.


Flying capacitor multi level inverter is Capable of solving capacitor voltage unbalance problem and excessive diode count requirement in diode capacitor multi level inverter and it is also known as flying capacitor multilevel inverter (capacitors are arranged to float with respect to earth). Structure and basic operating principle of flying capacitor multi level inverter are

* Employs separate capacitors pre-charged to [(n-1) / (n-1) x VDC], [(n-2) / (n-1) x VDC] ... {[n-(n-1)] / [n-1] x VDC}

* Size of voltage increment between two capacitors defines size of voltage steps in flying capacitor multi level inverter output voltage waveform

* n-level flying capacitor multi level inverter has n levels output phase voltage and (2n-1) levels output line voltage

* Output voltage produced by switching the right combinations of power devices to allow adding or subtracting of the capacitor voltages

For example the three phase six-level flying capacitor multi level inverter is shown in ure 2, the structure of this inverter is similar to that of the diode-clamped inverter except that instead of using clamping diodes, the inverter uses capacitors in their place.

This topology has a ladder structure of dc side capacitors, where the voltage on each capacitor differs from that of the next capacitor.

§ General features:

* With step modulation strategy, with sufficiently high n, harmonic content can be low enough to avoid the need for filters.

* Advantage of inner voltage levels redundancies - allows preferential charging or discharging of individual capacitors, facilitates manipulation of capacitor voltages so that their proper values are maintained.

* Active and reactive power flow can be controlled.

* Additional circuit required for initial charging of capacitors.

§ Advantages:

* Phase redundancies are available for balancing the voltage levels of the capacitors.

* Real and reactive power flow can be controlled.

* The large number of capacitors enables the inverter to ride through short duration outages and deep voltage sags.

§ Disadvantages:

* Control is complicated to track the voltage levels for all of the capacitors. Also, pre-charging all of the capacitors to the same voltage level and startup are complex.

* Switching utilization and efficiency are poor for real power transmission. The large numbers of capacitors are both more expensive and bulky than clamping diodes in multilevel diode-clamped converters. Packaging is also more difficult in inverters with a high number of levels.


It referred to Modular structured multilevel inverter (MSMI) or series connected H-bridge inverters, Structure and basic operating principle of cascade H-Bridge multi level inverter Consists of (n-1)/2 or h number of single-phase H-bridge inverters (MSMI modules) i.e..,

MSMI output phase voltage is

V0 = Vm1 + Vm2+ ........ +Vmh

Vm1: output voltage of module 1

Vm2: output voltage of module 2

Vmh: output voltage of module h

A single-phase structure of an m-level cascaded inverter is illustrated in ure 3. Each separate dc source (SDCS) is connected to a single-phase full-bridge, or H-bridge, inverter. Each inverter level can generate three different voltage outputs, +Vdc, 0, and -Vdc by connecting the dc source to the ac output by different combinations of the four switches, S1, S2, S3, and S4. To obtain +Vdc, switches S1 and S4 are turned on, whereas -Vdc can be obtained by turning on switches S2 and S3. By turning on S1 and S2 or S3 and S4, the output voltage is 0. The ac outputs of each of the different full-bridge inverter levels are connected in series such that the synthesized voltage waveform is the sum of the inverter outputs. The number of output phase voltage levels m in a cascade inverter is defined by m = 2s+1, where s is the number of separate dc sources.

§ Advantages:

· The number of possible output voltage levels is more than twice the number of dc sources (m = 2s + 1).

· The series of H-bridges makes for modularized layout and packaging. This will enable the manufacturing process to be done more quickly and cheaply.

§ Disadvantages:

· Separate dc sources are required for each of the H-bridges. This will limit its application to products that already have multiple SDCSs readily available.

M.G. Hosseini Aghdam at al., [ ] proposed Homotopy algorithm to solve the non linear transcendent equations which are formed to find switching angles of the devices in a cascaded H-bridge multi-level inverter with unequal DC sources, in order to eliminate some selected harmonics from the output voltage. The proposed algorithm is very effective, efficient and reliable in finding solutions to high-order nonlinear equations and solves the nonlinear transcendent equations with a much simpler formulation. Computer simulations based on a seven-level cascaded H-bridge inverter have been provided for the verification.

4. Other Multilevel Inverter Structures:

Besides the three basic multilevel inverter topologies previously discussed, other multilevel converter topologies have been proposed; however, most of these are "hybrid" circuits that are combinations of two of the basic multilevel topologies or slight variations to them. Additionally, the combination of multilevel power converters can be designed to match with a specific application based on the basic topologies.

A. Generalized Multilevel Topology

Existing multilevel converters such as diode-clamped and capacitor-clamped multilevel converters can be derived from the generalized converter topology called P2 topology proposed by Peng as illustrated in ure 4. The generalized multilevel converter topology can balance each voltage level by itself regardless of load characteristics, active or reactive power conversion and without any assistance from other circuits at any number of levels automatically. Thus, the topology provides a complete multilevel topology that embraces the existing multilevel converters in principle.

B. Mixed-Level Hybrid Multilevel Converter

To reduce the number of separate DC sources for high-voltage, high-power applications with multilevel converters, diode-clamped or capacitor-clamped converters could be used to replace the full-bridge cell in a cascaded converter. An example is shown in ure 5. The nine-level cascade converter incorporates a three-level diode-clamped converter as the cell. The original cascaded H-bridge multilevel converter requires four separate DC sources for one phase leg and twelve for a three-phase converter. If a five-level converter replaces the full-bridge cell, the voltage level is effectively doubled for each cell. Thus, to achieve the same nine voltage levels for each phase, only two separate DC sources are needed for one phase leg and six for a three-phase converter. The conuration has mixed-level hybrid multilevel units because it embeds multilevel cells as the building block of the cascade converter. The advantage of the topology is it needs less separate DC sources. The disadvantage for the topology is its control will be complicated due to its hybrid structure.

C. Soft-Switched Multilevel Converter

Some soft-switching methods can be implemented for different multilevel converters to reduce the switching loss and to increase efficiency. For the cascaded converter, because each converter cell is a bi-level circuit, the implementation of soft switching is not at all different from that of conventional bi-level converters. For capacitor-clamped or diode-clamped converters, soft-switching circuits have been proposed with different circuit combinations. One of soft-switching circuits is a zero-voltage-switching type which includes auxiliary resonant commutated pole (ARCP), coupled inductor with zero-voltage transition (ZVT), and their combinations as shown in ure 6.

D. Back-to-Back Diode-Clamped Converter

Two multilevel converters can be connected in a back-to-back arrangement and then the combination can be connected to the electrical system in a series-parallel arrangement as shown in ure 7. Both the current demanded from the utility and the voltage delivered to the load can be controlled at the same time. This series-parallel active power filter has been referred to as a universal power conditioner when used on electrical distribution systems and as a universal power flow controller when applied at the transmission level. Previously, Lai and Peng proposed the back-to-back diode-clamped topology shown in ure 8.for use as a high-voltage dc inter connection between two asynchronous ac systems or as a rectifier/inverter for an adjustable speed drive for high-voltage motors. The diode-clamped inverter has been chosen over the other two basic multilevel circuit topologies for use in a universal power conditioner for the following reasons:

§ All six phases (three on each inverter) can share a common dc link. Conversely, the cascade inverter requires that each dc level be separate, and this is not conducive to a back-to-back arrangement.

§ The multilevel flying-capacitor converter also shares a common dc link; however, each phase leg requires several additional auxiliary capacitors. These extra capacitors would add substantially to the cost and the size of the conditioner.

Because a diode-clamped converter acting as a universal power conditioner will be expected to compensate for harmonics and/or operate in low amplitude modulation index regions, a more sophisticated, higher-frequency switch control than the fundamental frequency switching method will be needed. For this reason, multilevel space vector and carrier-based PWM approaches are compared in the next section, as well as novel carrier-based PWM methodologies.

Oscar Lopez at al., [ ] presented multilevel multiphase space vector PWM algorithm which provides a sorted switching vector sequence that minimizes the number of switching. This SVPWM algorithm proves suitable for real-time implementation due to its low computational complexity.

Nicolau Pereira Filho at al., [ ] proposed an artificial neural network based space vector PWM for a five-level voltage-fed inverter. The approach uses two ANNs to implement the SVPWM algorithm. One ANN was used for triangle identification, generation of the corresponding weight matrices for the second ANN, and the coefficient matrices for the PWM waves. The second ANN was used for calculation of the duty cycles of the nearest three vectors. The ANN-based SVM implementation, particularly with ASIC chip, is considerably simpler than the traditional DSP-based solution.

P.Purkait at al., [ ] presented a new way of implementing the space vector modulation algorithm for reducing the neutral point current in the multilevel inverter. From the FFT analysis of line voltage and neutral current it is concluded that 1. Low frequency harmonic content of the neutral current is zero. 2. Neutral point current has a zero d.c. average value. But with this method, the line voltage contains slightly larger harmonics with respect to nearest three vector modulation.

R. S. Kanchan at al., [ ] presented a voltage modulation scheme of the SVPWM for multilevel inverters. The centering of the middle inverter switching vectors of the SVPWM is achieved by the addition of an offset time signal to the inverter gating signals, derived from the sampled amplitudes of the reference phase voltages. This SVPWM scheme covers the entire modulation range, including the over modulation region and it does not need any sector identification, as it required in conventional SVPWM schemes.

S. Ali Khajehoddin at al., [ ] proposed a simple and accurate current flow model for m-level diode-clamped multilevel converters. Independent of the modulation strategy, the model predicts the new states of the converter based on the measured values of output currents, dc-link voltages, and the current switching states. It presents a new understanding of voltage sharing accessibility among the dc link capacitors, and simplifies the prediction of the converter states and performance.

Using the switching function concept, a general, simple, and comprehensive current flow model for five-level diode-clamped multilevel converters is derived by S. A. Khajehoddin at al., [ ].Which presents a new understanding of voltage sharing accessibility among the dc link capacitors. An immediate conclusion is that the ordinary sinusoidal pulse width modulation (SPWM) fails to provide a voltage balancing solution and thus is inappropriate for switching diode-clamped multilevel converters. Moreover, an optimized voltage balancing strategy is proposed. The proposed scheme requires very simple calculations to accurately predict the capacitors voltages which are being used by the quadratic parameter to minimize the deviations of the DC-link voltages.

Giuseppe Carrara at al., [ ] analyzed the multilevel modulations process with a mathematical method which provided the analytical expression of the output phase voltages of the inverter and validated the result in over modulation operation. They highlighted the improvements in the harmonic contacts due to the increased number N of levels.

Zeliang Shu at al., [ ] developed a compact algorithm of space vector pulse width modulation for three-phase inverter. The conventional SVPWM is decomposed in to fast integer operations entirely by using an intermediate vector, which will properly counteract the redundant calculations of the remaining procedures. This has examined only in two level inverter applications.

In this thesis the main attention is given to Neutral Point Clamped Inverter.


This Thesis consists of six chapters. Chapter 1 gives an introduction to multilevel inverters, fundamentals of SVPWM, organization of the thesis and main objective of the thesis. Chapter 2 outlines the SVPWM applied for a two level inverter, determines the switching states, switching time duration and switching sequences for a two level inverter. In Chapter 3 algorithm for the implementation of SVPWM using fractal approach is discussed in detail.

The Chapter 4 explains SVPWM for a multilevel inverter using a fractal approach and is implemented for three level and five level inverters. In Chapter 5 the experimental investigations of the algorithm is implemented in MATLAB/SIMULINK software. Chapter 6 discusses the results of the MATLAB /SIMULINK model. Conclusions are given in Chapter7.