Metal Gate Nucleation And Microstructure Engineering Essay

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Scaling of transistors (the foot soldiers of modern information age) provides faster computation at the expense of excessive power dissipation. Thus to address these challenges, high-k/metal gate stack has been introduced in commercially available microprocessors since late 2007. From then titanium nitride (TiN) metal gate's work function (Wf) tunability with its thickness (thickness increases, Wf increases) is a well known phenomena. Many hypotheses are made over the years which include but not limited to: trap charge and metal gate nucleation [1], nitrogen concentration [2], microstructure agglomeration and global stress [3], metal oxide formation [4], and interfacial oxide thickness [5]. However, clear contradictions exist in these assumptions. Also, nearly all the papers skipped a comprehensive approach to explain this complex paradigm. Therefore, in this work we first show a comprehensive physical investigation using TEM/EELS, SIMS, XPS and XRD to show replacement of oxygen by nitrogen in the metal/dielectric interface, formation of TiONx, reduction of Ti/N concentration and grain size increment happen with TiN thickness increment and thus may increase the Wf. Then, using these finding, we experimentally show 300mV of Vfb modulation but with an effective oxide thickness (EOT) penalty in 10nm TiN MOSCAP by using low temperature oxygen annealing and nitrogen implantation. Nonetheless, a low thermal budget flow (replicating gate-last) shows similar Wf boost up without any EOT penalty. Thus, this study [i] quantifies role of various factors in TiN Wf tuning; [ii] it also reproduces the thickness varied TiN Wf modulation in single thickness TiN thus reducing the burden of complex integration and gate stack etch; and finally [iii] it shows that in a low thermal budget flow, it is more effective to achieve higher Wf without any EOT penalty.


All praise is to Allah the almighty.

I would like to express my deepest gratitude towards my supervisor and mentor Dr. Muhammad Hussain for the constant motivation, never ending support and guidance. I am also heartily thankful to Dr. Casey Smith for his invaluable advice and support throughout the course of this project. This work would not have been possible without their guidance. I would also like to extend a special thank you to Dr. Khaled Salama and Dr. Aram Amassian for taking out the time to review this thesis. Finally, I am grateful to my parents, my siblings and friends for their moral support.

Table of Contents


Field Effect Transistor


Completmentary Metal Oxide Semiconductor


n-channel Metal Oxide Semiconductor Field Effect Transistor


p-channel Metal Oxide Semiconductor Field Effect Transistor


Metal Oxide Semiconductor Capacitor


Titanium Nitride


Multi-threshold CMOS

List of Abbreviations

List of Figures

Chapter 1: Introduction


The metal-oxide-semiconductor field-effect transistor (MOSFET) which is the basic unit in a microprocessor integrated circuit is a 4-terminal electronic used for switching electronic signals in the microprocessor. The depth of functionality of a microprocessor depends of the number of transistor that can be inexpensively incorporated in the whole chip without increasing power dissipation a lot. After integrated circuit had first been invented by Jack Kilby on September 12, 1958 [1] where all the components of the electronic circuit are completely integrated[2], Robert Noyce also came up with his own idea of Silicon based integrated circuit of half a year later than Kilby solving many practical problems that Kilby's had not. In the early days of integrated circuits, only a few transistors could be placed on a chip, as the scale used was large because of the contemporary technology. As the extent of integration was small, the design & fabrication were done easily. Later on, millions, and now billions[3] of transistors could be placed on one chip.

Integrated circuits have constantly migrated to smaller feature sizes over the years, allowing more circuit elements to be packed on each chip. This increased capacity per unit area can be used to decrease cost and/or increase functionality. This trend exactly follows Moore's law [4, 5] which states that the number of transistors that can be expensively placed in an integrated circuit doubles every two years. In general, as the feature size shrinks, almost everything improves-the cost per unit and the switching power consumption go down, and the speed goes up. However, ICs with nanometer-scale transistor are not without their problems, principal among which is leakage current such as subthreshold leakage[6], although these problems are not insoluble and will likely be solved or at least amended by the introduction of high-k dielectrics such as Hafnium dioxide (HfO2) instead of conventional Silicon dioxide (SiO2) dielectric. At the same time, metal gate is also introduced instead of poly-silicon gate to solve the problems such as poor bonding poly-silicon gate and high-k dielectric, phonon scattering in channel region and uneven dielectric trap charges. For that reason, since 2007, semiconductor industry has migrated to high-k/metal gate stacks instead of classical SiO2/poly-Silicon gate[7]. As one of the few materials well established in CMOS technology, titanium nitride (TiN) turned out as remarkably stable[8].

TiN is a mid-gap work-function material and well-known for work function tenability i.e. the work function of TiN metal gate can be varied with the thickness of the TiN layer. As the work function is related to the threshold voltage of the transistor, the threshold voltage of the transistors can be varied by varying the thickness of TiN layer. This paves a way to have multi-threshold voltage device on the chip.

The potential of the multi-threshold CMOS (MTCOS) is that it utilizes transistors with multiple threshold voltages (Vt) to optimize delay or power. Lower voltage devices are used on critical delay paths to minimize clock periods. Higher voltage devices are used on non-critical paths to reduce static leakage power without incurring a delay penalty. Typical high voltage devices reduce static leakage by 10 times compared with low voltage devices. One method of creating devices with multiple threshold voltages is to apply different bias voltages (Vb) to the base or bulk terminal of transistors, the other way can be "gate engineering". In MOSFET devices, lower bias voltages will increase voltages, increase delay, and reduce static leakage. A common MTCMOS approach for reducing power uses sleep transistors. Logic is supplied by a virtual power rail. Low voltage devices are used in the logic for speed. The logic may be turned off by collapsing the virtual power rail. High voltage devices connecting the power rails and virtual power rails are turned off in sleep mode. High voltage devices are used as sleep transistors to reduce static leakage.


As we discussed in previous section, the ability of TiN gate metal to tune its work function can paves a way to have mutli-threshold device in a chip and multi-threshold CMOS is an approach to the circuit designer to have the optimization of power consumption and speed of the operation of the whole chip. Normally it is well-observed that the work function of TiN metal gate can be varied by changing the thickness of the TiN layer. So the threshold voltage of MOSFET with TiN metal gate can be tuned by varying the thickness of TiN metal. To get the multi-threshold devices in a same chip, we have to have TiN layers of different thicknesses in different devices.

But the integration of TiN layers of different thickness in different transistors on the same substrate is quite complex. The etch of deposited the subsequent layers (such as contact layers) on different TiN thicknesses becomes quite troublesome and the good surface profile may not achieved because of this problem. So our mission is to investigate an alternative way to tune the work function of TiN metal gate with easier process without changing the metal gate thickness.


To investigate a better solution to tune TiN work function without changing the thickness, we first need to understand why the work function modulates with thickness change. So we have done comprehensive physical investigation using transmission electron microscope/electron energy loss spectroscopy (TEM/EELS), x-ray diffraction c(XRD), X-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS). Based on the developed understanding from the physical investigation, we will apply some appropriate processes to replicate the same work function tuning mechanism without changing the thickness. Then, the measurement of capacitance versus voltage characteristics of the MOS structure devices and analysis of that data to plot the flatband voltages versus effective oxide thickness will verifty the change of the flatband voltage i.e. the change of the work function to TiN metal gate.

Thesis Organization

A comprehensive physical investigation of work function tuning with thickness and investigation of alternative to tune the work function of TiN gate metal is the scope of this study. For this purpose, we investigated the fabricated metal-oxide-semiconductor structure. So the physics of metal-oxide-semiconductor is related to this study. Also, the review of the previous attempt for the related investigation is in the scope of this study.

So Chapter 2 describes the physics behind the fabricated structure as well as the review of the related literature. Chapter 3 describes the fabrication process steps. Chapter 4 analyzes the mechanism of changing work function with thickness change based on the experimental result and analysis. Chapter 5 investigates the work function engineering based on study described in chapter 4 and studies the work function modulation due to the engineering adopted.

Chapter 2: Review of Literature

As the metal-oxide-semiconductor (MOS) structure is basis for the MOS transistor structure, we will concentrate on the MOS capacitor structure to study the work function of metal gate. After reviewing the brief physics of MOS structure, we will discuss the related literature.

MOS Capacitor

Fig. 1 shows a MOS capacitor where there is a semiconductor substrate, a thin dielectric layer and a top metal contact called the gate. Another metal layer forms an Ohmic contact to the back of the substrate. Here the substrate has a p-type and silicon dioxide is used as the dielectric layer.

Fig. 1: MOS capacitance structure []

To understand the operation, let us explain the three different bias voltages- (i)below the flatband voltage, VFB, (ii) between the flatband voltage, VFB and the threshold voltage, VT, and (iii) finally one larger than the threshold voltage. These voltage are bias regimes are called the accumulation, depletion and inversion mode of operation (Fig. 2).

Fig. 2: Charges in an n-type MOS structure under different conditions

Accumulation occurs typically for negative voltages where the negative charge on the gate attracts holes from the substrate to the oxide-semiconductor interface. Depletion occurs for positive voltages. The positive charge on the gate pushes the mobile holes into the substrate. Therefore, the semiconductor is depleted of mobile carriers at the interface and a negative charge, due to the ionized acceptor ions, is left in the space charge region. The voltage separating the accumulation and depletion regime is referred to as the flatband voltage, VFB. Inversion occurs at voltages beyond the threshold voltage. In inversion, there exists a negatively charged inversion layer at the oxide-semiconductor interface in addition to the depletion-layer. This inversion layer is due to the minority carriers that are attracted to the interface by the positive gate voltage.

The energy band diagram of an n-MOS capacitor biased in inversion is shown in Fig. 3. The oxide is modeled as a semiconductor with a very large bandgap and blocks any flow of carriers between the semiconductor and the gate metal. The band bending in the semiconductor is consistent with the presence of a depletion layer. At the semiconductor-oxide interface, the Fermi energy is close to the conduction band edge as expected when a high density of electrons is present. The semiconductor remains in thermal equilibrium even when a voltage is applied to the gate. The presence of an electric field does not automatically lead to a non-equilibrium condition, as was also the case for a p-n diode with zero bias.

Fig. 3: Energy band diagram of an MOS structure biased in inversion.

Now let us discuss the four modes of operation of an MOS structure: Flatband, Depletion, Inversion and Accumulation. Flatband conditions exist when no charge is present in the semiconductor so that the silicon energy band is flat. Initially we will assume that this occurs at zero gate bias. Later we will consider the actual flatband voltage in more detail. Surface depletion occurs when the holes in the substrate are pushed away by a positive gate voltage. A more positive voltage also attracts electrons (the minority carriers) to the surface, which form the so-called inversion layer. Under negative gate bias, one attracts holes from the p-type substrate to the surface, yielding accumulation.


Fig. 4: Flatband energy diagram of MOS structure[]

If there is no charge present in the oxide or at the oxide-semiconductor interface, the flatband voltage simply equals the difference between the gate metal workfunction, FM, and the semiconductor workfunction, FS.


The workfunction is the voltage required to extract an electron from the Fermi energy to the vacuum level. This voltage is between three and five Volt for most metals. The actual value of the workfunction of a metal deposited onto silicon dioxide is not exactly the same as that of the metal in vacuum.

The workfunction of a semiconductor, FS, requires some more thought since the Fermi energy varies with the doping type as well as with the doping concentration. This workfunction equals the sum of the electron affinity in the semiconductor, c, the difference between the conduction band energy and the intrinsic energy divided by the electronic charge in addition to the bulk potential. This is expressed by the following equation:


For a charge, Qi, located at the interface between the oxide and the semiconductor, and a charge density, rox, distributed within the oxide, the flatband voltage is given by:


where the second term is the voltage across the oxide due to the charge at the oxide-semiconductor interface and the third term is due to the charge density in the oxide.


TiN as a metal gate

Chapter 3: Experimental

We prepared our experimental samples on heavily doped p-type Si (100) substrates. A gate dielectric consisting of chemical SiO2 as a host interface and post-deposition NH3 annealed 2nm thick hafnium dioxide (HfO2) was then deposited by atomic layer deposition (ALD). Then we deposited a series of 5, 10 and 20nm thick TiN (metal gate film) using ALD on top of the gate dielectric. We prepared multiple samples in each split to ensure statistical accuracy. Next we deposited a 100nm poly-Si using chemical vapor deposition. We then carried out a spike anneal at 1000°C for 1 sec to imitate the actual device [1-3]. We used transmission electron microscope/electron energy loss spectroscopy (TEM/EELS), x-ray diffraction (XRD), x-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS) to physically analyze the samples.

Based on the developed understanding by analyzing the samples, we prepared another batch of experimental samples. First following the same steps as in the previous samples, just after TiN metal deposition, we implant N in several samples and do the oxygen anneal in some samples. Then after poly-silicon deposition and subsequent P implantation, high temperature short anneal is done in several samples, long anneal is done in some samples and no anneal is done in a sample.

Fabrication steps:

Here are the details of fabrication steps. The layers are not drawn to scale.

Fig. Fabricated MOSCAP structure.

Wafer pre-clean: A set of P-type, <100(±0.5)> orientated, 180nm lithograde general purpose test wafers is used as the substrates. Before starting the other process, the substrates are pre-cleaned with SPM or piranha solution.

High-k deposition: 2nm Hafnium dioxide is deposited by atomic layer deposition.

Post Deposition Annealing(PDA): PDA is one of the fundamental technique to improve the material properties in the deposited film [4]. N2 post-deposition annealing is done by at 700oC for 60 sec.

Metal deposition: TiN of 5nm, 10nm and 15nm are deposited in several wafers using atomic layer deposition (ALD).

N-implantation is done with 1Ã-1015 /cm2 dose on several wafers.

Furnace annealing in O2 is carried out at 400oC for 30min on several wafers.

Etch back: For a wafers, standard clean 1 (SC1) is used 20 minutes.

Poly-silicon deposition with P-implantation: 100nm poly-silicon is deposited by chemical vapor deposition. Then P is implanted with the implantation dose of 2.5Ã-1015 /cm2.

High temperature anneal: On several substrates, a short anneal of 2 sec is carried out at 1000oC. A long anneal of 3 minutes is also carried out on some other subtrates. For a substrate, no annealing is carried out.

Etching: After photo-resist coating and patterning, the wafer is etched the oxide layer can be found.

For the first batch of substrates with which TEM/EELS, XRD, XPS and SIMS analysis are carried out, the step 5, 6, 7 and 9 is not used. Instead of step 9, a spike anneal at 1000oC for 1 sec is carried out.


We characterize the first set of devices using the transmission electron microscope/electron energy loss spectroscopy (TEM/EELS), x-ray diffraction (XRD), x-ray photoelectron spectroscopy (XPS) and secondary ion mass spectroscopy (SIMS).

Transmission electron microscope (TEM): It is a microscopy system whereby a beam of electrons is transmitted through an ultra thin specimen, interacting with the specimen as it passes through.

Electron energy loss spectroscopy (EELS): In electron energy loss spectroscopy (EELS) a material is exposed to a beam of electrons with a known, narrow range of kinetic energies. This can be used to generate an image which provides information on elemental composition, based upon the atomic transition during electron-electron interaction[5].

X-ray diffraction (XRD): X-ray diffraction yields the atomic structure of materials and is based on the elastic scattering of X-rays from the electron clouds of the individual atoms in the system. The most comprehensive description of scattering from crystals is given by the dynamical theory of diffraction [6].

X-ray photoelectron spectroscopy (XPS): It is a quantitative spectroscopic technique that measures the elemental composition, empirical formula, chemical state and electronic state of the elements that exist within a material.

Secondary ion mass spectroscopy (SIMS): A technique used in materials science and surface science to analyze the composition of solid surfaces and thin films by sputtering the surface of the specimen with a focused primary ion beam and collecting and analyzing ejected secondary ions.

CV measurement and analysis

Capacitances versus voltage (CV) characteristics are measured using Keithley Semiconductor Characterization System (SCS) 4200 with a CV module setup. For three frequencies such as 10KHz, 100KHz and 1MHz, a large number of devices of different sizes are measured from each wafers so that we can ensure maximum statistical accuracy. These data are analyzed using Hauser CVC-software[7] and the equivalent oxide thickness (EOT) and flat-band voltage (Vfb) were extracted for each device. The variation of Vfb from wafer to wafer equals the variation of work function.

Chapter 4: Mechanism of Work Function Tuning

Recent advancement of high-k/metal gate Complementary Metal Oxide Semiconductor (CMOS) technology shows many evidences that effective work function (Wf) of Titanium Nitride (TiN) metal gate increases with its thickness [1-5]. This can pave the way for multiple threshold voltage (Vt) Systems-on-Chip (SoC). Many hypotheses are made over the years which include but not limited to: trap charge and metal gate nucleation [1], nitrogen concentration [2], microstructure agglomeration and global stress [3], metal oxide formation [4], and interfacial oxide thickness [5]. However, clear contradictions exist in these assumptions. Also, nearly all the papers skipped a comprehensive approach to explain this complex paradigm. Concentration of nitrogen is a prominent one where some studies showed its richness leads to higher Wf whereas findings are available to support the reverse fact [6-8]. Therefore, we comprehensively examined how the physical properties of TiN changes with its various thickness and impacts its Wf.

TEM Analysis

At first, we studied our samples with TEM and it showed uniform deposition of gate stacks (high-k/metal) and the thicknesses of each intended split were nearly right on target [Fig. 1(a)]. Although in the past discontinuous TiN island formation and thus direct mix-up of poly-silicon and high-k for thin film (<5nm) was speculated to be the reason for lower Wf [1], in the TEM analysis we did not observe the same [Fig. 1(a)]. We observed continuous TiN films without any penetration of poly-silicon to the underlying dielectric. Therefore, possible interaction between high-k/poly-Si cannot be a reason for Wf variation. It was also speculated that the penetration of the tail of electron wave function of n+ poly through very thin TiN layer occurs. However, possible effects from extrinsic causes such as interfacial reaction or stoichiometry change with film thickness due to diffusion was not ruled out [9]. Another possible reason for the Wf change is the increased value of interfacial fixed charge (Qf), an effect that can shift VFB and change the effective Wf. However, the value of Qf increased by only a factor of two over the entire TiN thickness range, suggesting that fixed charge alone cannot explain the entire increase in TiN work function (1E10 cm-2 vs. 2E10 cm-2) [2].

EELS Analysis

In our EELS analysis we observed that the relative composition of nitrogen is increasing specifically in the TiN/HfO2 interface [Fig. 1(b)]. It is possible that oxygen replacement by nitrogen in the interface can increase the Wf. This effect is due to a balance of two opposing dipoles associated with the Ti and Hf atoms at the interface (the sequence O-Hf-O-Ti-N is being replaced by O-Hf-N-Ti-N). Due to the larger polarizability of the Hf atom compared with that of Ti, the dipole associated with the Hf atom is more pronounced creating a net increase of the Wf [10]. Previously three reports claimed nitrogen concentration may tune the Wf characteristics [2, 6-8]. Our XPS analysis [Fig. 2] also resonate the same. Increased nitrogen will reduce influence of low vacuum Wf material Ti and thus results in TiN higher Wf [1].

Previously, Wakabayashi [6] and Westlinder [7] reported that by using ion implantation or higher nitrogen gas flow during sputtering, respectively, the Wf increases in n-MOSFET. However, Wakabayashi's claim was convoluted with channel doping. Also, it is not clear what perturbation was caused by ion implantation process. On the other hand, Liu (2006) [8] contradicted this observation by using a sputtering system (same as Westlinder [7]) where with higher nitrogen gas flow the NMOS Wf in non-planar FinFET device was reduced. Thus, based on our physical analysis and careful review of contradictory reports, we believe the nitrogen's role to alter the Wf depends on nitrogen inclusion process as well as the device architecture.

Figure 1: (a) TEM and (b) EELS analysis of TiN (5, 10 and 20nm)/SiO2 (Interface oxide)/HfO2. The TEM image shows uniform and continuous deposition of high-k/metal gate stacks. EELS analysis shows that the relative composition of nitrogen is increasing specifically in the TiN/HfO2 interface.

XPS Analysis

Besides stoicheometric analysis, in our XPS analysis for Ti 2p and N 1s, we did not observe any shifting in the peak position [Fig. 2]. This suggests that there was not any significant bonding trend shift for N 1s. Therefore, chemical analysis does not indicate any significant correlation related to surface chemistry or bonding.

Previously we reported that typically ALD processed TiN contains some oxygen and the thicker the TiN, the probability of oxygen intrusion is higher too and thus resulting in thicker interfacial oxide [11]. Current TEM images also show thicker interfacial oxide associate with thicker TiN [Fig. 1(a)]. Our EELS analysis also shows oxygen is fairly distributed throughout the high-k/TiN gate stack [Fig. 1(b)]. However, the relative composition of oxygen reduces with higher thickness of TiN.

Figure 2: XPS analysis of TiN experimental samples. Inset shows the elemental composition. We did not observe any significant peak shifting for Ti 2p and N 1s. Elemental analysis shows increased amount of nitrogen in thicker TiN.

SIMS Analysis

Our SIMS study [Fig. 3] shows a direct correlation between TiONx formation in metal/dielectric interface and TiN thickness. When the two surfaces are brought into contact, charge is exchanged between the metal and the dielectric surface states resulting in the formation of an interfacial dipole. These changes in Wf suggest that an increase in the number of oxygen excess regions at the interface can modify the proportion of charges exchanged at the interface [12].

In the past, Bae [7] inconclusively indicated some interference by global stress in TiN. We observe that the stress of TiN increases with its thickness [13]. For 5nm TiN the tensile stress is 1.12 GPa and it goes up to 1.7GPa for 20nm TiN. At the same time, the same set of samples show increased Wf, with increased thickness of TiN. This is indicative that stress may play some fringe role to tune the work function like previously reported for some other material systems [14]. We took a set of 10nm ALD TiN/2nm HfO2 MOSCAP devices and when uniaxial stress was applied, no significant change (Wf change was less than 5%) was observed.

Figure 3: SIMS analysis of TiN experimental samples shows a direct correlation between TiONx formation in metal/dielectric interface and TiN thickness.

XRD Analysis

During our XRD analysis [Fig. 4] we observed no significant changes in crystal phase or orientation. Also, in the past amorphous TiN has shown Wf rise with its thickness increment without any preferred crystal orientation [2]. There was no peak shifting in the rocking curves. Then general observation on the grain size (volume-weighted size) using Scherrer method, (which neglects the contribution of the microstrain and gives lower limit values of the TiN grain size) that thicker films seem to have larger grains [15, 16]. It might be explained by the fact that Wf decreases with small grain size due to the increasing fractional defect area near the crystallite edges [17]. Also, the film with small grain indicates that it exhibits poor crystalline quality [18]. In addition, amorphous film has lower Wf than its crystalline counterpart [19, 20]. Therefore, the poor crystalline quality (small grain size) may decrease the Wf.

Figure 4: XRD analysis of TiN experimental samples shows no significant changes in crystal phase or orientation. The general observation on the grain size (volume-weighted size) using Scherrer method, (which neglects the contribution of the microstrain and gives lower limit values of the TiN grain size) that thicker films seem to have larger grains.

To conclude, we attribute that with increased thickness of TiN, replacement of oxygen by nitrogen in the metal/dielectric interface, formation of TiOx or TiONx, reduction of Ti/N concentration and grain size increment also increase and thus may affect the Wf. Also, apparently a weak correlation exists between stress and Wf of TiN metal gate. Advancement in process technology based on our study can create a larger window of Wf tunability in single thickness based TiN to reproduce its multi-thickness induced Wf. This offers a simple and practical solution for multi threshold voltage (Vt) devices in Systems-on-Chip.


Future Research Objectives