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In this modern world there is a drastic increase in the manufacturing of vehicles compare to 20 years ago. The more cars being sold, lead to an increase in car thefts. To combat this setback majority of the time, a car security system can be installed. Generally a car security system consists of an alarm, immobilizer, tracking system and a remote keyless entry.
Remote keyless systems (RKS) are also used for other purposes such as opening and closing of electronic gates and doors. It is also used for luxury services such as opening and closing curtains and controlling of lighting systems. These systems have different functionality, but use the same type of security components as the car entry system .
A key fob is a miniature hardware device containing buttons, which has an electric circuit built in to fulfill the functions as stated above.
Modulation is a technique of imposing information (analog or digital ) contained in a lower frequency signal which is the modulating signal, onto a higher frequency signal known as the carrier. The modulation process has an advantage of enabling many baseband channels at various carrier frequencies to be transmitted simultaneously without the interference on each other. Modulation is a requirement in an RF system to translate a baseband signal(audio, video ,data) from its original frequency bandwidth to a specified RF frequency spectrum. Modulation technique most commonly used in RKE systems
A modulation scheme known as amplitude shift key (ASK) is used majority of the time in RKE systems.
From figure…, it can be clearly be noticed that the amplitude of the carrier signal varies with the modulating signal. The phase and frequency remains constant. Theses levels of amplitudes represent binary 0's and 1's. When a binary 0 is presented, the carrier signal is absent and when a binary 1 is presented the carrier signal is present. An advantage of using ASK modulation technique is, it is an inexpensive process.
The RKE system is required to provide secure codes during transmission by utilizing a signaling technique known as Spread Spectrum (SS) modulation , so that it is not easily intercepted by criminals. A spread spectrum communication system rejects intentional and unintentional external interference.
The form of SS modulation used majority of the time is frequency-hop SS modulation (FHSS). In this modulation scheme the spectrum of the data modulated carrier is widened by changing the carrier frequency in a pseudo-random manner .
Frequency hop spread spectrum (FHSS)
Transmitter block diagram:
Frequency hoping output
Receiver block diagram
Remote key less entry receivers is a fast growing application for wireless technology and in almost every communications systems; a key component named a low noise amplifier exists in the receiving end. It plays a vital role in amplifying weak signals received from the transmitted antenna to a decent power level with adding minimum noise as possible. Amplification is one of the most basic and prevalent microwave circuit functions in modern RF and microwave systems . The front end of the receiver governs the noise performance of the entire system. The LNA must not introduce any distortions and channel interference during the amplification process.
Figure 1.1: Superheterodyne receiver block diagram
1.2 LNA Design Parameters
Noise is present in all active and passive components of a RF system, which is defined as random fluctuation of EMF or current, and is the unwanted form of energy that interferes with the reception and accurate reproduction of the wanted signal .
Two types of noise are encountered by the receiver: the noise intercepted by the antenna which is external noise and noise generated internally by the receiver. The external noise consist of ;atmospheric noise, man made noise, galactic noise and sky noise whilst the internal noise is made up of shot noise, thermal or Nyquist noise and flicker noise.
Noise free circuits do not exist and is therefore evaluated by using the signal to noise ratio and noise figure (NF) approach.
184.108.40.206 Signal to noise ratio
Signal to noise ratio is a ratio comparing signal power to noise power at a specific point in a system. If the noise power is greater than the signal power, then the wanted signal will not be detected.
220.127.116.11 Noise figure
Figure 2: Two port network
Noise factor is a quantitative measure similar to the signal to noise ratio at the input port and output port of the device under test. To what degree the device under test degrades the signal to noise ratio measured in dB, is regarded as the noise figure (NF). The systems noise figure is dependant on various factors such as amplification, bias applied, losses that exist in a circuit and solid state devices.
Figure 3: Operating power gain, Available power gain and Transducer gain in a two port network
In RF circuitry the gain that is of interest is power gain. A power gain is essential because of impedance having broad variation levels that are present in RF circuits. Current gains and voltage gains in a circuit become insignificant when impedance levels alter.
PAVS = available power from source
PIB = input power to the two port network
PAVB = available power from the two port network
PL = power which is delivered to load
The three important power gains are as follows:
18.104.22.168 Power Gain
Power gain is a ratio of power delivered to the load ZL, to the input power of the active device PIB as shown in equation……., and power gain is not dependant of ZS
22.214.171.124 Available Gain
Available gain is a ratio of power existing from the two port network PAVB, to power existing from the source PAVS as shown in equation…. and is a function of the source reflection coefficient (ΓS).
126.96.36.199 Transducer Gain
Transducer Gain is a valuable gain for designing of amplifier, which is a ratio of power being conveyed from source to the load in scenarios where the input or output impedances are not matched, and is greatly dependant on source reflection coefficient (ΓS) and load reflection coefficient (ΓL).
The gain can be maximized if both the input and output ports are conjugately matched to source and load which results by GAmax = GP = GT. This phenomenon is known as Maximum Available Gain (MAG)
1.2.3 1 dB compression point
Figure 3: Output power of active device as function of input power
Po[dBm] = output power level of amplifier displayed in dBm
OP1dB = output power of amplifier at 1 dB compression point measured in dBm
Pi(MDS) = minimum input signal that is detectable measured in dBm
Po(MDS) = output power level of Pi(MDS) measured in dBm
IP1dB = input power level of the amplifier referred to the 1 dB compression point measure in dBm
An active device has a linear and non-linear region of operation which is a reasonable approximation. Linear operation is vital, especially when there is a strong interfering signal close to the weak input signal. At lower power levels the linear response has a slope of unity. As the input power into the active device has increased to a maximum level, the active device output power starts to saturate which causes the linear gain to roll off relative to the theoretical gain. A level of 1 dB drop of output power from the maximum output power level is known as, the 1 dB compression point. A further increase of input power levels will generate distortion components of high harmonics. The advantage of a higher 1 dB point value means the input power can be of a greater value into the amplifier before the output power of the amplifier starts to compress.
To calculate the output 1 dB compression point (OP1dB) value, equation…is used
OP1dB = IP1dB + GA dBm
1.2.4 Third order intercept
Figure 4: Third order intercept point
When the active device has entered saturation, it is now operating in the non-linear region and generates inter-modulation products. These products are multiples, sum and differences of the fundamental frequency. Third order intercept (TOI) is a fictitious point, where the desired linear output power, slope 1:1 response and undesirable third order output power slope 3:1 response intercepts. This intercept point can be improved by increasing the collector current of the biasing circuit.
Figure 5: Intermodulation distortion of active device
Inter-modulation distortion is the result of applying two un-modulated harmonic signals of slightly different frequency to the input of an amplifier and observing the output 
From the diagram above the output results can be interpreted by, the third order tone (2f2-f1) is closest to the fundamental tone (f2), therefore can not be filtered and is very likely to fall within the bandwidth of the amplifier adding distortion and non-linearity to the output signal. The intermodulation product increases at multiple rates of the fundamental signal. There are many spurious tones which are situated outside the bandwidth of the amplifier and cause no problem because of having very small power levels.
Intermodulation distortion (IMD) level is defined as the difference between the fundamental ouput power of amplifier (Po) and output power of third order product as shown in figure…., measured in dB as shown in equation….. The third harmonic must be of a much lower value than the output power of the fundamental frequency so the likelihood of interference caused to the fundamental output signal is negligible.
IMD (dB) = Pout (f2) (dBm) - Pout (2f2-f1) (dBm)
Third order intercept point(OIP3) value can be estimated by adding 10 dB to the P1dB point as shown in equation…. :
OIP3 = P1dB + 10dB
1.2.5 Dynamic Range
Dynamic range (DR) is defined as the power range over which the amplifier provides useful linear operation [minicircuits], between the minimum detectable output signal and the 1dB compression point, as shown in figure 4 and explained by equation……………….. for a mixer, amplification, or receiver system, the designer would like to have a high dynamic range so the system can operate over a wide range of input power levels.
DR = (P1dB- Pmdos)
The initial requirement which is a great concern for LNA design is, to provide a stable performance at the desired frequency range
An amplifier may be classified as being potentially unstable if the magnitude of any reflection coefficient is greater than 1 as shown in the conditions below:
To overcome this dilemma a design rule is initiated; Rollet stability factor (K) should be greater than unity and Delta â”‚Δâ”‚ less than unity as shown in equation………………………..to be classified as unconditionally stable. This also means the magnitude of the reflection coefficient shown above will be less than 1.
Δ= (S11S22-S12S21) <1
Rollet stability factor (K) can be numerically calculated by using S-parameter values as shown in equation…….or computed on Advance Design Systems (ADS) by having K factor swept over a desired frequency range.
Another uncomplicated equation which could replace the K factor is the μ factor as shown in equation….:, this could also be simulated on Advance Design System (ADS) software
The amplifier is potentially unstable if μ is less than 1 and unconditionally stable if greater than 1
Figure 6: Two port network showing various reflection coefficients
If K is less than unity and |Δ | greater than unity the active device is classified as potentially unstable and does not mean it can not be used. To combat this crisis four resistive loading techniques are mentioned below for Bipolar Junction Transistor (BJT), which are designed before the matching network:
A series connected resistor with the base of active device to guarantee source stability
A shunt connected resistor with the base of active device to guarantee source stability
A series connected resistor with the collector of active device to ensure load stability
A shunt connected resistor with the collector of active device to ensure load stability
The first two techniques are rarely used as they provide poor noise figure values even though it provides great stability to the design.
The fourth technique is most preferred for LNA designs as it provides excellent circuit stabilization and a relative good compromise between power gain and noise figure. This technique degrades the noise figure and power gain if utilized in a narrowband amplifier design. Stabilizing technique used for narrowband amplifier design is by choosing a source reflection coefficient (ΓS) and load reflection coefficient (ΓL) in the stable region of smith chart but this technique is not often used in practice.
1.2.7 DC Biasing
Majority of the time bias networks are just taken for granted due to its perceptible simplicity. The purpose of biasing is to provide the appropriate quiescent point for the active devices under specified operating conditions and maintain a constant setting irrespective of transistor parameter variations and temperature fluctuations . Two devices with totally different DC current gain (hFE) can have a quiet close RF performance provided both the active devices are biased at the same collector current (IC) and collector-emitter voltage (VCE).
Active and Passive biasing networks exist. Active biasing is usually a integrated circuit, very costly but sets IC and VCE at the required point regardless if hFE and temperature changers.
The least costly biasing networks are passive biasing which are made up of two to five resistors arranged in a certain pattern. It provides decent objective in ensuring IC remains constant with variations of hFE.
Figure 7: Three different passive biasing networks; (a) non-stabilising bias network, (b) Emitter feedback bias network, (c) Current source with voltage feedback bias network
188.8.131.52 Non-stabilised bias network shown in circuit (a)
The most straight forward bias network which allows IC to change as hFE varies. These both variables are directly proportional to each other. This is not used in practice a lot because this design does not accommodate for change in hFE.
184.108.40.206Current source with voltage feedback bias network shown in circuit (b)
This design has a emitter resistor (RE) which provides voltage feedback, optimum control over temperature and hFE changes. RE must be bypassed with a capacitor for RF, and a real capacitor has internal lead inductance which could cause the active device to be unstable from unwanted regenerative feedback.
220.127.116.11Emitter feedback bias network shown in circuit (c)
This biasing network is used when the supply voltage is of a high value (VCC>15V), which has resistor (RB1) and (RB2) as voltage dividers. It provides negative feedback which limits the IC change as hFE varies which directly provides temperature stability. Current source with voltage feedback biasing network is majority of the time used in practice.
1.2.8 Active Device
Figure ..: family tree of transistors
18.104.22.168 Bipolar Junction Transistors (BJT)
Diodes consist of two types of semiconductor material known as germanium and silicon to form a PN junction, as shown in figure 8(b). The P represents a positive region and N a negative region. So if two diodes are joined together in a series combination, it can be deduced that a two junction, three layer, three terminal device has formed a Bipolar Junction Transistor (BJT), as shown in figure 8(c). The word transistor is derived from the words, Transistor and Varistor. A BJT consist of three semiconductor regions known as; emitter, base and collector as shown in figure 8(d) and is current driven device.
Figure 8: NPN transistor developed from two diodes
During a forward bias, the depletion region narrows between the base to emitter junction. Then free electrons add up with the n-type heavily doped emitter region, which then diffuses into the p-type region of the base. The base region has minimum number of holes and is very thin, which allows for a small amount of electrons to pass through base to emitter junction adding up with present holes in the base. An electron current is formed at the base as recombined electrons flow. In the base to collector region which is reversed biased, an electric field is created by the force between the negative and positive ions. These electrons now move through the collector region, out through the collector lead, and into the positive terminal of the collector voltage source[pg168electfundamentals]
22.214.171.124 Field Effect Transistors (FET)
Field effect transistors (FETs) are not current controlled devices as the BJTs; they are voltage controlled unipolar devices best suited for higher operating frequencies. The two types of FETs are metal oxide semiconductors field effect transistors (MOSFETS) and junction field effect transistors (JFET).
Figure 9: (a) n channel FET structure and (b) n channel symbol of FET
Basic structure of FET is shown in figure 9(a), having a drain situated at the top end and the source at the opposite end to the drain. The n channel is situated in-between the two p regions.
VDD provides voltage and drain to source current. A reverse bias voltage is set by VGG between gate-source junctions which then creates a depletion region at the pn junction. The pn junction is thus extended into the n-channel, increasing its resistance by limiting the channel size. Gate voltage controls the channel size, resistance and drain current (ID). The gate length limits the frequency operation. FET has an extremely high input resistance and generates minimum output noise.
Figure…: S-parameters of a 2 port network
S-parameters or Scattering parameters quantifies exactly the propagation of voltage in the environment of radio frequency which is a complex number and is frequency dependant. At ultra high frequencies (UHF) it is complicated to directly measure current and voltages, therefore incident and reflected power are measured using directional couplers.
A 2 port network displays four S-parameters:
S11 = Input Reflection Coefficient = |a2 = 0 = (reflected power at port 1/incident power at port 1)
S12 = Reverse Gain Coefficient = |a1 = 0 = (transmitted power at port 1/incident power at port 2)
S21 = Forward Gain Coefficient = |a2 = 0 = (transmitted power at port 2/incident power at port 1)
S22 = Output Reflection Coefficient = |a1 = 0 = (reflected power at port 2/incident power at port 2)
No power is returned to port 1 or port 2 which is implied by condition a1 = 0 and a2 = 0. In measuring S11 and S21 port 2 is terminated in the characteristic impedance of the system . As well as measuring S22 and S12, port 1 is terminated in the characteristic impedance of the system . By varying the terminations of a network, the S-parameters values are not affected but could vary the reflection coefficient at a port.
Figure ..: reflection and transmission
Is a complex number, which is between 0 and 1.
VSWR = Vmax/Vmin = (1+â”‚Γâ”‚)/ (1-â”‚Γâ”‚)
Power being transferred to a load from a line is quantified by four factors: VSWR, mismatch, reflection coefficient and return loss.
Voltage standing wave ratio (VSWR) from equation… defines a ratio of maximum voltage to minimum voltage of the standing wave.
Voltage, current or power emanating from source impedance (ZS) and being delivered to a load (ZL) can be regarded as the sum of incident and reflected waves traveling in opposite directions along a transmission line of characteristics impedance Zo  The degree of mismatch between Zo and ZL or ZS determines the amount of incident wave reflected
When ZL is equal to Zo the incident wave is absorbed at the load (ZL) and no reflected wave are produced, therefore Γ equals zero and VSWR is 1:1.
If ZL and Zo are not the same, a small portion of the incident wave is absorbed at the load and a portion is reflected back to the source. In this situation a standing wave is produced when power is propagated back to source which could lead to components and equipment getting damaged. Mismatch of impedance between load and source, open circuit and short circuit can cause reflection of waves and the reflection coefficient (Γ) will be equal to one. In worst case scenarios, VSWR measures infinity.
If ZS and Zo are equal then the wave reflected from ZL is absorbed at the source with no reflections occurring any further.
When ZS differs from Zo, a portion of the wave is reflected from load (ZL) to source (Zs) and a portion is reflected back from source to load.
RL = -20 log â”‚Γâ”‚
Return loss is a measure in dB of the ratio of power in the incident wave to that in the reflected wave, and we define it to have a negative value .
Mismatch loss = 10 log (1- ρ2)
This is a measure of how much the transmitted power is attenuated due to reflection .
1.2.11 LNA Design Trade-off
The simultaneous requirement for low noise figure, high power gain, excellent input and output matching, minimum current draw, high 1 dB compression point and high third order intercept point is a serious challenge to achieve when designing a LNA. By choosing the appropriate active device a part of the trade-off parameters can be accomplished.
To achieve an excellent noise performance value during a LNA design, minimum collector current must be utilized. Whilst a minimum collector current is used, a low third order intercept point and 1 dB compression point will be achieved.
When designing LNA for maximum gain, maximum collector current must be utilized which will directly affect the third order intercept point and 1 dB compression point to be of a higher value. The disadvantage of using maximum collector current is that the noise performance will be very poor.
If the active device is made conditionally stable by resistively loading the input of the device, then the noise performance degrades but the stability of the device improves. Resistively loading the output of the active device degrades the power gain and output 1 dB (OP1dB) point.
To achieve maximum gain the source is complex conjugately matched to the input reflection coefficient that is, (ΓSm =Γi*) and the load is complex conjugately matched to the output of the amplifier, that is (ΓLm = Γo*). This method degrades the noise performance but improves the input and output Voltage Standing Wave Ratio (VSWR).
From the statements above it is clearly stated that there are a lot of conflicting parameters, and one parameter is affected by a change in another parameter. The designer should make decisions on sacrificing one parameter for another parameter aswell as utilizing data sheets as a baseline to achieve expected results. Data sheets provide important results and facts about the active device over a range of frequencies. At times not all the information regarding the active device is presented on data sheets.
3. Low Noise Amplifier Design for Maximum Gain Procedure
3.1 Design Procedure
It is off great importance to have a solid procedure in designing the amplifier until the final stage of physically building the design. By utilizing the following steps proper planning and execution can be achieved.
Define specifications of the design, viewing data sheets would be of great assistance
Carefully select an appropriate active device
Simulate S-parameters and compare data sheet S-parameters
Stabilize the chosen active device
Design input matching and out matching networks
Design appropriate DC biasing network
To realize the specification of the design, perform computer simulations
Finally construct and test the design to validate results to specifications
If tested results do not correlate with specifications, the following steps above should be revisited.
Single polarity DC supply
> 15 dBm
> 5 dBm
> 24 dB
< -25 dB
< -25 dB
3.2 Selecting active device
Selecting the correct manufacturer who is capable of supplying the products in a reliable time period is the stepping stone to the design because the active device is the final limiting factor, and is therefore wise to choose the most appropriate active device which will assist the designer in achieving desired specifications. Since this design was below 1 GHz the new technology surface mount NPN AT-41486 Bipolar Junction Transistor (BJT) from Avago Technology was chosen.
This active device was best suited for maximum gain design, based on its higher power gain, excellent linearity, good broad band capability and its cost effectiveness.
The non-linear model and S-parameter files were both available on the Avago Technology website which was easy accessible and utilized in Advance Design System (ADS) computer software to conduct linear and non-linear simulations.
Pin connections Plastic package AT-41486
3.3 Verifying S-parameters to data sheets S-parameters
It is off great importance to compare S-parameter values to the values illustrated on the data sheet at the correct biasing point. It could be at times that they do not correspond and could lead the entire design to not achieving design goals.
The S-parameter values accurately correspond to the data sheet values biased at VCE = 8 V and IC = 25 mA.
3.4 Stabilize active device
The S-parameter file t414868b.s2p was downloaded from Avago Technology website for AT-41486 BJT and was simulated as a two port network. The active device was swept over a range of desired frequencies to check if it was stable at the operating frequency of 433 MHz.
Figure. Two port simulation of active device tested for stability
Table..: S-parameter interpolated for unstable active device
The S-parameter values of AT-41486 BJT were interpolated at 433 MHz for biased conditions of VCE = 8 V and IC = 25 mA. These results were used to calculate the Rollet stability factor (K) and the magnitude of Delta (Δ).
Figure…: simulated K and |Δ| for unstable active device
Results from figure …. evidently shows K =0.640 and |Δ| = 0.221 which concludes that the active device is potentially unstable at the desired frequency. A great chance of oscillation may occur at the desired frequency but to prevent this phenomenon from occurring a resistor was connected in shunt with the collector of the active device to ground. The input of the active device was not chosen to be resistively loaded stabilized since it will cause additional noise to the circuit.
Figure ..:Simulation of Maximum available gain
Maximum available gain is an indication if the active device can produce enough gain for the application. AT-41486 BJT produces a maximum available gain of 30.121 dB without matching networks, at 433 MHz which meets the specification of the design comfortably.
To determine the value of the shunt resistor connected to the output of active device, a source and load stability circle were plotted on a smith chart. Then a constant conductance circle was plotted as close to the load stability circle without intersecting it as shown in figure…...
The constant conductance circle determines the conductance value which is the shunt resistance of maximum value. The value of normalized resistance computed was 283.33 â„¦. The blue portion of the source stability circle and the red portion of load stability circle illustrate the unstable region of the smith chart. The stability circles are affected by both frequency and bias conditions.
From the E12 range decade standard resistors a 270â„¦ value was chosen as the stabilizing resistor as shown in figure. A new set of S-parameters were computed which were utilized to calculate K and |Δ|.
Figure ..: Simulated K and |Δ| confirming stability of active device
Marker 1 clearly verifies that K is greater than unity and marker 2 shows |Δ| less than unity. Manufacturers by all means avoid constructing active devices with both K and |Δ| being > 1 by integrating matching networks inside the casing of the active devices. This active device is now certified as being conditionally stable at 433 MHz. Unconditional stability refers to the situation where the amplifier remains stable throughout the entire domain of the smith chart at the selected frequency and bias conditions , and this statement stands for both input port and output port. Any load can be presented to the output of this active device and no oscillation would take place at the desired frequency of operation.
The disadvantage of stabilizing the active device would degrade the noise figure because of the additional resistor generating thermal noise which can then affect either input or out impedance matching and could also result in power flow loss.
Figure ….: Entire smith chart being stable region
S-parameters were once again interpolated after adding the shunt 270 â„¦ resistor to the design at 433 MHz which was used to calculate of K and |Δ| shown below.
Figure. : Two port simulation of active device with stabilizing resistor
Load stability and Source a stability circle were once again simulated, and has now moved off the smith chart which makes the entire smith chart a stable region of operation.
3.5 Matching networks
Table …: S-parameter interpolated after stabilizing the active device
If S12 was an insignificant value (S12 = 0) then the unilateral method of amplifier design could have been used. By having S12 set to 0, a great chance of imprecise design could be achieved.
Bilateral design takes S12 value into consideration, since it is a great value that can not be ignored. The S-parameter values are substituted into equation…..below to calculate matched source reflection coefficient (ΓSm) and matched load reflection coefficient (ΓLm).
B1 = 1 + |S11|2 - |S22|2 - |Δ|2
B2 = 1 + |S22|2 - |S11|2 - |Δ|2
C1 = S11 - ΔS22*
C2 = S22 - ΔS11*
Δ = S11S22 - S12S21
SmGamma1 represents ΓSm and SmGamma2 represents ΓLm
To achieve maximum gain the source is complex conjugately matched to the input reflection coefficient of the active device which is, (ΓSm =Γin*) and the load is complex conjugately matched to the output of the amplifier, that is (ΓLm = Γout*)
Γin*= ΓSm =0.758/-147.718 ΓLm=0.686/38.629
ΓSm=0.758/147.718 Γout*= ΓLm =0.686/-38.629
3.6 Matching L-network
Software named, L-Network impedance matcher v.1 by Justine Grant was utilized to design L-pad matching networks. Resistors are not used in the designing of matching networks since they add a lot of noise to the circuit.
Figure : input matching network
Figure : output matching network
The active including ideal matching networks were then designed and simulated
Input return loss (S11) was simulated and displayed by marker 1 and Output return loss (S22) displayed by marker 2. Stunning results are shown which are in excess of -25 dB. Both input and output return loss demonstrated values of being in range as stated in specifications. At 433 MHz, the transducer power gain (S21) displayed by marker 3 showed a gain of 27.718 dB.
Once again the design is simulated but this time making use of s2p files containing S-parameter values which describe linear networks that are frequency dependant. The input return loss value degenerated whilst the output return loss value improved. The power gain reduced slightly, but all specifications are still within close proximity to design specifications.
3.7 DC Biasing
The non-linear model of the active device AT-41486 BJT was swept over a range of VCE and IC values. From simulation results in figure…. Marker 1 was placed at a chosen VCE which was 8 V. At that point IC measured 25.14 mA and IB measured 250 μA. This method was used to check if the non-linear file correlated to the biasing values displayed on the data sheet and it did correlate.
The topology chosen for this amplifier design was a voltage feedback constant current for a bias point of VCE = 8 V and IC = 25mA. A non-linear model of the active device was used to simulate the DC characteristics. After simulating, VCE measured 8.06 V and IC measured 24.8 mA. These values are relatively close to the bias points chosen.
Optimized final circuit
The final circuit modified is shown in figure… which includes matching networks and DC biasing circuit. The modification did not affect the performance of the design. It is important that the DC bias circuit should not interfere with the RF signal and the RF matching circuitry should not compromise the DC bias circuit[rad3pg4-9]. The use of minimum components will save on cost; therefore this circuit was optimized, by flipping the stabilizing resistor (R5) and the inductor (L2) on the output matching upwards. By this smart technique, the inductor acts as a RF choke and assist in output matching. Inductor (L2) acts as a DC feed which has a lower resistance path than resistor (R5), this method avoids resistor (R5) from having an effect on the DC biasing network. Capacitor (C3) was placed to bypass RF to ground and preventing it from propagating into the DC supply. Input capacitor (C1) and output capacitor (C2) function as part of the input and output matching networks aswell as DC blocking preventing damages to adjacent circuitry.
3.8 AT-41486 NPN BJT Die-model
A non-linear model of AT-41486 BJT which is also known as a zap file consists of a die-model was accessed from the Avago Technology website. This non-linear file is used for DC biasing and all non-linear simulations on ADS.
3.9 Comparison between S-parameter model and Non-linear model for AT-41486 NPN BJT
A DC bias point at VCE = 8 V and IC = 25 mA, the S-parameter model (s2p file) was compared to the non-linear model (die-model). The both models were swept over a range of frequencies.
The red colour trace symbolizes the non-linear results and blue colour trace symbolizes linear results.
Input reflection coefficient Output reflection coefficient
Forward reflection coefficient Reverse reflection coefficient
From the results above, a conclusion can be made that the output reflection coefficient (S22) is slightly off which will have an affect on the predictions of the output matching but the rest of the parameters is a precise representation of AT-41486 NPN BJT
4. Simulated results
4.1 DC biasing simulation
The DC bias parameters were simulated using the non-linear model of AT-41486 NPN BJT. The collector current (IC) and collector emitter voltage (VCE) simulated values of 24.8 mA and 8.06 V.
4.1 Amplifier Gain
The transducer gain, which is also known as forward transfer function (S21) was swept from 200 MHz to 800 MHz. At the design frequency 433 MHz, the gain measured was a spectacular value of 27.652 dB which means that the signal at the output port is in the region of 500 times bigger than the signal at the input port.
4.2 Input and output return loss
The source is complex conjugately matched to the input reflection coefficient and the load is complex conjugately matched to the output of the amplifier. The input reflection coefficient (S11) displayed by marker 3 and output reflection coefficient (S22) displayed by marker 4, were calculated as -28.448 dB and -26.713 dB which were relatively good.
4.3 Stability of design
The final circuit is stable at 433 MHz, therefore no oscillations will occur
The VSWR at input port and output port displayed excellent values of 1.079 and 1.097, since the VSWR is close to value of 1; this also means good matching at input port and output port of which will enable maximum power transfer from source to the load.
4.5 dB compression point (P1dB)
The circuit above consists of a DC biasing network, matching networks and a non-linear active device AT-41486 BJT. This circuit is compressed into one block which will simplify and prevent puzzlement when having to simulate for non-linear measurements. The circuit above exist in box shape named, complete_circuit_16v_41486_compressed as shown below
The input carrier of 433 MHz is set to be swept between -100 dBm to +10 dBm in steps of 0.01 dB by the sweep plan simulation icon. The internal source has a resistance of 50â„¦. The XDB simulation block is used to measure gain compression and is set at 433 MHz with correct input and output powers. An order of 7 harmonic amplitudes was chosen, so that a realistic model can be constructed by Fourier series. If the order is to low errors would occur and using a to high order will take plenty of time for the simulation process to be completed.
Figure ..: Seven harmonic frequencies including output power in dBm.
The first frequency which is 0 Hz is DC therefor states invalid in the table. At 433 MHz the output power is 9.725 dBm.
At 1 dB compression point the input and output power were as follows
Figure..: Gain compression curve including linear gain curve
Marker 1 and marker 2 are placed having an input power of -16.920 dBm. Marker 1 displayed the 1 dB compression at 9.72 dBm
Marker 4 was placed on the constant part of figure ….which displayed a gain of 27.642 dB then marker 3 is placed 1 dB below marker 4 which was the input P1dB (IP1dB) gain of 26.644 dB. The input power at this point is -16.920 dBm.
The output P1dB (OP1dB) can be calculated by adding the gain at marker 3 which is the IP1dB point to the input power at that point.
OP1dB = (26.644 dB-16.920 dBm) = 9.724 dBm
4.6 Third order intercept point (IP3)
The same procedure has been done to figure … to obtain a …..
The source consists of two equal power tones, the variable RF (VAR1) is 433 MHz and the power level is set to -30 dBm. A termination of 50â„¦ is set at the output of the circuit. Both the tones will have spacing off 35 MHz.
The fundamental tone is placed at 450.5 MHz and the third order product is placed at 485.5 MHz.
The intermodulation distortion(IMD) product was calculated to be -56.207dBc
Another option is to place a
series resistor in the input at the expense of noise figure.