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The possibility of achieving high breakdown voltages on advanced CMOS processes has increased importance as the maximum operating supply voltage decreases. Power management, display drivers and automotive applications require the integration of high voltage and power components into standard CMOS technology. However, the development of mixed mode or power integrated circuit for high-voltage applications is still resorting to dedicated and expensive technologies, like BCD, Bi-CMOS and high-voltage CMOS . The dedicated process is extremely complex and very costly. A common solution consists of modifying a low-voltage CMOS technology to accommo-date a high-voltage option . This approach usually requires the addition of supplementary masks and im-plantation steps, resulting in an expensive technology. To minimize cost and process complexity, it is preferred to realize these devices and determine their performance by layout only [3,4].
Furthermore, in current advanced technologies, the method for device isolation is to use an oxide filled shallow trench around the transistors. The lack of local oxidation of silicon (LOCOS) means that field plate techniques cannot be used to reduce the electric field near the gate edge. CMOS compatible high-voltage devices using ex-tended drain and designed for LOCOS technologies cannot be integrated with shallow trench isolation (STI) . With the progress of technology development towards smaller geometry, the increasing conflict in well profiles makes integration of low- and high-voltage devices in a single-technology platform increasingly difficult. Therefore high-voltage device development is getting more challenge.
In this paper, high-voltage NMOS and PMOS devices with STI based on 0.25 mm/5 V standard CMOS technology have been proposed and characterized. No process modification and no additional mask have been made to the standard CMOS processing steps. These high-voltage devices have been designed and optimized by process and device simulations and their performances have been verified experimentally in a 0.25 mm/5 V standard CMOS technology.
II.PROCESS TECHNOLGY AND DEVICE STRUCTURE
The design of high-voltage MOS device is based on 0.25 mm/5 V standard CMOS technology. This process includes low-doped p-type substrate, one layer of poly, four layers of metal available for interconnection and retrograde twin-well. Isolation between devices is imple-mented using STI technology.
A cross section of the high-voltage NMOS device is shown in Fig. 1. As can be seen, the device is formed in a lightly doped p-type substrate. The poly silicon gate extends over the thin gate oxide and terminates on STI region in consider of mask misalignments. An oxide filled trench (STI) along drift region is introduced to separate the channel and n+ drain region. The source and channel regions, including the thin gate oxide, are identical to those of standard NMOS devices. Therefore, its gate can be driven by standard logic level inputs as well.
High-voltage blocking capability is obtained by combin-ing the existing technological layers to create buffer regions. Firstly, in order to withstand high drain-to-source voltage, the drain region is separated from the edge of the channel by a lightly doped buffer region formed by the n-well implant. This is normally called extended drain MOS device. Due to the presence of the n-well buffer region, critical electric field is reached at drain voltages well above the standard low-voltage NMOS breakdown vol-tage. The top layout view of high-voltage NMOS device with extended drain is shown in Fig. 2(a). This arrange-ment reduces the electric field when the device is blocking a drain voltage. The disadvantage is the increased specific on resistance at the same time.
Secondly, as shown in Fig. 2(b), the interface of channel/ drift regions is implemented by inter-digitated p-well and n-well pillars for further breakdown improvement.
Figure. 1. Cross section of high-voltage NMOS device.
Figure. 2. Top layout view of high-voltage NMOS device.
Figure. 3. Cross section of high voltage PMOS device
Figure. 4. Top layout view of high-voltage PMOS device.
This is in contrast to the case in Fig. 2(a) where only channel/drift region junction function to deplete the drift region. The availability of inter-digitated p-well and n-well pillars has enabled lateral depletion therefore the depletion layer will widen. Consequently the electric field lowers and the breakdown voltage increases. Obviously, if the n- and p-well pillars width Li used is short enough, the breakdown voltage can be raised to a higher value due to fully depletion of n and p pillars. However these pillars width are mandated by the technology design rules of the process used, in which the minimum width of the pillars is 1.2 mm.
The high-voltage PMOS device structure and top layout view shown in Figs. 3 and 4 are identical to its NMOS counterparts. The lightly doped p-type buffer region is formed by the p-well implants that provide the higher breakdown voltage blocking capability than standard low-voltage PMOS device. The interface of channel/drift regions is implemented by inter-digitated n and p-well pillars for higher breakdown voltage. The high-voltage PMOS device can achieve the same breakdown voltage as NMOS device due to the similar device structure. These high-voltage NMOS and PMOS structures are easily obtained by layout manipulation with no additional mask and no changing of design rules.
III.DEVICE SIMULATIONS AND OPTIMIZATION
Process simulations were first carried out to generate the doping profile for the process used. The doping profiles have been calibrated using secondary ion mass spectro-scopy (SIMS) measurements to ensure their accuracy. The doping profile generated then transferred to device simulator Taurus-device to study the performance of the high-voltage devices.
Since the existing standard CMOS technology has been designed for optimum operation of the low-voltage devices and cannot to be altered. The simulations focused on achieving the highest possible breakdown voltage assuming the minimum length (mandated by the technology design rules of the process used) for all the layout parameters, thus achieving the lowest possible specific on resistance.
Four parameters are of key importance for controlling the electrical behaviors of the high-voltage NMOS devices. These layout parameters include the channel length Lc, the drift region length Ld, the overlap length Lw of thin oxide over drift region and inter-digitated p and n pillars width Li. As for inter-digitated p and n pillars width Li, it should be as short as possible for achieving the highest breakdown voltage. Therefore it is not necessary to perform 3-D process and device simulation and optimization for these high-voltage MOS device by using the minimum pillars width defined by design rules. However in consideration of the design rule of the process used, the minimum Li width is 1.2 mm (much larger than what is needed to fully deplete the pillars effectively). Consequently the breakdown voltage of high-voltage MOS device with inter-digitated extended drain cannot be raised too high.
The effects for other three layout parameters on the specific on resistance of the high-voltage MOS device are relatively straightforward. An increase in channel length Lc, overlap length Lw and drift region length Ld result in an increase in channel resistance and drain resistance, leading to a high specific on resistance. The overlap length Lw is the most important layout dimension for controlling device breakdown performance. The decrease in the breakdown voltage of the high-voltage NMOS device with increasing Lw results from the increased electric field under thin gate oxide. However, the breakdown voltage of the high-voltage MOS device does not increases with increasing channel length Lc and drift region length Ld. It was found through simulations that both parameters had negligible effect on the breakdown voltage of the high-voltage device. Because the high-voltage device suffers from breakdown which is located near the channel, the effects of Ld on the breakdown voltage becomes insignificant. The limitation for channel length Lc is that it must be increased to avoid channel punch through.
The 2-D potential contours at the onset of avalanche breakdown, for the high-voltage NMOS device with optimized layout dimensions (Lc, Ld, Lw) are illustrated in Fig. 5. The potential between each line is 2 V. As shown in Fig. 5, the existing of low-doped n-well region reduces electric fields which leading to a relatively high breakdown voltage of 17 V in the high-voltage NMOS device.
Figure. 5. Potential contour of high-voltage NMOS at breakdown.
Figure. 6. Potential contour of high-voltage PMOS at breakdown.
Figure. 7. Measured on stage I-V characteristics of high-voltage NMOS.
The 2-D potential contours at the onset of avalanche breakdown, for the high-voltage PMOS device with optimized layout dimensions (Lc, Ld, Lw) are illustrated in Fig. 6. The potential between each line is â‚ƒ2 V. As shown in Fig. 6, the existing of low-doped p-well region reduces electric fields which leading to a relatively high breakdown voltage of â‚ƒ17 V in the high-voltage PMOS device.
The high-voltage NMOS and PMOS devices have been fabricated in standard 0.25 mm/5 V technology. The mea-sured breakdown voltages of high-voltage NMOS and PMOS with extended drain reach to 17 and â‚ƒ17 V, respectively. It fit very well with device simulation results. Fig. 7 shows the on-state I-V characteristics of high-voltage NMOS device with inter-digitated extended drain. This device exhibits a breakdown voltage of about 20 V. It is about 15% larger than the device structure without inter-digitated extended drain. The cell pitch of the high-voltage NMOS device is about 5 mm, and its specific on resistance is about 1.06 mO cm2. Fig. 8 shows an on state I-V characteristics of high-voltage PMOS device with inter-digitated extended drain. The breakdown voltage is about â‚ƒ20 V, while the high-voltage PMOS device without inter-digitated extended drain show a breakdown voltage of â‚ƒ17 V. The high-voltage PMOS device has a cell pitch of 5 mm and specific on resistance is about 2.83 mO cm2. It should be noted that these optimized high-voltage MOS devices are cost-effective because of their full compatibility with the existing process.
Figure. 8. Measured on stage I-V characteristics of high-voltage PMOS
High-voltage NMOS and PMOS devices fully compatible with 0.25 mm/5 V standard CMOS technology have been designed and characterized. The device layout parameters in proposed high-voltage NMOS and PMOS are optimized to achieve highest performance possible in terms of breakdown voltage and specific on resistance. The high-voltage NMOS using unit-cell pitches of 5 mm achieve breakdown voltage of 20V and specific on resistance of 1.28 mO cm2. The high-voltage PMOS using unit-cell pitches of 6 mm achieve breakdown voltage of â‚ƒ20 V and specific on resistance of 3.40mO cm2. Due to their full compatibility with the existing process, the high-voltage MOS devices can be implemented without any increase of manufacturing cost. Analog and power integrated circuit designers could continue to resort to low cost and accessible advanced CMOS for high-voltage applications.