# Design A Digital Circuit Of Electronic Synchronous Counter Engineering Essay

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## Abstract:-

This report is to design a digital circuit of electronic synchronous counter. The synchronous of 4 bits have to convert numeric to binary numbers by using my student ID of Caledonian College Of Engineering. I'm going to design the circuit by using synchronous counter of JK flip-flop.

The report will be achieved in six steps:-

Firstly, I have to draw the state diagram by using student number and convert it to binary. As shown in bellow table :-

Binary

Numerical

0

0000

8

1000

9

1001

1

0001

Secondly, I have to tabulate the next state table. Then from excitation table of JK we can find the Flip-flop excitation table. After that I can sketch the K-map simplification to get the value of J3, K3, J2, K2, J1, K1, J0, K0. Next I will get the logic expression from the K-map. Finally I have to draw the circuit diagram by using orcad program and simulate the circuit to get the output of the student number.

## Objective of this report is:-

To design the JK flip-flop counter by using student ID.

## A physical description of the circuit:-

The physical description of the circuit I get it by some steps:-

First, after i got the value from k-map, the value was:-

J3 = Q0

K3 = Q0

J2 = 0

K2 = 0

J1 = 0

K1 = 0

J0 = Q3

K0 = Q3

after i got these values i drew the circuit in the Orcad program by using 4 JK Flip-Flop counter and i connected the value which i got from the K-map in the circuit by using wires which J3 is connected to Q0, K3 is connected to Q0, J2 K2 J1 K1 are connects to law source, J0 is connected to Q3 and K0 is connected to Q3.

After that I connected the all CLK by wires to the digital clock and i changed the value of digital clock from .5us to .5ms and for the CLR i connected to the high source.

Then i put VCC in the CLK and in every Q point and I named as the VCC for clock I named as CLK, the VCC that I put it to all Q point I named as Q3 Q2 Q1 Q0.

Next I pressed a new simulation profile and i created a name by 08911 then i changed the run to time from 1000ns to 30ms then i pressed an option next pressed the Gate-level simulation and i changed initialize all flip-flops to 0. Then in the last i pressed Run PSpice. Finally I pressed Add Trace the i clicked on CLK, Q0, Q1, Q2, and Q3 then i pressed OK to get the output that contain my student number 0891 (0000, 1000, 1001, 0001).

## Technical content:-

## Introduction:-

Aim of this report is to build and investigate the working principle of a synchronous counter by using Orcad program and design the circuit along with finding the output for it.

Counters are generally made up of flip flops and logic gates digital counter are classified as sequential circuit flip flops can occupy one of only two possible states while counter can have more than that. In counters the value of state is expressed as multidigit binary numbers which are 1's and 0's. The number of state a counter is limited only by the available amount of electronic hardware. There are two types of flip flop, J-K flip flop and T flip flop, the J-K flip flop are both J and K input tied together. Example for JK flip-flop showing in figure bellow:-

Flip flop counters have many applications. Generally they are used in digitals clocks and measuring the flow rate of auto traffic on roads.

There are two types of counters (Asynchronous counters and synchronous counters), the best one is the one whose flip flops are clocked at the same time and this counter is called synchronous. There are three main functions for counters in a digital circuit:

Timing

Sequencing

Counting

In a simple way counter is semiconductor device that is use for counting the number of times a digital event has occurred. The output of the counter's is indexed by one LSB every time when the counter is clocked. A simplified way of applying the logic for each bit for an ascending counter is for each bit to toggle when all the less significant bits are having logic high state.

Figure 1

for this counter implementation the output is 1 2 5 7

The advantage of Synchronous counters is that, there is no cumulative time delay because all flip flops are triggered in parallel. There for the maximum operating frequency for the count will be significantly high more than for its corresponding ripple counter.

## Theory :-

## Truth table for Student ID:-

The truth table is from 0 to 9. In Which the number of cells for a 4 variable input combination is.

## Present State

## No.

## Q3

## Q2

## Q1

## Q0

## 0

0

0

0

0

## 1

0

0

0

1

## 2

0

0

1

0

## 3

0

0

1

1

## 4

0

1

0

0

## 5

0

1

0

1

## 6

0

1

1

0

## 7

0

1

1

1

## 8

1

0

0

0

## 9

1

0

0

1

This truth table will help me to get the possibilities out of the flip-flop circuit that what I have to do.

0-8-9-1

## Step1:-

The state diagram:

## 0000

## Qn Qn+1

## J K

## 0 0

## 0 X

## 0 1

## 1 X

## 1 0

## X 1

## 1 1

## X 0

## 1001

## 0001

## 1000

## Step2:-

Next state table:

Present state

Q3 Q2 Q1 Q0

Next state table

Q3 Q2 Q3 Q4

0 0 0 0

1 0 0 0

1 0 0 0

1 0 0 1

1 0 0 1

0 0 0 1

0 0 0 1

0 0 0 0

The Next State table shows the outputs of the 4 flip-flops.

## Step3:-

Flip flop excitation table:

J3 K3

J2 K2

J1 K1

J0 K0

1 X

0 X

0 X

0 X

X 0

0 X

0 X

1 X

X 1

0 X

0 X

X 0

0 X

0 X

0 X

X 1

The flip-flop excitation table help me to get the K-map

## Step4:-

K-Map simplification:

The K-map simplification helps me to get the value of (J3, K3, J2, K2, J1, K1, J0, K0 )

J3 Map:-

Q1 Q0

Q3 Q2

00

01

11

10

00

1 0

0 1

X 3

X 2

01

X 4

X 5

X 7

X 6

11

X 12

X 13

X 15

X 14

10

X 8

X 9

X 11

X 10

J3 = Q0

K3 Map:-

Q1 Q0

Q3 Q2

00

01

11

10

00

X 0

X 1

X 3

X 2

01

X 4

X 5

X 7

X 6

11

X 12

X 13

X 15

X 14

10

0 8

1 9

X 11

X 10

K3= Q0

J2 Map:-

Q1 Q0

Q3 Q2

00

01

11

10

00

0 0

0 1

X 3

X 2

01

X 4

X 5

X 7

X 6

11

X 12

X 13

X 15

X 14

10

0 8

0 9

X 11

X 10

J2 = 0

K2 Map:-

Q1 Q0

Q3 Q2

00

01

11

10

00

X 0

X 1

X 3

X 2

01

X 4

X 5

X 7

X 6

11

X 12

X 13

X 15

X 14

10

X 8

X 9

X 11

X 10

K2 = 0

J1 Map:-

Q1 Q0

Q3 Q2

00

01

11

10

00

0 0

0 1

X 3

X 2

01

X 4

X 5

X 7

X 6

11

X 12

X 13

X 15

X 14

10

0 8

0 9

X 11

X 10

J1 = 0

K1 Map:-

Q1 Q0

Q3 Q2

00

01

11

10

00

X 0

X 1

X 3

X 2

01

X 4

X 5

X 7

X 6

11

X 12

X 13

X 15

X 14

10

X 8

X 9

X 11

X 10

K1 = 0

J0 Map:-

Q1 Q0

Q3 Q2

00

01

11

10

00

0 0

X 1

X 3

X 2

01

X 4

X 5

X 7

X 6

11

X 12

X 13

X 15

X 14

10

1 8

X 9

X 11

X 10

J0 = Q3

K0 Map:-

Q1 Q0

Q3 Q2

00

01

11

10

00

X 0

1 1

X 3

X 2

01

X 4

X 5

X 7

X 6

11

X 12

X 13

X 15

X 14

10

X 8

0 9

X 11

X 10

K0 = Q3

## Step 5:-

J3 = Q0

K3 = Q0

J2 = 0

K2 = 0

J1 = 0

K1 = 0

J0 = Q3

K0 = Q3

## Circuit diagram :-

This the circuit that I have drew it after I get my value from the K-map

## Design with necessary sketch :-

This the circuit diagram with 1s and 0s.

## Simulation:-

After I drew the circuit diagram this is the output that I get it and it give me output 0891 as my student number

## List of component :-

4 JK flip-flop (7473)

Digital clock Source

HI Source

Low Source

## Conclusion:-

In this report I was able to learn to build and investigate the working principle of a synchronous counter by using Orcad program and design the circuit along with finding the output for it, which will help me to calculate the precise calculation for the report.

The aim of this report is achieved. The investigation of a synchronous counter is done and verified with the help of Orcad. To get the same count sequence the circuit is also redesigned. This investigation of flip flop counter shows that a 4 bit flip flop counter generates eight different possible states.

## Bibliography:-

The information for the report is taken from the following source :-

http://www.ask.com/wiki/Flip-flop_(electronics)

http://www.doc.ic.ac.uk/~nd/surprise_96/journal/vol1/cwl3/article1.html

Digital fundamentals, Thomas L. Floyd.

## Appendix :-

## There are two appendix:-

## Appendix 1

## Appendix 2

## Appendix 1 :-

## The output file of simulation :-

**** 12/18/10 15:27:53 ******* PSpice 15.7.0 (July 2006) ****** ID# 56424836 *

** Profile: "SCHEMATIC1-08911" [ c:\users\ahmed\desktop\jaleeloo ee2 part b\orcad design\jaleeloo-PSpiceFiles\SCHEMATIC1\08911.sim

**** CIRCUIT DESCRIPTION

## ******************************************************************************

** Creating circuit file "08911.cir"

** WARNING: THIS AUTOMATICALLY GENERATED FILE MAY BE OVERWRITTEN BY SUBSEQUENT SIMULATIONS

*Libraries:

* Profile Libraries :

* Local Libraries :

* From [PSPICE NETLIST] section of C:\OrCAD\OrCAD_15.7\tools\PSpice\PSpice.ini file:

.lib "nom.lib"

*Analysis directives:

.TRAN 0 30ms 0

.OPTIONS DIGINITSTATE= 0

.PROBE V(alias(*)) I(alias(*)) W(alias(*)) D(alias(*)) NOISE(alias(*))

.INC "..\SCHEMATIC1.net"

**** INCLUDING SCHEMATIC1.net ****

* source JALEELOO

X_U1A CLK $D_HI N00670 Q0 Q3 N01048 $G_DPWR $G_DGND 7473 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_U1B CLK $D_HI $D_LO $D_LO Q2 M_UN0001 $G_DPWR $G_DGND 7473 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_U2A CLK $D_HI $D_LO $D_LO Q1 M_UN0002 $G_DPWR $G_DGND 7473 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

X_U2B CLK $D_HI Q3 N01048 Q0 N00670 $G_DPWR $G_DGND 7473 PARAMS:

+ IO_LEVEL=0 MNTYMXDLY=0

U_DSTM1 STIM(1,1) $G_DPWR $G_DGND CLK IO_STM IO_LEVEL=0

+ 0 0

+ +.5mS 1

+REPEAT FOREVER

+ +.5mS 0

+ +.5mS 1

+ ENDREPEAT

**** RESUMING 08911.cir ****

.END

**** 12/18/10 15:27:53 ******* PSpice 15.7.0 (July 2006) ****** ID# 56424836 *

** Profile: "SCHEMATIC1-08911" [ c:\users\ahmed\desktop\jaleeloo ee2 part b\orcad design\jaleeloo-PSpiceFiles\SCHEMATIC1\08911.sim

**** Digital Gate MODEL PARAMETERS

## ******************************************************************************

D0_GATE D_73_4 D_73_3

TPLHMN 0 6.000000E-09 2.400000E-09

TPLHTY 0 6.000000E-09 6.000000E-09

TPLHMX 0 6.000000E-09 6.000000E-09

TPHLMN 0 0 2.400000E-09

TPHLTY 0 0 6.000000E-09

TPHLMX 0 0 6.000000E-09

**** 12/18/10 15:27:53 ******* PSpice 15.7.0 (July 2006) ****** ID# 56424836 *

** Profile: "SCHEMATIC1-08911" [ c:\users\ahmed\desktop\jaleeloo ee2 part b\orcad design\jaleeloo-PSpiceFiles\SCHEMATIC1\08911.sim

**** Digital Gated FF MODEL PARAMETERS

## ******************************************************************************

D_73_1 D_73_2

TPDQLHMN 0 0

TPDQLHTY 0 0

TPDQLHMX 0 0

TPDQHLMN 0 0

TPDQHLTY 0 0

TPDQHLMX 0 0

TPGQLHMN 0 4.000000E-09

TPGQLHTY 0 10.000000E-09

TPGQLHMX 0 19.000000E-09

TPGQHLMN 0 7.600000E-09

TPGQHLTY 0 19.000000E-09

TPGQHLMX 0 34.000000E-09

TPPCQLHMN 0 4.000000E-09

TPPCQLHTY 0 10.000000E-09

TPPCQLHMX 0 19.000000E-09

TPPCQHLMN 0 7.600000E-09

TPPCQHLTY 0 19.000000E-09

TPPCQHLMX 0 34.000000E-09

TWGHMN 0 0

TWGHTY 14.000000E-09 47.000000E-09

TWGHMX 14.000000E-09 47.000000E-09

TWPCLMN 0 0

TWPCLTY 25.000000E-09 25.000000E-09

TWPCLMX 25.000000E-09 25.000000E-09

TSUDGMN 0 0

TSUDGTY 0 0

TSUDGMX 0 0

TSUPCGHMN 0 0

TSUPCGHTY 0 0

TSUPCGHMX 0 0

THDGMN 0 0

THDGTY 0 0

THDGMX 0 0

**** 12/18/10 15:27:53 ******* PSpice 15.7.0 (July 2006) ****** ID# 56424836 *

**** Digital IO MODEL PARAMETERS

## ******************************************************************************

IO_STM IO_STD

DRVL 0 104

DRVH 0 96.4

AtoD1 AtoD_STD

AtoD2 AtoD_STD_NX

AtoD3 AtoD_STD

AtoD4 AtoD_STD_NX

DtoA1 DtoA_STM DtoA_STD

DtoA2 DtoA_STM DtoA_STD

DtoA3 DtoA_STM DtoA_STD

DtoA4 DtoA_STM DtoA_STD

TSWHL1 1.511000E-09

TSWHL2 1.487000E-09

TSWHL3 1.511000E-09

TSWHL4 1.487000E-09

TSWLH1 3.517000E-09

TSWLH2 3.564000E-09

TSWLH3 3.517000E-09

TSWLH4 3.564000E-09

TPWRT 100.000000E+03 100.000000E+03

JOB CONCLUDED

**** 12/18/10 15:27:53 ******* PSpice 15.7.0 (July 2006) ****** ID# 56424836 *

**** JOB STATISTICS SUMMARY

## ******************************************************************************

Total job time = .09