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Multi Threshold Complementary Mosfet is a design technique to reduce leakage current in integrated circuit. This paper give analytical review on various solution models of MTCMOS design techniques and highlights design issues that bring effect to the circuit performances. Leakage current has become major concern in digital design and soon will dominate the total energy consumption of high performance ICs. Leakage power is a combination of the subthreshold leakage power due to the non ideal off state characteristics of the MOSFET switches and the gate leakage power caused by carrier tunnelling through the thin gate oxides. This technique based on disconnecting the low threshold voltage logic gates from the power supply and/or the ground line via cut off high threshold sleep transistor is also known as "power gating". Several MTCMOS circuit techniques has been proposed by considering many costs such as energy overhead, wake up delay, voltage, current and etc. Several techniques have been proposed that efficiently minimize this leakage power loss but each of the technique give some penalty or lead to another design issue. MTCMOS technique at certain extent has demonstrated significant improvements in standby power consumption in any gate or circuit level.
In modern high performance integrated circuits, more than 40% of the total active mode energy can be dissipated due to the leakage currents . With more transistors integrated on die, leakage currents will soon dominate the total energy consumption of high performance ICs. The subthreshold leakage current is one of the most dominant leakage current components . It is the drain to source leakage current when the transistor is off, i.e, the applied voltage Vgs is less than the threshold voltage Vt of the transistor (weak inversion mode). The subthreshold leakage current in short channel MOSFET can be expressed as follow 
Where is the drain current with Vgs =Vt. The subthreshold current depends on the transistor parameters as listed in Table 1 .
Transistor Width (W)
Transistor Length (L)
Transistor Threshold Voltage (Vt)
Increase by an order of magnitude with 100mV decrease
Input Voltage (Vgs)
Portable battery operated devices that have long idle times are particularly affected by this leakage power loss. Existing designs must therefore be modified in a way that it curbs the draining of battery current when it is not operational.
A popular low leakage circuit technique is the Multi threshold Voltage CMOS (MTCMOS) [1-27]. This technique based on disconnecting the low threshold voltage logic gates from the power supply and/or the ground line via cut off high threshold sleep transistor is also known as "power gating". Several MTCMOS circuit techniques has been proposed by considering many costs such as energy overhead, wake up delay, voltage, current and etc. The paper is organized is follows. The concept and operation of MTCMOS circuits are described in Section II. The design issues in MTCMOS circuits and previous works that are related to MTCMOS technique are presented in Section III and IV. Conclusions are offered in Section V.
II. MTCMOS CONCEPT
Multi threshold voltage CMOS (MTCMOS) reduces the leakage by inserting high threshold devices in series to low Vth circuitry . An MTCMOS circuit is shown in Figure 1. In an MTCMOS circuit, all of the logic transistors have low threshold voltages to enhance circuit speed. In order to suppress the high subthreshold leakage current characteristics of the scaled low threshold voltage transistors, high threshold voltage switches are added between the low threshold voltage logic circuits and the power supply and ground lines . These high threshold voltage power supply and ground switches are controlled by a sleep signal. A sleep control scheme is introduced for efficient power management. During the active mode of operation, the sleep control switches are activated, providing a virtual power and ground line for the logic circuits. Since their on resistance are small, the virtual power and ground line almost functions as real power line. During the standby mode, these high threshold voltage sleep control switches are turned off, reducing the subthreshold leakage current. This technique is also called power gating.
Figure 1: Schematic of MTCMOS circuit
In fact, only one type of high Vth transistor is enough for leakage control. Figure 1(b) and (c) shows the PMOS insertion and NMOS insertion schemes respectively. The NMOS insertion scheme is preferable, since the NMOS on resistance is smaller at the same width; therefore it can be sized smaller than corresponding PMOS. The effect of an on resistance NMOS sleep transistor in series with a low Vth circuit can be approximated very accurately by replacing the high Vth device with a single linear resistor, R as shown in Figure 2. During normal circuit operation, the virtual ground node is close to real ground, so Vds of the sleep transistor is small and the resistive approximation is very accurate 
Figure 2: Sleep Transistor modelled as resistor
III. DESIGN ISSUES IN MTCMOS CIRCUIT
A number of problems have been addressed in MTCMOS circuits that affect the performance of the circuits.
i) Voltage variation at virtual line
Figure 2 shows the sleep transistor modelled as resistor and it can gives us valuable insight into the relationship between sleep transistor size and circuit performance. When the inverter is discharging and neglecting the parasitic capacitance Cx, any charging flowing out of the source of M2 will flow through the sleep transistor R, including a voltage drop Vx. This voltage drop has two effects:
it reduces the gate drive from vdd to vdd-vx
it causes the threshold voltage of the pull down NMOS to increase die tu the body effect
Both change result in a decrease in the discharging current which slows the output high to low transition. To maximize performance, the resistor should be made as small as possible and consequently the transistor as large as possible .
. This will lead to other issue of sleep transistor size where large transistor size comes at the expense of large area and power overhead.
ii) Sizing sleep transistor
Sleep transistor is an important issue in designing the MTCMOS circuits. The power consumption, area and the performance are affected with each other at the same time. If the sleep transistor size is too large, the circuit performance can be maintained but the dynamic power consumption of the sleep transistor will increase. On the other hand, of the sleep transistor size is too small; there will be significant performance degradation because of the increased resistance to ground . The sleep transistor should be sized to attain adequate performance. In other words, the current flowing through the sleep transistor must be satisfactory to achieve sufficient speed. The worst case scenario takes place if all gates supported by the sleep transistors are simultaneously switching in time as shown in Figure 3. The sleep transistor exhibits maximum current then, which is the sum of the currents of the switching gates () (Case 1). The sleep transistor is thus sized up to contain the high current. If the gates are exclusively discharging (i.e. not discharging simultaneously in time), the sleep transistor is sized according to the maximum current of the mutually exclusive discharging gates (. The sleep transistor is much smaller in this case.
Figure 3: Sleep Transistor in MTCMOS circuit
iii) Distribution of Sleep Transistor
Applying MTCMOS design to a block can be done in several ways and it requires extra routing due to the virtual ground/power lines, and a sleep signal distribution. Global MTCMOS design Figure 4(a) controls the whole block via a large centralized single sleep transistor. Whereas, distributed MTCMOS design Figure 4(b) employs multiple sleep transistors for a single block. Distributed MTCMOS, can be applied in two ways:
a- cluster based is where a block is divided into clusters and each cluster has its own virtual power/ground and sleep device. Clustering is done based on the switching behaviour of the gates to minimize the total sleep transistor area.
b- network-based (also known as coarse grain) is where many distributed sleep transistor are inserted between the actual and virtual power/ground networks inside the block and these sleep transistor share discharge currents.
Figure 4: (a) Global MTCMOS design, (b) Distributed MTCMOS design
Different MTCMOS style presents different design tradeoffs. Global MTCMOS style has the lowest optimal total sleep transistor area. However, determining the optimal size of the global sleep transistor is hard, and impractical for large block. This leads to an over sized sleep transistor and reduces the efficiency for global MTCMOS in terms of area. Regarding signal integrity, global MTCMOS is also impractical since it suffers from degraded noise margin and large ground bounce in power/ground network. Global MTCMOS does not require intra block sleep signal routing but it suffers from high virtual power/ ground lines sizing and routing complexity.
Determining the optimal sleep transistor size for fine grain MTCMOS is easy but the area penalty is large. Fine grain MTCMOS does not require virtual power/ ground traces but the sleep signal has to be delivered to all gates. Although fine grain MTCMOS offer many desirable advantages in term of signal integrity and sleep transistor sizing complexity but it suffers from a large area penalty and it can only be considered when the sleep transistor area penalty can be tolerated. In distributed MTCMOS (cluster based or network based), the sleep distribution network present an overhead since the sleep signal has to be routed to all the sleep devices within the block. The sleep signal line consumes precious routing sources and increases the total intra block wirelength, which in turn increases design cost. The noise issue is critical for cluster based design since a single sleep transistor is shared by all the gates in the cluster. This in turn will degrade the signal integrity performance. The increased on resistance of the sleep device affects all the gates performance and if the noise occur during peak current switching of the cluster, functional failure might occur .
iv) Energy overhead during transition mode
In conventional MTCMOS circuits, switching mode consumes a significant amount of energy. The energy dissipation occurs while charging and discharging the parasitic capacitance of the virtual lines and the sleep transistors. The virtual power and ground lines have high capacitance due to the wire parasitic, the large number of transistors sharing a common sleep transistor, and the decoupling capacitors attached to the supply rails for voltage stabilization against bouncing. The parasitic capacitors are illustrated in Figure 5 with a single lumped capacitor attached to virtual rails. Figure 5 shows the MTCMOS circuits during the energy consuming mode transitions.
Figure 5: MTCMOS circuits during the energy consuming mode transitions. (a) Gated-ground circuit during the active-to-sleep mode transition. (b) Gated- VDD circuit during the sleep-to-active mode transition. High-Vt transistors are represented with a thick line in the channel region.
For the gated ground circuits, the virtual ground is maintained at a low voltage close to Vgnd in the active mode. In the sleep mode, the sleep transistor is cut off. The virtual ground is slowly charged to a steady state voltage close to Vdd by the leakage current of the low Vt gates (I1) as shown in Figure 5. A portion of the energy drawn from the power supply is dissipated in the parasitic impedance of the low Vt circuitry. The remaining portion of the drawn energy is stored at Cvirtual while placing the circuit into sleep. When the gated ground circuits are reactivated, the energy stored at Cvirtual is dissipated by the active NMOS sleep transistor while discharging the virtual ground.
For a full cycle of mode transitions (active-to-sleep-to-active or sleep-toactive-to-sleep), a significant amount of energy is dissipated for charging and discharging the virtual line. is
In addition to , the MTCMOS circuits also consume energy while charging and discharging the gate oxide capacitance of the sleep transistor during the mode transitions. The total energy overhead () due to a full cycle of mode transitions with he conventional MTCMOS circuits is
The total energy overhead is therefore dominated by and suppressing is critical for lowering the overhead of mode transitions in order to achieve effective energy reduction with the MTCMOS circuits .
v) Data loss during wake up state due to floating nodes appearance in MTCMOS circuits during sleep mode
The MTCMOS idea is straightforward for combinational logic but there are difficulties with sequential circuits. If the power supply is simply gated during sleep mode, the state of the circuit is loss and cannot be recovered when returning to active mode . The retrieval of the previously stored data for restoring a system to a pre sleep state costs significant energy and timing overheads when the MTCMOS sequential circuits are activated . The sudden surge current also exists in floating node and might violate the reliability of the circuit . One of the problems with sequential circuits that utilize feedback and parallel devices is that sneak leakage paths may exist. Sneak leakage path can arise in MTCMOS circuits whenever the output of an MTCMOS gate is electrically connected to the output of a CMOS gate. In fact, the interfacing between MTCMOS type circuits and CMOS type circuits is what gives rise to potential leakage paths .
IV. PREVIOUS WORKS
A number of methodologies have been reported in the literature to solve the issues that affect the performance of the MTCMOS circuit.
Several MTCMOS techniques based on charge recycling between the virtual rails and the sleep signal lines are presented in - for suppressing the energy overhead of mode transitions. These techniques require complicated timing control circuitry to enable charge recycling during the mode transitions. These techniques also significantly increase the system wake-up delay, thereby degrading the system performance. In ,, both gated vdd and gated ground techniques are employed in a charge recycling MTCMOS circuit. A pass transistor is placed between the virtual power and virtual ground to allow charge recycling. Another proposed technique is employed a pass transistor for charge recycling between virtual rails and sleep signal lines. The sleep transistor is driven by a tri-state buffer and a high-vt pass transistor is allowed charge recycling between virtual rail and sleep signal line.
Sequential MTCMOS circuits require more tought since they must hold state in standby mode. The previously published MTCMOS flip flop circuits that are capable of data retention in sleep mode utilizes a localized sleep switch circuit structure where high Vt NMOS and PMOS sleep transistors are inserted into both the master and the slave latches in order to eliminate the sneak leakage current paths during the sleep mode . Another approach uses the leakage feedback flip flop (LFBFF) in . The LFBFF uses feedback from the output to cut off one power rail conditionally during standby. Four design rules have been propose in  to prevent sneak leakage current in MTCMOS flip flops. These guideline allowing sleep device to be inserted locally without having leakage savings degraded by sneak leakage. The improved MTCMOS flip fops which providing a low leakage data retention sleep and simplified control circuitry as compared to the prevous published MTCMOS circuits is proposed in . A quasi SRAM structure is combine with the slave latch where NMOS pass transistor are utilized for storing and retrieving the data. A wake up startegies is proposed in  to control sudden surges of current during the time the gates are getting turned on from sleep mode. Two wake up protocols to partition a circuit for minimum peak drwan current. A new diode structure Ultra Low Power Diode (ULPD)  combining an n and a p MOSFET that strongly reduces reverse current in the circuit.
Correct sleep transistor is a key parameter that affects the performance of MTCMOS circuits. It is a challenge to choose right number of sleep transistors with proper size. Over the past few years, a number of sleep transistor (ST) sizing methodologies have been reported in the literature. Cluster based technique was proposed in ,  and  which accounted for the circuit floor plan and the noise bouncing on the virtual ground rails. In , and , gates are not clustered with exclusive discharged patterns. Instead, gates are allowed to be clustered with partially overlapping discharging currents. The peak current value of gates and switching time of gates as well as its duration is monitored. This paper proposed two techniques for efficient gate clustering in MTCMOS circuits by modelling the problem as Bin Packing and Set Partitioning problems. Results showed that this approach effectively decreased the size of sleep transistors in MTCMOS circuits. An improvement of this method was suggested in  where a distribution ST network methodology was proposed to minimize the total ST area. The network based design also known as coarse grain where many distributed sleep transistor are inserted between the actual and virtual power/ground network inside the block and these sleep transistor shares the charge and discharge currents. Distributed sleep transistor network was shown to be better than distributed clusters in term of sleep transistor area and performance.
The placement and sizing problem in the presence of RC interconnects can be formulated as a linear programming in . In , self sleep buffer with gated clock that capable of generating sleep signal based on the clock behaviour was proposed. The sleep buffer is assigned to each sleep transistor for distributed cluster based and network based MTCMOS. It reduces total intra block wire length, routing complexity and interconnect buffer and eliminate the need for distributing a sleep signal to all sleep devices. Another method to estimate the size sleep transistor is based on the usage of the vectorially modelled in . Two techniques for efficient gate clustering that based on maximum current pattern in MTCMOS circuit are proposed which are First Fit Technique and Set Covering Technique.
Cluster based technique was proposed in  that based on clustering logic cells and scheduling wakeup signals for the cluster. This method efficiently reduce the wake up time and maximum current flowing to ground for power gating structure. Clustering algorithm is introduced  to determine how to cluster cells to share sleep transistor taking both topology and functionality into consideration. Gates are clustered to share one sleep transistor and the relations of gates are modelled as a relation graph taking both topology and functionality into consideration. Clustering of gates is formulated as a clique partitioning problem. The improvement of cluster based technique is proposed in  where Decap Aware Sleep Transistor Design (DASTD) is improved cluster based sleep transistor design by taking on chip decoupling capacitance into account. The authors adopt an approach for reducing the transition time from sleep mode to active mode for a circuit part while assuring power integrity for the rest of the system by restricting the current that flows to ground during the transition.
One of the critical issues in MTCMOS circuit is the delay problem that increases due to the voltage fluctuation of the virtual ground . The cell delay and the output slew linearly increase with the virtual ground length and the inverse of power switch size . Static Timing Analysis (STA) methodology was proposed in  to compute delay in a good accuracy. The delay computation scheme use the four dimensional linear interpolation. The voltage variation at virtual ground node is thereby degrading the switching speed of the logic cells. Optimization algorithm for gate sizing and execute effective logic restructuring technique for timing critical path in the circuit is proposed  in making the MTCMOS circuits robust with respect to the voltage drop variation on its virtual ground network.
The optimization of virtual supply networks plays an important role because the parasitic effect of virtual networks will impact the circuit performance. In , a low power driven physical design flow and low power placement algorithm with two techniques as net weighting balance and ST relocation have been proposed to deal with low power implementation. In physical design level, two layout styles are proposed  for constructing power supply interrupt switch for leakage control. It improves performance over integrated layout and can also allow separate well bias for the power supply interrupt switch. This work  focuses on leakage power minimization in light of the growing significance of gate leakage current. Circuit reorganization and sleep-state assignment techniques are presented for gate and total leakage minimization of static and dynamic circuits. Two schemes for MTCMOS circuits are evaluated for total leakage minimization.
With the continous scaling of CMOS devices, leakage current is becoming a major contributor to the total power consumption. In current deep-submicrometer devices with low threshold voltages, subthreshold and gate leakage have become dominant sources of leakage. Power gating techniques have become very common in literature and in practice, and MTCMOS implementations in particular have demonstrated significant improvements in standby power consumption.
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