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The present day bulk CMOS technology is running into a number of physical limitations. Probably you must be aware of the fact that technology is approaching the limits of deep sub micron manufacturing using conventional Si technology. There is a limit imposed by the short channel effects and exponential raise of leakage power in bulk technology. Drawing smaller device patterns on wafer does not signify circuits to offer improved performance that Moore's law has delivered in the past. There is a limit to the progress which we expect due to scaling in terms of power and speed from circuits. Migration to lower technologies has helped us to produce transistors with shorter channel, lower supply voltages and lower current resulting in overall reduction of dynamic power. Higher sub threshold and source drain leakage currents and thinner oxide resulted in high leakage current which was not a big deal for IC technologies older than .18 micron. However in current technologies leakage power is in par with dynamic power and may very soon exceed it! Most of the reduction in dynamic power came from the scaling of voltage supplies; a change from 3.3v to 1.0v reduced dynamic power by a factor of 10. Dropping the core voltage beyond .8v poses threshold and noise margin issues.
It is hard to find another material to replace the Silicon with all its superior qualities. Question arises here: Can we improvise the current silicon technology? Answer is Silicon on Insulator (SOI).
What makes SOI so special? Is it a new technology? Proven solution? Cost/yield effective? Let's find out.
SOI technology features a buried layer of Silicon dioxide (insulator) layer across the wafer just below a surface layer of device quality single crystal silicon. Active elements are fabricated on the single crystal silicon above the insulator.
The very first SOI applications back in 1960 were designed for satellite and space exploration systems to guard the IC from ionization by radiation. Most of the earliest SOI integrated circuits used sapphire (Silicon on sapphire, SOS) instead of Silicon oxide due to its inertness to radiation.
Buried insulator (BOX)
Metal layers, same as bulk technology
Fig1:3D view of SOI inverter (from deep submicron CMOS circuit design simulator in Hands by Etienne Sicard Sonia Delmas Bendhia)
A brief history of the SOI development though out these years is given below (from IEEE SOI annual conference):
1970 - RCA:1k, 4k, 16k SRAM, SOS
1976 - HP:16bit MPU, SOS
1978 - Toshiba :16bit MPU, SOS
1978 - NTT :19 stage ring-oscillator, SIMOX
1982 - NTT :1k SRAM, SIMOX
1988 - Hughes :1GHz ADC, SOS
1988 - LETI :16bit MPU, SIMOX
1989 - LETI :16k SRAM, SIMOX
1989,1993 -TI :64k, 256k, 1M SRAM, SIMOX
1991,1993 - IBM :156k, 1M SRAM, SIMOX
1994 - LETI :32bit MPU, SIMOX
1994 - Fraunhofer :600V, 25A IGBT+CMOS, SIMOX
1994 - Samsung :16MDRAM, Hyundai (96):1GDRAM
1998 - IBM :64 bit PowerPC MPU shipping: 1.3GHz, 0.18 micron
First industrial application of SOI was announced by IBM in 1998. However the scenario has changed in the recent years and soon the market will flood with SOI devices. SOI devices offer a 20-35 % performance improvement over conventional bulk devices. More and more companies were attracted to this technology as the device dimensions shrink to .13 um and below scales. Applications of SOI extend to high end microprocessors and its low power variants, RF cmos, embedded DRAM and integration of vertical SiGe bipolar devices. These applications of SOI make it suitable for SoC applications which require high performance, ultra low power, embedded memory and bipolar devices. The main reasons which hindered the progress of SOI technology over last decade were SOI material quality, device design and steady progress of bulk cmos performance through scaling.
Apart from micro electronics SOI technology is widely used in silicon photonics in which crystalline silicon layer over insulator can be used to fabricate optical waveguides and other passive devices for integrated optics. This uses total internal reflection principles for the propagation of EM waves through waveguides.
Reducing power consumption is the ultimate limitation faced by today's deep sub micron BULK technology. The main physical limitations causing these effects are reduction in carrier mobility due to impurity scattering, increase in gate tunnel current due to use of ultra thin gate insulating materials and increase in PN junction leakage as the junction becomes shallower. The short channel effects also contribute to the shrinking channel length beyond a certain limit. These trends make conventional scaling less feasible. At 22 nm and below the current bulk technology is highly inefficient in meeting today's smart phone requirements. Current bulk has reached its limit in controlling the leakage current and ability to reduce the operating voltage or dynamic power without compromising performance a major source of wasted battery power.
On the other hand SOI technology features a low capacitance and thus a high speed operation. Supply voltage can be effectively lowered without affecting the circuit performance. SOI also features radiation hardness, ability to handle extreme temperatures and ability to handle high voltages. These advantages also enable the fabrication of micro-electro-mechanical (MEMS) systems for control systems. Compared to similar circuits fabricated on bulk CMOS technology, the same circuit fabricated on SOI wafers can run at 20-35 % higher switching speeds, 2-4 times lower power requirement while operating at similar speeds and conditions. These advantages of SOI technology makes it, 1-2 generations ahead of scaling of CMOS devices on bulk silicon wafers. Various advantages of SOI are listed below,
Better radiation hardening
Enhanced latch-up immunity
Less performance variations over temperature
Functional at higher temperatures
Better immunity to crosstalk
Reduction of parasitic
*2009-SOI consortium (SOI fundamentals)
SOI wafer manufacturing
There are several methods for producing a film of single crystal silicon on top of insulator (SiO2 or sapphire). One technique involves growing silicon over Si wafer covered with an insulator (homo-epitaxial techniques) or a crystalline insulator (hetero-epitaxial techniques). SOI wafers can be produced from conventional Si wafers by isolating thin SI layer from substrate through oxidation of porous silicon (FIPOS) or by an ion beam synthesis of a buried insulator layer (SIMOX, SIMNI and SIMON). Thinning a silicon wafer boned to an insulator and mechanical substrate is another way of producing SOI wafers. These various methods are intended for different applications. For example, SIMOX and UNIBOND are the ideal candidates for VLSI CMOS application, wafer bonding method adapted for bipolar and power applications. Description of various methods is given below.
Hetero Epitaxial Technique
This method involves epitaxial growth of Si on a single crystal insulator. At 1000 degree Celsius, films are grown using silane or dichlorosilane. In this process thermal coefficients of all insulating substrate are 2-3 times higher than Silicon. This thermal mismatch determines the electrical and properties of Si films grown on bulk insulators. SOS is the most mature material manufactured by this technique. It is fabricated by growing Si on Al2O3 substrate.
Homo Epitaxial Technique
SOI wafers are fabricated by growing a single crystal Si over SiO2 layer. Epitaxial lateral overgrowth (ELO) requires post thinning of Si layer. The Si layer in excess is removed leaving the Si Island. The main application is for 3D stacked circuits.
In Full isolation by oxidized porous silicon method, an anodic reaction is used to convert a part of Si wafer into porous silicon. During oxidation, the porous Si transforms very rapidly and selectively in a BOX (Buried oxide).
SIMOX (Separation by IMplanted OXygen )
SIMOX is the most prominent technology as of today. It is synthesized by internal oxidation during deep implantation of oxygen ions into SI wafer. Annealing of these wafers at high temperatures ensures the crystal quality of top layer Si. Some features of SIMOX wafers are good thickness uniformity, low defect density, sharp Si-SiO2 interface, robust BOX and high carrier mobility.
Fig 2: A high dose of oxygen implantation into Si followed by annealing produces BOX below a thin layer of crystalline silicon. (Silicon on insulator technology and devices: from present to future, Sorin Cristoloveanu, Solid state electronics)
An oxidized Si wafer is mated to second Si wafer. Bonding naturally occurs when two hydrophilic surfaces come into contact with each other. After bonding the Si layer is thinned down from 600 um to desired target thickness level. Thinning process usually consists of grinding and mechanical polishing followed by etch-back process.
This method is a subset of wafer bonding technique. The difference is absence of etch-back process in unibond technique. Smart cut mechanism involved in this process uses deep implantation of hydrogen to create micro cavities. The wafers separate naturally at a depth defined by location of hydrogen micro cavities which have eventually coalesced. Unibond process is finished by touch polishing. Unibond wafers have low defect density and excellent electrical characteristics.
Fig 3: Various steps involved in unibond process. (Created by 'Michel BRUEL' from
More into SOI
SOI technology can be classified into two based on the Si film thickness over the insulator. Partially depleted (PD) and fully depleted (FD) characteristics are explained here.
Partially depleted (PD)
As the name indicates there is an un-depleted neutral region at the bottom of SOI layer. Here Si layer over the top of wafer is thicker than the depth of the depletion region in the transistors channel. Thus two factors determining the FD or PD characteristics of SOI wafer is the Si layer thickness above BOX and the doping concentration in the channel. The neutral piece of Silicon beneath the depletion region in PD devices which is called the body is connected to ground through a contact, the characteristics of the device be similar to that of bulk devices. But in case if this connection is not made to make use of the spacing advantage of SOI technology, two parasitic properties called kink effect or floating body and presence of a parasitic open based NPN transistor between source and drain may emerge.
KINK Effect in PD devices:
In PD devices a strong current between source and drain causes a parasitic phenomenon called kink effect. The sudden rise of Ids creates a conductance discontinuity leading to impact ionization near drain causing high energy electrons entering drain region and generate electron hole pairs below the gate. While electrons contribute to the Ids, insulator underlying will prevent holes from escaping to substrate. The same effect in BULK technology is compensated by escape of secondary generated holes into substrate. Eventually the holes will get collected on the neutral body region which raises the potential of body.
Fig 4: from Advanced CMOS cell design by Etienne Sicard and Sonia Delmas
The raise in body potential below the gate has an instant impact on the threshold voltage of the transistor which is lowered. At certain point, the potential between source and bulk is high enough to turn the junction on, causing sudden increase in channel current. The effect is also known as floating body effect (FBE). Impact ionization is more prominent in N channel devices which make NMOS devices more susceptible to kink effect. Over the time many models have been devised to accommodate the kink effect in IÂds equations. Many of the negative effects of FBE can be eliminated by using a body contact for every MOSFET which is not an optimum solution from the layout point of view, considering the area constraints.
Fig 5: Explanation of Kink effect (Advanced CMOS cell design by Etienne Sicard and Sonia Delmas)
Fig 6: Ids Vs Vds to explain kink in the current. (Advanced CMOS cell design by Etienne Sicard and Sonia Delmas)
Formation of parasitic NPN transistor in PD devices:
A lateral bipolar transistor is formed by the forward biasing of body/source junction. A large drain current adds to the regular contribution of the MOS channel. This sidewall transistor operates in parallel with main transistor and strong coupling, charge sharing with front, back and edge channels dictate its threshold voltage. The parasitic transistor induces a premature breakdown in PD and FD short channel transistors. The effect of parasitic transistor can be alleviated by tuning the material properties in the channel to reduce carrier lifetime and by source engineering.
Fig 7: SOI transistor symbols explained with parasitic bipolar transistor effect included. (2009 SOI consortium - SOI fundamentals)
For an amplifier the gain at low frequency will reduce considerably due to kink and parasitic transistor presence. In order to reduce these effects, on method is to tie the floating body to substrate which means increase in circuit area and loss the SOI advantages like low parasitic and device density.
Various methods to tie the floating body is shown in the below diagram.
Fig 8: Showing various biasing options of SOI inverter circuit. (2009 SOI consortium - SOI fundamentals)
Transistor body voltage is dependent on previous switching activity.
The same device will switch differently depending on the recent switching activity.
Threshold voltage will change based on body charge.
(From SOI digital implementation & sign-off training from cadence)
The most prominent electrical property present in PD devices is history effect. The electric charge present in the floating body of PD device causes undesirable electrical properties. The device behavior is determined by the distribution of charge caused by the drain, gate and source. History effect is defined as the threshold difference caused by the variation of charge stored in the floating body. Drain current transients are observed when floating body potential is out of equilibrium. The current may vary from higher value (overshoot) to lower value (undershoot) than equilibrium value. Difference between the final and initial body charges is caused by transient current variations. Time constants depend on the generation-recombination process and leakage through gate and junctions.
During high frequency operation the charging/discharging of the body may cause history effects and dynamic instabilities. Switching delay is governed by the available current which can be higher or lower than at equilibrium. Switching speed depends on previous switching cycles. Delay variation between static and dynamic charge states define delay times as "First switch/second switch" delays. Difference between first switch to second switch is referred as hysteresis. The amount collected in the floating body will be at its minimum when the circuit is idle. The value of stored charge reaches its highest point when the circuit operates in its steady state operation.
Short channel effects in SOI:
The scaling of gate lengths in bulk deep submicron technology is almost approaching the physical limits. When channel length shrinks, the controllability of gate over channel reduces due to increased charge sharing from source to drain. Short channel effect refers to threshold voltage reduction with channel length for very short channels. But in bulk technology the magnitude of short channel threshold voltage roll off has been observed to decrease with elevated substrate bias.
When the same conditions meet in PD devices, due to increase in potential of the floating body the threshold voltage roll off appears to be diminishes or disappear.
Fully Depleted (FD) SOI device
As the Si layer thickness above BOX layer is reduced to a few nm ranges, the floating body disappears or the SOI is fully depleted when the channel is inverted. The maximum depletion width is greater than the Si layer thickness. Potential barrier to holes at the source end is small in FD devices, even deep within the body region, because the body region is depleted all the way down to the bottom. As a result the accumulation of holes is less in this region which results in a kink free transistor Ids characteristics. FD devices unlike PD devices need not require a contact to body for the proper functioning, which in fact results in the higher density fabrication with FD devices. These advantages make FD layout much compatible with bulk layouts.
Threshold voltage of a FD device depends on the drain voltage, i.e. it decreases with drain voltage due to parasitic bipolar effects in FD SOI devices.
To obtain a FD device with .3 - .4 V threshold value, the thickness of Si layer must be at most 50-60 nm.
Fig 9: Energy band diagram in bulk (A), PD SOI (B), FD SOI (C). All devices are represented at threshold (front gate voltage = threshold voltage). Shaded areas represent depletion region. SOI devices are represented by a condition of week inversion at the back interface. (From Silicon on insulator technology: materials to VLSI by Jean Pierre Colinge)
Fully depleted SOI are virtually free of kink effect, if their back interface is not in accumulation. Among all the devices, FD devices with depleted back interface exhibit the most attractive properties like high trans-conductance, quasi-ideal sub threshold slope characteristics, excellent short channel behavior and low electric fields.
There are nine modes of operation for FD devices, as a function of Vg1 and Vg2 depending on the front and back interface conditions. Front and back interfaces can be either in accumulation, depletion or inversion. But in practical applications only a few modes are used.
Tab 1: Comparison of electrical properties of FD and PD devices. '0' means similar to bulk, '+' means better than bulk and '-' indicates worse than bulk. (From Silicon on insulator technology: materials to VLSI by Jean Pierre Colinge)
These excellent electrical properties of FD SOI enable lower VDD (lower power consumption) whilst reaching remarkable performance. FD SOI strongly reduces random doping fluctuation thus drastically cutting Vt variability. FD SOI is intrinsically low leakage and thus regains a good control of short channel effects. Consequence is the ability to shrink the gate length aggressively and making it easier to fit more devices into smaller and smaller pitches therefore increase device density to continue Moore's law.
Self Heating effects:
The beneficial effects of BOX layer on the electrical characteristics have a dark side when the thermal properties are considered. Thermal conductivity of the SiO2 film used in the BOX has 1.4 WmÂÂ-1K-1, which is two orders of magnitude smaller than Si (140 WmÂÂ-1K-1) used in BULK. As a result heat generated by the drain current cannot easily escape though BOX layer which raises the channel temperature. A large amount of heat generated during saturation condition when Id and Vd is high. And resulting increase in temperature may adversely affect drain current by lowering carrier mobility and may lead to appearance of a differential negative resistance in the drain current voltage characteristics. The joule heat dissipation can occur through interconnections via the contacts on the source and drain layer and via the gate oxide film and gate electrode.
Increase in channel temperature caused by self heating is governed by the structural parameters of device, such as distance between the channels and source drain contact and thickness of SOI layer.
Fig 10: Various heat contribution elements in SOI device (2009 SOI consortium - SOI fundamentals)
Current Market trends
The hot topic of 2011 will be FD SOI, the top competitor for mobile, low power and SoC apps at 22 nm node process. The ability to operate at high temperatures makes SOI the ideal candidate for automobile applications. SOI consortium is a group of leading semiconductor companies with the mission of accelerating SOI into broader markets. Recently SOI consortium released the results of assessment and characterization of the FD SOI ARM cortex processor. The results concluded that SOI technology is capable of addressing low power and high performance requirements of smart phone and portable computing technology. This project was a joint effort by industry giants like IBM, ARM, global foundries, ST micro-electronics and SOITEC.
Tab 2: Comparison of bulk, next generation bulk and FD SOI. (SOI consortium)
There exist proven solutions for 45 and 32 nm SOI technologies in today's industry. IBMs 45 and 32 nm foundry is supported by cadence, synopsys with ARM libraries. Lack of available IPs is the main barrier for a broader adoption of the SOI technology. The global SOI market is estimated to hit a target of $1.3 billion by 2015.
Presently IBM, global foundries, free scale and UMC offer SOI foundry service. SOITEC, ultrasil, icemos, shin-etsu and MEMC are leading SOI wafer manufactures. Cadence, mentor graphics and synopsys provide industry standard EDA tools for SOI design.
It is evident that further scaling of CMOS bulk technology imposes limitation in performance and leakage current. Whereas SOI still a raw technology and its possibilities are yet to be explored. It's not a mature technology like CMOS bulk technology. To establish more complex and robust SOI design flows, it's necessary to examine its various electrical and mechanical behaviors. With its advantages over present day bulk technologies, more and more companies are attracted towards SOI and lot of R&D is going on in this field. SOI CMOS is being applied to more microprocessors, SRAMs and eDRAMs, and is being implemented by a number of companies. Brining SOI to the mainstream Si market was challenging and involves years of R&D by various companies. However as we move beyond 45 nm and below, SOI offers total solution and its future is promising too.