A High Speed Low Cost For Rf Applications Engineering Essay

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In this paper it is proposed to design a high speed low cost PLL that will be used for RF applications. This architecture will have a ring oscillator running at very high frequency instead of traditional LC VCO oscillator and the frequency divider circuit will be used that will provide the desired frequency and will also reduce the phase noise. This design will be of particular interest in the RF applications because of the high speed, less phase noise and low cost.

The objective of this proposed project is to reduce the cost of PLL that is used in many RF applications. This will be achieved by using the ring oscillator instead of LC Voltage Controlled Oscillator. Further, the idea is to reduce the phase noise by using appropriate frequency divider circuit.

Phase Lock Loop (PLL) is used in many applications today. PLL has an important role in many RF applications. High speed, low cost and low power PLL are of main interest for wireless applications [1]. PLL are also used as clock recovery for communication systems, frequency synthesizer of wireless systems, etc. [2]. As name suggests, Phase Lock Loop, PLL controls and locks itself to the reference frequency. The basic block diagram of a PLL is shown in Figure 1:

The phase locked loop has four important blocks in its designing. These blocks are Phase Frequency Detector, Charge Pump, Filters and Voltage Controlled Oscillators. The Frequency Phase Detector detects the phase difference between the reference signal and the signal coming from the frequency divider circuits and generates the resultant voltage error signal. When this error signal is compared with the incoming reference signal it can be checked if the VCO is too fast or too slow. [4] The signal generated can be either leading or lagging signal, depending on the reference and output from the oscillator. The charge pump is used to convert the error voltage signal to the current. This current is then fed to the low pass filters which conditions the signal. The filters also work as integrator to integrate the signal from the charge pump and it gives this to the oscillator. [4] These filters also determine the bandwidth of the PLL. The voltage controlled oscillator then oscillates with respect to the input voltage. The voltage controlled oscillator is usually LC based voltage controlled oscillator. The main disadvantage of using LC Voltage Controlled Oscillator is the cost. In order to reduce the cost, we are using a ring oscillator in this project. The main advantage of using ring oscillator is their minimal area and thus minimizing the cost. Also, the ring oscillators have large frequency tuning range and large bandwidth [5].


If the Phase Locked Loop is designed using the ring oscillator instead of traditional LC VCO and then connected to frequency divider and if this frequency divider runs properly at a high speed and divides the output frequency from the ring oscillator, then the desired frequency will be obtained which will be suitable for RF applications. This design will not only help to reduce the cost of a high speed PLL but also to reduce the phase noise of PLL.


The increasing demand of PLL in almost every circuit has led to reduce the cost PLL every other day. The PLL should not only be of low cost but also should be of high speed, low noise and large bandwidth. All these reasons have led to great research on techniques of how to reduce the cost while maintaining high speed and less noise. Many different papers have been published describing how to reduce to noise and ways to reduce the cost while increasing the bandwidth and high speed. The proposed project tries to reduce the cost of a Phase Locked Loop by running PLL at high speed.


The objective of achieving high speed, large bandwidth and low cost PLL’s has led many researchers interest in this area of technology. There have been many papers released showing the techniques to reduce the cost and build high speed, low area and low noise PLL’s. The major part of the cost can be reduced by using ring oscillator VCO instead of LC VCO. A paper was published which had presented the comparison of using LC and ring VCO in a PLL in 90nm process technology [3].

From the published paper we can see that by using a ring oscillator we can considerably reduce the layout area as compared to that by using a LC Voltage Controlled Oscillator [3]. Another advantage of using ring oscillator is that using ring oscillator we can meet the requirements of applications which needs high speed clock synthesizer such as in RF applications [3]. Also, ring oscillator has an advantage of larger tuning range and smaller layout area [3]. Due to smaller layout area the cost will also be considerably decreased. In this proposed project the ring oscillator will be used because of its large tuning range, high speed and low cost.


Phase Locked Loops are used in many applications as an Integrated circuit. The motivation for doing this project is that the designed PLL will be of high speed and low cost. In this project a ring oscillator will be used instead of LC Oscillator which will reduce the overall cost PLL considerably. This high speed and low cost Phased Locked Loop will be used in many RF applications.



The designing of PLL will be done in parts / blocks. There are different blocks in PLL. Each block will be designed differently and then integrated together later. The PLL designing will be done in Synopsys Schematic Capture Tool.

Simulation for the designing will be done to check for the proper working of all the blocks. In an ideal case there will not be any phase difference between the reference signal and the signal coming from the Voltage Controlled Oscillator. The proposed design will try to ensure the same.

In this proposed project of PLL, PLL has phase frequency detector, charge pump, loop filters, and voltage controlled oscillator (ring oscillator) and frequency dividers. All of the above mentioned components will be individually tested after designing them and will be seen to it that each block is working correctly.

DRC and LVS of each of these modules will be made and will be checked for errors. After checking for the errors, a final layout will be made where all these blocks will be integrated.

4.2] SCOPE

The block diagram of the Phase Locked loop is shown in Figure 2.

Figure 2. Traditional Phase Locked Loop

Figure3. Scope of Work: PLL with ring oscillator VCO

In this project, the design of Phase frequency detector, charge pump, ring oscillator and frequency divider will be the part of the project. The simulation and analysis of the ring oscillator and the frequency down conversion will be in the scope of this project. The fabrication and packaging of the chip will not be in the scope of this project.


The Phase Locked Loop (PLL) will be designed on the Cadence design tool that is available in the laboratory to begin the design process. The objective is to make a high speed and low cost PLL using a ring oscillator. The specifications and the technology that will be used in designing this PLL are as follows:



Process Technology

Gpdk 45nm

Operating Voltage

1 V


2 - 2.4 GHz






Environment Setting up the environment in Cadence for 45nm

A fully functional setup

Completed/Not Completed

Designing of Individual Blocks

A working schematic design

It will compare the individual performance of each blocks and check the values

Layout of Individual Blocks

Working Layout

It should clear the DRC’s & LVS

Integrating the layouts

Working layouts

It should integrate the schematic and pass the DRC’s and LVS

Combining all the blocks

Schematic, simulations and layout

Will perform final analysis and measure all parameters

Report and presentations

Simulation results

Advisors and co-advisors approval


Phase Locked Loop with high speed and low cost will be of advantage for various RF wireless applications. The use of ring oscillators Voltage controlled oscillators instead of LC Voltage Controlled Oscillator will reduce the overall cost of the PLL and also will provide high bandwidth and high speed. The important applications are in RF wireless applications.






Literature survey

2 weeks



Proposal draft

1 week



Final submission of proposal draft

2 weeks



Block diagram

1 week



Designing modules

4 weeks



Layout and debug

8 weeks




1 week




2 weeks




1 week



Final report

1 week




1 week



Preparation of presentation

1 week



Total time