32 Bit Risc Microprocessor Using VHDL Engineering Essay


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The main aim of the project is to design 32 bit RISC processor which consists of different stages of pipelining and the code is written in VHDL and simulated using MODELSIM.

The technologies are comparatively changing from the past 20 years. The microprocessor or “Computer on chip” came to existence for the first time by the unknown company named Intel Corporation in 1971 with the 4 bit 4004 by a small [1]. Microprocessor is the heart of all the smart devices such as mobile phone. The computer typically consists of mainly four components they are Input, Output, Memory and the processor [2]. The parts for the computer that we purchase will come under these four components that is the keyboard comes under the input device, monitor is output devices and RAM is under memory. The microprocessor is also known as the Central Processing Unit (CPU) which includes data path, control unit, memory, I/O devices and clock timing circuitry [2].

Data path is responsible for all actual execution of all data operation performed by the microprocessor such as ADD, SUB, AND etc, control unit which control all the activities inside the microprocessor [2]. Below figure shows in details inside the control unit and the data path

As we came to the selection of the processor, we will be in the state of mixed up position to select the processor either CISC (Complex Instruction Set Computer) or RISC (Reduced Instruction Set Computer), since the CISC processor is the prevailing processor in the market, but in the recent years the Intel has moved from CISC to RISC for the designing of the 64 bit processor [3] and my choice is RISC because

Assembly language is referred as the low level programming language [3], since they are native to the processor used in the system. For example program which is written in the Intel assembly language cannot be executed in Power PC [3]. The processor will understand only machine language which consists of 1's and 0's. Both are closely related to each other. Some of the examples are shown below

From the above example we can say that most instruction uses 2 addresses. But in MIPS it uses three addresses as shown below

Here the processor register are recognised by $ [3]. The first instruction perform bitwise and of $S1 with 5 and stores the results in $S2. The second instruction adds both the register that is S1, S2 stores the result in $S3 [3].

The MIPS architecture has 32 general purpose register, program counter (PC) and two special purpose register [3], all register is of 32 bit wide as shown in the figure

The instruction is stored in the text segment which is placed at the bottom of the address space [3] at 0x4000000; the data segment starts at 0x10000000 which is placed above the text segment [3], and further the data segment is divided into two types that is static and dynamic. The stack segment starts at 0x7FFFFFFF and which is situated at the bottom of the address space [3], and below figure shows the MIPS memory layout

The design of the 32 bit RISC processor will be consisting of the various blocks such as arithmetic and logical unit, control logic unit, accumulator, program counter, instruction register and memory clock generator.

Here they will be performing all the arithmetic and logical set of operation such as Add, Not, Subb etc. Depending on the decode instruction here they will be that is arithmetic and logic unit they will be used for three different functions which are data manipulation instruction, it will be going on evaluating the effective address for load and store instruction. So therefore this results will be transferred to the destination register with the help of the central processing unit. The block diagram of the ALU is as shown below

These will be going on generating all the necessary required control signals which has to be used by the central processing unit, which are as fallows load instruction register, increment program counter, memory read and memory write.

When ld_acc is set to 1 then the output of the arithmetic and logical unit will be loaded into the accumulator. If inr pc =1, then the program counter is incremented by one to its previous value. Whether the write signal=1 and read is set to 0 the n the data bus will write the content to the memory which is specified by the program counter.

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