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VLSI (Very large scale integration), involves the technology that allows a large number of circuits to be included on single silicon chip. It is developed during the 1980's, to usher in an age where many of the technical innovations we enjoy today were made possible.
VLSI is a process that can be employed in several different ways. It comes to the production of semiconductor chips, the process provides the ideal means of including huge numbers of logic elements and memory capacity on one single chip. The simple application helped to make desktop computers more powerful than ever, as well as setting the stage for the utilization of resources that make online video and other high resource applications possible . VLSI circuits are there with your computer, your car, your brand new state-of-the-art digital camera, the cell-phones, and what have you. It involves a lot of expertise on many fronts within the same field
VLSI can incorporate components that perform analog signal processing, digital signal processing or both. Microprocessor is a VLSI device. This term is no longer as common as it once was, as chips have increased in complexity into billions of transistors. The first semiconductor chips held two transistors each. It advances added more and more transistors, and, as a consequence, more individual functions or systems were integrated over time. The first integrated circuits held only a few devices, perhaps as many as ten diodes, transistors, resistors and capacitors, making it possible to fabricate one or more logic gates on a single device. There must be improvements led to large-scale integration (LSI), i.e. systems with at least a thousand logic gates. The Current technology has moved far past this mark and today's microprocessors have many millions of gates and billions of individual transistors.
The design is a modular methodology originated by Carver Mead and Lynn Conway for saving microchip area by minimizing the interconnect fabrics area. It is obtained by repetitive arrangement of rectangular macro blocks which can be interconnected using wiring by abutment. The Example is partitioning the layout of an adder into a row of equal bit slices cells. In complex designs the structuring may be achieved by hierarchical nesting.
DEALING WITH VLSI CIRCUITS
The Digital circuits are basically predominantly CMOS based. The way the normal blocks like latches and gates are implemented in different from what students have seen so far, but these are the behaviour remains of the same. All this miniaturisation involves new things to consider. Lot of thought has to go into actual implementations as well as design. Factors involved .are:
1. Circuit Delays. Large circuits running at very high frequencies have one big problem to solve upon the delays in propagation of signals through gates and wires. The areas a few micrometers across .The operation speed is large enough that as the delays add up, they can actually become compared to the clock speeds.
2. Power :The effect of high operation frequencies are increased in the consumption of power. This is a two-fold effect - devices consume batteries faster, and heat dissipation increases. These are Coupled with the fact that surface areas have decreased the heat poses a major threat to the stability of the circuit itself.
3. Layout : The circuit components is a common task to all the branches of the electronics. There are many ways to do such things, which can be multiple layers of different materials on the same silicon, there are different arrangements of the smaller parts for the same component. The power dissipation and the speed of circuit present a trade-off; if we try to optimise on anyone, the other is affected.
Microprocessors have become more complex due to new trends in technology scaling, The designers have encountered several challenges which force them to think beyond the design plane, and look ahead to the post-silicon:
Power usage/Heat dissipation -Threshold voltages have encountered to scale with advancing process technology, dynamic power dissipation cannot be scaled proportionally. The Maintainenece of logic complexity when scaling the design by only means that the power dissipation per area will be go up. This gives rise to techniques such as dynamic voltage and frequency scaling (DVFS) to minimize overall power.
Process variation - The photolithography techniques tend to closer the fundamental laws of optics, which achieves high accuracy in doping concentrations and etched wires is becoming more difficult and prone to errors due to variation. Designers now must simulate across multiple fabrication process corners before a chip is certified ready for production.
Stricter design rules -The etch issues with scaling, design rules for layout have become confinement. Designers must use ever more of such rules in mind while laying out the custom circuits. The overhead for the custom design is reaching a tipping point, with design houses opting to switch to the electronic design automation (EDA) tools used to automate their design process.
Timing/design closure -Clock frequencies tend to scale up, It is more difficult to distribute and maintain a low clock skew between these high frequency clocks across the entire chip. This led to the rising interest in multicore and multiprocessor architectures, when an overall speedup can be obtained by lowering clock frequency and the distributing processing.
First-pass success -The die sizes shrink due to scaling, and the wafer sizes go up to lower manufacturing costs, the number of losses per wafer increases and their complexity of making suitable photomasks makes up rapidly. The mask set for a modern technology can cost upto several million dollars. The non-recurring expense deters of the old iterative philosophy which involves several "spin-cycles" to find the errors in silicon, which encourages first-pass silicon success.
Very Large Scale Integration
design/manufacturing of extremely small, complex circuitry using modified semiconductor material
integrated circuit (IC) may contain millions of transistors, each a few mm in size applications wide ranging: most electronic logic devices
Three Dimensional VLSI
The fabrication of a single integrated circuit whose functional parts (transistors, etc) extend in three dimensions
The vertical orientation of several bare integrated circuits in a single package
Advantages of 3D VLSI
Speed - the time required for a signal to travel between the functional circuit blocks in a system (delay) reduced.
Delay depends on resistance/capacitance of interconnections
resistance proportional to interconnection length
Noise - unwanted disturbances on a useful signal
reflection noise (varying impedance along interconnect)
crosstalk noise (interference between interconnects)
electromagnetic interference (EMI) (caused by current in pins)
fewer, shorter interconnects
power used charging an interconnect capacitance
P = fCV2
power dissipated through resistive material
P = V2/R
capacitance/resistance proportional to length
reduced interconnect lengths will reduce power
Interconnect capacity (connectivity)
more connections between chips
increased functionality, ease of design
Printed circuit board size/weight
planar size of PCB reduced with negligible IC height increase
weight reduction due to more circuitry per package/smaller PCBs
estimated 40-50 times reduction in size/weight
3D VLSI - Challenges and Solutions
Challenge: Thermal management
increased circuit density
increased power density
circuit layout (design stage)
high power sections uniformly distributed
advancement in cooling techniques (heat pipes)
Three Dimensional VLSI
Moore's Law approaching physical limit
Increased performance expected by market
Paradigm shift needed - 3D VLSI
many advantages over 2D VLSI
economic limitations of fabrication overhaul will be overcome by market demand
Three Dimensional VLSI may be the savior of Moore's Law
THE VLSI DESIGN PROCESS
All the modern digital designs start with a designer who writes a hardware description of the IC using HDL or Hardware Description Language in Verilog/VHDL. A Verilog or the VHDL program essentially describes the hardware such aslogic gates, Flip-Flops, counters etc and the interconnect of such circuit blocks and their functionality. Various CAD tools which are available to synthesize a circuit based on HDL. The widely used tools come from the two CAD companies. Synposys and Cadence. VHDL can be called as the "C" of the VLSI industry. It stands for "VHSIC Hardware Definition Language" where VHSIC stands for "Very High Speed Integrated Circuit". This is used to design the circuits at the high-level, in the two ways. It can be either of a behavioural description, which describes what the circuit is supposed to do, and a structural description, who describes what the circuit is made. There are some other languages for describing the circuits, such as Verilog, which work in a same fashion. Both the forms of description are used to generate a very low-level description which actually spells out all this is to be fabricated on the all silicon chips. This will result in the manufacture of the intended IC.
In case of the analog design, the flow changes :
SPICE Simulation Layout
Parametric Extraction / Back Annotation
Tape Out to foundry.
The digital design are highly automated very small portion of analog design can be automated. The hardware description language called AHDL but not widely used as it does not accurately give us the behavioral model of the circuit because of their complexity of such effects of parasitic on the analog behavior of the circuit. The analog chips are termed as "flat" or non-hierarchical designs. This is used for small transistor count chips such as an operational amplifier, or a filter or a power management chip. No many CAD tools are available for the analog designs even today and thus analog design remains a difficult art. SPICE remains the useful simulation tool for the analog as well as digital design.
VLSI Design Flow
The design process is usually a evolutionary in nature. It starts with a given set of requirements. The Initial design is developed and tested against the requirements. When requirements are not met with the design has to be improved. The Y-chart first introduced by D. Gajski shown in illustrates a design flow for most logic chips, using design activities on three different axes domains which resemble the letter Y.
Simplified view of the VLSI design flow.
This provides a more simplified view of the VLSI design flow, in which various representations, or abstractions of design - behavioral, logic, circuit and the mask layout. The verification of design plays an important role in the every step during this process. The failure is to properly verify the design in its early phases typically causing significant and expensive re-design at a later stage, which ultimately increases the time-to-market. The design process has been described in such a fashion for its simplicity, in reality there are many iterations back to, especially between any two neighboring steps, which occasionally even remotely separated the pairs. The top-down design flow provides an excellent design process control there are unidirectional top-down design flow. Both top-down and bottom-up approaches have been combined.
If a chip designer describes an architecture without close estimation of the corresponding chip area, it is very likely to the resulting chip layout which exceeds the area limit of the available technology. It is very important to feed forward low-level information to higher levels (bottom up) as early as possible. The design methodologies and the structured approaches are developed over the years to deal with both the complex hardware and the software projects. The basic principles of the structured design will improve the prospects of the success. Some of the classics techniques for reducing the complexity of IC design are: Hierarchy, regularity, modularity and locality
The use of hierarchy technique involves dividing a module into sub- modules and repeating this operation on the various sub-modules until the complexity of the smaller parts becomes manageable. This is very similar to the software case where large programs are divided into smaller and smaller sections until simple subroutines, with well-defined functions and the interfaces. The design of a VLSI chip can be represented in three domains. The hierarchy structure can be described in each domain separately. It is important for the simplicity of design that the hierarchies in such different domains can be mapped into different each other easily.
As an example of structural hierarchy shows the structural decomposition of a CMOS four-bit adder into its components. The adder can be splitted progressively into one- bit adders, separate carry and the sum circuits which finally into individual logic gates. The lower level of the hierarchy such as the design of a simple circuit realizing a well-defined Boolean function is much more easier to handle than at the higher levels of the hierarchy. In the physical domain, partitioning a complex system into its various functional blocks will provide a valuable guidance for the actual realization of these blocks on chip
Structural decomposition of a four-bit adder circuit, showing the hierarchy down to gate level
Concepts of Regularity, Modularity and Locality
The hierarchical design reduces the design complexity by dividing the large system into several sub- modules. The other design concepts and the design approaches are also needed to simplify the process. Regularity means that the hierarchical decomposition such large system should result in not as only simple, but also similar blocks, as much as possible. An example of regularity is the design of an array structures consisting of identical cells - such as a parallel multiplication array. Regularity can exist at levels of all abstraction: At this transistor level, uniformly sized transistors simplify the designs. At the logic level, identical gate structures can be used. The regular circuit-level designs of a 2-1 MUX (multiplexer), an D-type edge-triggered flip flop, and a one-bit full adder. All of these circuits were designed by using inverters and the tri-state buffers only. If the designer has a small library of a well-defined and well-characterized basic building blocks, the number of different functions can be constructed by using this principle. Regularity reduces the number of different modules that need to be designed and verified, at all levels of abstraction.
Regular design of a 2-1 MUX, a DFF and an adder, using inverters and tri-state buffers.
Modularity means that the various functional blocks which make up the larger system must have a well-defined functions and the interfaces. It allows that at each block or module can be designed relatively to independently from each other, as there is no ambiguity about the functions and the signal interface of these blocks. All of the blocks can be combined at the end of the design process, to form the large system component . The concept enables the parallelisation of the design process. It also allows to use of generic modules in the various designs the well-defined functionality and the signal interface allow plug-and-play design. By well-characterized interfaces for each module in the system, we ensure that the internals of such module become unimportant to their exterior modules. Internal details remained at the local level. The concept of locality ensures that the connections are mostly between neighboring modules, avoiding the long-distance connections. This point is extremely important for all avoiding excessive interconnect delays such as Time-critical operations should be performed locally, without the need to access such distant modules or signals.
VLSI Design Styles
There are Several design styles that can be considered for chip implementation of specified algorithms or logic functions. In each design style has its own merits and shortcomings, which has a proper choice that has to be made by designers in order to provide the functionality at low cost
Field Programmable Gate Array (FPGA)
It is termed as Fully fabricated FPGA chips which contains thousands of logic gates with programmable interconnects which are available to the users for their custom hardware programming to realize the desired functionality. It provides a means for fast prototyping and for the cost-effective chip design, especially for low-volume
applications. A field programmable gate array chip consists of an I/O buffers, an array of configurable logic blocks (CLBs), and the programmable interconnect structures. The programming of such interconnects is implemented by programming of RAM cells whose output terminals are connected to gates of MOS pass transistors. The full utilization of the FPGA chip area is not possible as many cell sites may remain unused. The largest advantage of using FPGA design is the very short turn-around time, in which the time required from the start of the design process until a functional chip is available. As there is no physical manufacturing step which is necessary for customizing the FPGA chip, a functional sample can be obtained almost as soon as the design is mapped into specific technology. The typical price of FPGA chips are usually higher than realization alternatives such as gate array or standard cells of the same design but for the small-volume production of ASIC chips and for the fast prototyping FPGA offers a very valuable option.
General architecture of Xilinx FPGAs
Detailed view of switch matrices and interconnection routing between CLBs
XC2000 CLB of the Xilinx FPGA
Gate Array Design
The gate array (GA) comes after the FPGA. The design implementation of the FPGA chip is done with the user programming, that of the gate array which is done with a metal mask design and the processing. Gate array implementation requires a two-step manufacturing process: The first phase is based on generic (standard) masks results in an array of uncommitted transistors on each of GA chip. These uncommitted chips can be stored for the later customization which is completed by the defining the metal interconnects between the transistors of the array. As the patterning of metallic interconnects is done at the end of the chip fabrication the turn-around time can be still short a few days to the few weeks. A corner of a gate array chip which contains bonding pads on its left and bottom edges, diodes for I/O protection, nMOS transistors and pMOS transistors for the chip output driver circuits in neighboring areas of the bonding pads, arrays of nMOS transistors and the pMOS transistors, underpass wire segments, and power ground of the buses along with contact windows.
MOST OF TODAY'S VLSI DESIGNS ARE CLASSIFIED INTO THREE CATEGORIES:
Small transistor which count precision circuits such as Amplifiers, Data converters, filters, Phase Locked Loops, Sensors .
2. ASICS or Application Specific Integrated Circuits:
The Progress in the fabrication of IC's enabled us to create the fast and the powerful circuits in smaller and smaller devices. This means that we can pack a lot of functionality in the same area. The biggest application is the ability to found in the design of ASIC's. There are IC's that are created for a specific purposes - each device is created to do a particular job. The most common application area for this is the DSP - signal filters, image compression, etc..
3. SoC or Systems on a chip:
These are the highly complex mixed signal circuits digital and analog all on the same chip. A network processor chip or a wireless radio chip is an example of an SoC.
List of Some VLSI Companies:
Accel Technologies Limited
Alcatel Vacuum Technology
Digital Core Design
Mentor Graphics (I) Pvt. Ltd.