Vhdl And Fpga Processor Design And Implementation Computer Science Essay

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The design and implementation of a basic microprocessor is carried out using VHDL. The microprocessor to be designed here is a Xilinx Spartan3 FPGA (XC3S200). A Microprocessor is a single Integrated circuit(IC) designed to interpret and execute program instructions at higher rate. An eight bit data, reset and clock are fed as the inputs to the processor with status flags. Programs are coded externally individually for Arithmetic Logic Unit, Data memory (RAM) and Program memory (ROM) as VHDL files. The coded data's are later used to perform control unit operations. Thus four modules will be created. A top level module is created with the combination of these modules which is said to be the structural VHDL module or a Schematic Diagram.

2. Introduction to Microprocessors:

 An integrated circuit that contains all the functions of a central processing unit is referred to as a Microprocessor. It performs arithmetic and logic operations that make use of small number-holding areas called registers. Typical microprocessor operations include adding, subtracting, comparing two numbers, and fetching numbers from one area to another. These operations are the result of a set of instructions that are part of the microprocessor design. Microprocessors are classified by the semiconductor technology of their design by the width of the data format they process and by their instruction set. (1)

The microprocessor has an arithmetic logic unit (ALU), a control unit, a memory interface, an interrupt or exception controller, and an internal cache. The memory interface fetches instructions from, and writes data to, external memory. The control unit issues one or more instructions to other function units. These units process the instructions in parallel to boost performance. (2)

3. Architecture of Microprocessor:


Fig 1: Architecture of Microprocessor (1)

The Architecture of Microprocessor includes four basic blocks. They are discussed below.

Arithmetic Logic Unit

Data Memory(RAM)

Program Memory (ROM)

Control Unit.

3.1. Arithmetic Logic Unit (ALU):


Fig 2: Arithmetic Logic Unit

The ALU is a core of the central processing unit (CPU). It is a calculator chip that performs mathematical and logic operations on the data words supplied to it. It is made to work automatically by control signals developed in the instruction decoder. The ALU combines the contents of its two inputs, which are called the data registers and the accumulator. Addition, subtraction and logic comparisons are the primary operations performed by an ALU. The specific operation to be performed is determined by the instruction decoder. The data supplied to the inputs of an ALU may be in the form of 8-bit binary numbers. They are combined by the ALU in accordance with the logic arithmetic. Since mathematical operations are performed on the two data inputs, they are called operands. (3)

The various functions performed by an Arithmetic Logic Unit include addition, subtraction, AND, OR, Exclusive OR, Complement, shift right, shift left, increment and decrement.

3.2. Memory Unit:

In order to store a program and data, microprocessor requires a memory unit. Random access memory (RAM) and read only memory (ROM) are the two types of memories involved in a microprocessor.


Fig 3: Types of memory (5)

3.2.1. Data Memory (RAM):


Fig 4: RAM (6)

RAM is the basic kind of internal memory. It is also called as read/write memory. Random access memory is a volatile memory. In case of volatile memory unsaved contents are lost when there is a breakage of power. The word random refers to the fact that any piece of data can be returned in a constant time, regardless of its physical location and whether or not it is related to the previous piece of data.(5)

Data can be read or written into RAM. The block diagram of RAM consists of a data bus, address bus, and read and write signals. The data bus carries information out of or into RAM. The address bus is used to select a memory location. The read signal become active when reading data from RAM and the write line becomes active when writing to RAM. It has been made from reed relays, transistors, integrated circuits, magnetic core, or anything that can hold and store binary values. (6,7)

RAM is broadly divided into two, Static RAM and Dynamic RAM. Static RAM continues to hold and store information even when the power is removed. Magnetic core and reed relays are examples of static memory. Dynamic RAM loses all data when power is removed. Transistors and integrated circuits are examples of dynamic memory. (7)

3.2.2. Program Memory (ROM):

Read only chips are device which permanently store data that are resident to the system and does not change when power is disconnected. Unlike RAM, it is permanently programmed so data are always present, even when power disconnected. This type of memory is often called as non-volatile memory.(5) Data stored in ROM cannot be modified, at least not very quickly or easily. This type of memory can only be read.


Fig 5: ROM

The different types of ROM include MROM, PROM, EPROM and EEPROM. Mask-Programmed ROM (MROM) - programmed at the factory. Programmable ROM (PROM) - can be custom-programmed by the user (once) using special circuitry. Erasable-Programmable ROM (EPROM) - can also be programmed and erased by the user using ultraviolet light and special circuitry external to the computer. Electrically Erasable PROM (EEPROM)-can be erased and reprogrammed by special circuitry within the computer.

The major advantages of ROM are its permanence of data storage and security of data's stored since ROM cannot be easily modified. The most common example is the system BIOS program. (9)

3.3. Control Unit:

Control units are in charge of the computer. They fetch and decode instructions. (7)

C:\Users\HARISH\Desktop\cnt unit.jpg

Fig 6: Control Unit

The control unit governs and coordinates the activities of different sections of the processor and I/O devices. The main purpose of control unit is to read and decode instructions from the program memory. To execute an instruction, the control unit steps through the appropriate blocks of the ALU based on op-codes contained in the instruction register. The op-codes define the operations to be performed by the control unit to execute an instruction. The control unit interprets the contents of the instruction register and then responds to the instruction by generating a sequence of enable signals. These signals activate appropriate ALU logic blocks to perform the required operation. (10, 11)

4. Introduction to VHDL:

VHDL is a hardware description language. It describes the behaviour of an electronic circuit from which the physical circuit can then be implemented. VHDL stands for VHSIC Hardware Description Language. VHSIC is itself an abbreviation for Very High Integrated Circuits. (12)

VHDL is intended for circuit synthesis as well as circuit simulation. Not all constructs are synthesizable even VHDL is fully simulatable. A fundamental motivation to use VHDL is that VHDL is standard, technology independent language, and is therefore portable and reusable. The main applications of VHDL are in the fields of Programmable Logic Devices (including CPLDs-Complex Programmable Logic Devices and FPGAs-Field Programmable Gate Arrays) and in the field of ASICs (Application Specific Integrated Circuits). (12)

VHDL statements are broadly classified into two categories

Sequential statement

Concurrent statement

Sequential statements: Statements that appear in a process or subprogram is said to be sequential. These statements are executed sequentially, that is one after another. If, case and loop statements are examples of sequential statements. (13)

Concurrent statements: AVHDL architecture contains a set of concurrent statements. Each concurrent statement defines one of the interconnected blocks or processes that describe the overall behaviour or structure of a design. Concurrent statements in a design execute continuously, unlike sequential statements. The two main concurrent statements include process statement and block statement. (14)

A final note regarding VHDL, contrary to sequential programs, its statements are inherently concurrent (parallel). Due to this reason VHDL is usually referred to as a code rather than a program. In VHDL, only statements placed inside a PROCESS, FUNCTION, or PROCEDURE are executed sequentially.

5. TASK A:

Design a Xilinx Spartan3 FPGA (XC3S200) using VHDL to function as a basic Microprocessor.

5.1. Design Methodology:

The processor design involves four sections. Every section is designed in a sequential order. The grouped sections are

A Logic Unit

Data Memory

Program Memory

Control Unit.

5.2. Section 1: Arithmetic Logic Unit

The Arithmetic Logic Unit or simply a Logic Unit is a sequential unit with a single Accumulator, in which to store intermediate data. The Logic Unit has a single 8-bit data input port, and a single 8-bit data output port. The Logic Unit should have four function pins (S0 - S3) to select the operation (opcode). The logic unit should flag for accumulator zero and for overflow.

5.2.1. Coding for Arithmetic Logic Unit:

library IEEE;




entity ALU is

Port ( DATA_IN : in STD_LOGIC_VECTOR (7 downto 0);



Flag : out STD_LOGIC;

SEL : in STD_LOGIC_VECTOR (3 downto 0);

ACCUM : inout STD_LOGIC_VECTOR (7 downto 0));

end ALU;

architecture Behavioral of ALU is




if rising_edge (clk) then

if EN = '1' then

if SEL = "0000" then

ACCUM <= "00000000"; ----- Reset

elsif SEL ="0001" then

ACCUM <= DATA_IN + ACCUM; -----Addition

elsif SEL ="0010" then

ACCUM <= ACCUM - DATA_IN; -----Subtraction

elsif SEL ="0011" then

ACCUM <= ACCUM AND DATA_IN; ----- ADD operation

elsif SEL ="0100" then

ACCUM <= ACCUM OR DATA_IN; ----- OR operation

elsif SEL ="0101" then

ACCUM <= NOT ACCUM; ----- NOT operation

elsif SEL ="0110" then

ACCUM(7 downto 1) <= ACCUM(6 downto 0); ---- Left Shift

ACCUM(0) <= '0';

elsif SEL ="0111" then

ACCUM(6 downto 0) <= ACCUM(7 downto 1); ----- Right Shift

ACCUM(7) <= '0';

elsif SEL= "1000" then

ACCUM <= ACCUM +1; ----- Incrementation

elsif SEL ="1001" then

ACCUM <= ACCUM-1; ----- Decrementation

elsif SEL ="1010" then

ACCUM <= "11111111"; ------ SET Accumulation

end if;

end if;

end if;

end process;

Flag <= '1' when ACCUM = "00000000" else '0';

end Behavioural;

5.2.2. Simulation of Arithmetic Logic Unit:

5.2.3. Description:

5.3 Section 2: Data Memory

The Data Memory (RAM) shall have an address width of four bits and capable of storing up to one byte (eight bits) of data at each address. In total 16 bytes of data can be stored. The data in the Data Memory can be written or read as part of the Control Unit Operation.

5.3.1. Coding for Program Memory:

library IEEE;




entity RAM is

Port ( clk : in STD_LOGIC;

en : in STD_LOGIC;

we : in STD_LOGIC;

addrs : in STD_LOGIC_VECTOR (3 downto 0);

din : in STD_LOGIC_VECTOR (7 downto 0);

dout : out STD_LOGIC_VECTOR (7 downto 0));

end RAM;

architecture Behavioral of RAM is

type ram_type is array (0 to 15) of std_logic_vector(7 downto 0);

signal RAM : ram_type;




if(clk'event and clk = '1') then

if(en = '1') then

if(we = '1') then

RAM(conv_integer(addrs)) <= din;

dout<= din;


dout<= RAM(conv_integer(addrs));

end if;

end if;

end if;

end process;

end Behavioral;

5.3.2. Simulation of Data Memory:

5.3.3. Description:

5.4. Section 3: Program Memory

The Program memory (ROM) must be capable of storing 16 lines of program code. Each memory line consist of a four bit operand and a four bit data address. The program code will be loaded into a program memory as part of the VHDL file. It will not be externally programmed. The operand selects the Logic Unit function to be executed.

5.4.1. Coding for Program memory:

library IEEE;




entity ROM is

Port ( CLK : in STD_LOGIC;


ADDR_DATA_IN : in STD_LOGIC_VECTOR (3 downto 0);

OPCODE : out STD_LOGIC_VECTOR (3 downto 0);

RAM_ADDR: out STD_LOGIC_VECTOR (3 downto 0));

end ROM;

architecture Behavioral of ROM is

signal ROM_LOG: STD_LOGIC_VECTOR (7 downto 0); ---- An internal signal of ROM_LOG is declared


process (CLK, EN)


if rising_edge (CLK) then

if EN = '1' then ---- if enable is 1(high)

if ADDR_DATA_IN = "0000" then

ROM_LOG <= "00001111"; ---- if data_in address is "0000" then ROM is equal to "00001111"

elsif ADDR_DATA_IN = "0001" then

ROM_LOG <= "00011110"; ---- else if data_in is "0001" then address of ROM is "00011110"

elsif ADDR_DATA_IN = "0010" then

ROM_LOG <= "00101101"; ---- else if data_in is "0010" then ROM address is "00101101"

elsif ADDR_DATA_IN = "0011" then

ROM_LOG <= "00111100"; ---- else if data_in is "0011" then ROM is equal to "00111100"

elsif ADDR_DATA_IN = "0100" then

ROM_LOG <= "01001011"; ---- else if data_in is "0100" then address of ROM is "01001011"

elsif ADDR_DATA_IN = "0101" then

ROM_LOG <= "01011010"; ---- else if data_in is "0101" then ROM address is "01011010"

elsif ADDR_DATA_IN = "0110" then

ROM_LOG <= "01101001"; ---- else if data_in is "0110" then ROM address is "01101001"

elsif ADDR_DATA_IN = "0111" then

ROM_LOG <= "01111000"; ---- else if data_in is "0111" then address of ROM is "01111000"

elsif ADDR_DATA_IN = "1000" then

ROM_LOG <= "10000111"; ----else if data_in is "1000" then ROM address is "10000111"

elsif ADDR_DATA_IN = "1001" then

ROM_LOG <= "10010110"; ---- else if data_in is "1001" then address of ROM is "10010110"

elsif ADDR_DATA_IN = "1010" then

ROM_LOG <= "10100101"; ---- else if data_in is "1010" then address of ROM is "10100101"

elsif ADDR_DATA_IN = "1011" then

ROM_LOG <= "10110100"; --- else if data_in is "1011" then address of ROM is "10110100"

elsif ADDR_DATA_IN = "1100" then

ROM_LOG <= "11000011"; ---- else if data_in is "1100" then ROM address is "11000011"

elsif ADDR_DATA_IN = "1101" then

ROM_LOG <= "11010010"; ---- else if data_in is "1101" then ROM address is "11010010"

elsif ADDR_DATA_IN = "1110" then

ROM_LOG <= "11100001"; ---- else if data_in is "1110" then ROM address is "11100001"

elsif ADDR_DATA_IN = "1111" then

ROM_LOG <= "11110000"; ---- else if data_in is "1111" then ROM address is "11110000"

end if; ---- end of 'if' statement

end if; ---- end of 'if' statement

end if; ---- end of 'if' statement

end process; --- end of process

OPCODE <= ROM_LOG (7 downto 4); ---- first four bits of ROM address is assigned to 'opcode'

RAM_ADDR <= ROM_LOG (3 downto 0); ---- remaining four bits are assigned to 'address of RAM'

end Behavioural;

5.4.2. Simulation of Program Memory:

5.4.3. Description:

5.5. Section 4: Control Unit

5.5.1 Coding for Control Unit:

5.5.2 Simulation for Control Unit:

5.5.3 Description:

6. Field Programmable Gate Array (FPGA):

6.1 Introduction to FPGA:

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by the customer or designer after manufacturing-hence field-programmable. The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC).

FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"-somewhat like a one-chip programmable breadboard. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.

6.2 Connectivity to SPARTAN 3 Kit:

Xilinx Spartan-3 FPGA w/ twelve 18-bit multipliers, 216Kbits of block RAM, and up to 500MHz internal clock speeds

-200 and -1000 versions available.

On-board 2Mbit Platform Flash (XCF02S)

8 slide switches, 4 pushbuttons, 9 LEDs, and 4-digit seven-segment display.

Serial port, VGA port, and PS/2 mouse/keyboard port

Three 40-pin expansion connectors.

Three high-current voltage regulators (3.3V, 2.5V, and 1.2V)

Works with Digilent's JTAG3, JTAG USB, and JTAG USB Full Speed cables, as well as P4 & MultiPRO cables from Xilinx.

1Mbyte on-board 10ns SRAM (256Kb x 32)


Fig 9 : Spartan S3 Board()

6.3 Download Design to the Spartanâ„¢-3 Demo Board

This is the last step in the design verification process. This section provides simple instructions for downloading the counter design to the Spartan-3 Starter Kit demo board.

1. Connect the 5V DC power cable to the power input on the demo board.

2. Connect the download cable between the PC and demo board.

3. Select Synthesis/Implementation from the drop-down list in the sources window.

4. Select counter in the Sources window.

5. In the Processes window, click the "+" sign to expand the Generate Programming File processes.

6. Double-click the Configure Device (IMPACT) process.

7. The Xilinx Web Talk Dialog box may open during this process. Click Decline.

8. Select Disable the collection of device usage statistics for this project only and click OK.

IMPACT opens and the Configure Devices dialog box is displayed.

7. Decisions:

Before starting with the coding, decisions were made to understand the basics. Every single operations like reset, AND operation, OR operations were checked individually instead of checking entire ALU. This helped in minimal of syntax errors. Errors could be identified and rectified easily using this method.

8. Problems and Errors:

The beginning part of simulation worked well even though I encountered some syntax errors.

Understanding various codes was bit difficult.

The designing of control Unit was tough as I had problems in understanding it.

Initially test bench output could not be obtained. Correcting errors helped in obtaining test bench.

Designing hardware could not be done due to lack of sufficient time.

Was able to study only the basics of hardware.

9. Critical Assessment:

The individual files of the microprocessor performing ALU, RAM, ROM and Control Unit is done using port mapping. The designing problem of control unit affected the entire module. Adding to it syntax errors and complications made the programming very difficult. Since every operation in the module was studied and performed individually errors could be minimized.

10. Conclusion:

The Designing and Implementation of Microprocessor on FPGA is partially fulfilled. ALU, RAM, ROM are done and executed correctly without any errors. As a result of problems faced in control unit, final output could not be obtained correctly. Designing hardware could not be done due to lack of sufficient time.