The main aim of the project is to develop a basic 4-bit parallel adder using carry look- ahead logic. In this project research we obtain knowledge about functional description of adder in parallel process of addition and developing at its fastest speed of addition. Basic reason is adders are basic components in any operation so if we develop the adders at high efficiently at high speed performances we change the technology nature rapidly. Carry Look Ahead Adder is developed such that to increase the speed by reducing the delay caused by waiting for carry in a basic ripple carry adder at each stage as carryout will be feed back as the next stage carry input.
Model architecture of a 4-bit carry look ahead adder, which is works developed based on carry look ahead logic. CLA logic is nothing but producing final carryout independent of intermediate carry feeding i.e., we find carryout by only depending on initial carry input and input bits value.
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Thus a carry look ahead adder developed in 3 generator stages. They are propagate generator, carry generator ( cla ) and sum generator. Such that there is no more such a delay developed cause by carry waiting at each stage. We can find carryout at each stage independent to sum output at present stage and generated carry at previous stage so in CLA adder operated as a perfect parallel process with respect to the initial values.
The developed logic will be implemented as a schematic using mentor graphics software. The function of CLA logic tested from obtained waveforms.
The performance and delay will be calculated and verified with truth table of different combination addition process even a carry feedback for the next stage 4-bit addition looping mechanism as well developed for a continuous process.
Layout of CLA adder will be designed as a blue print for final IC design blue-print.
The generation of technology developing in a rapid speed. That to approximately every six months a new generation such that every thing depends on the speed of processing. So every thing depends on data processing i.e., functional speed. In the end they need to speed-up operational speed. basically to do any arithmetic or logical operation Adder is a basic element. All the operations in control systems and digital system followed by addition. As we deal with binary 0 & 1 's all operations must be done in addition. Therefore in addition we need adders.In any operation, what ever may be the technology adders are the basic elements. So how fast and efficient the adder works will effect every thing in the system. Such that adders are developed for different applications in different way.
Adders are half adder, full adder and serial and parallel adders
All these adders used based on the application depending on the time delays, power consumption and architecture designs. But all adders based on the CMOS technology such their parameters are all most same.
Carry Look-Ahead adder is a parallel adder, in which carry will be calculated independent to the previous stage carry that to directly from given inputs. Thus addition by using CLA logic will made faster than ripple carry adder in which delay caused by carry feed to the next stage. Thus delay reduced by parallel processing at each stage.
CLA adder consists of three generator blocks. They are propagation generator, carry generator and sum generator where each stage followed by others respectively. Thus we get the sums and final carry out faster than basic adders.
TYPES OF ADDERS
Half adder is the adder witch is used to add two bits and its outputs as sum and carry of bits. Half adder build by EXOR gate for sum of bits and AND gate used for carry of the bits. We construct using k-mapping.
If A, B are adder inputs then Sum, S and Carry, C0 are,
Sum = A.B' + A'.B =A xor B
Carry = A . B
Full adder(1-bit serial adder):
Full adder is used to add three binary bits together and their sum and carry given as its outputs. Full adder is constructed by two cascaded half adders followed by or gate. we construct using k-mapping i.e., exor product of bits gives sum output of the bits and carry from two and gate and followed by a or gate.
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If A, B and CI are adder inputs then Sum and Carry are,
S = (A+B+CI)+(A.B.CI) = CI xor A xor B
CO = B . CI + A . CI + A . B = CI . (A + B) + A . B = CI . (A xor B) + A . B
Serial adder is a single full adder that is used to add two bits of data at a time by carry feed back to next stage of the inputs. In this carry will be stored for a bit of time and feed back so that the single full adder circuit is operated to add stream of 2 inputs data will be added one by one. Such that finally one carry out generated at the end and sum bits generated at each stage of input bits. This is a practical full adder that used to add a stream of two bits addition. It takes LSB bits first in addition. This is a very simple way of addition such that serial and less complex but much delayed operation.
As shown above serial adder is like a single bit full adder, where the Cout feeded to the next stage of Cin. such that serial adder is a simple and a bit delays expected in the feed back looping. But at low speed this is a perfect adder as it constructed cheeper and simple.
If Ai, Bi and Ci are the adder inputs then Si and Ci+1 are,
Si = Ci xor Ai xor Bi
Ci+1 = Bi . Ci + Ai . Ci + Ai . Bi = Ci . (Ai xor Bi) + Ai . Bi
The output is sum at each stage sums and a final catty output after all bits addition finished, even we get each stage carry output for reference.
RIPPLE CARRY ADDER (Basic Parallel adder):
Parallel adders are digital circuits that compute the addition of variable binary strings of equivalent or different size in parallel. parallel adder is nothing but a combination of Full adders as cascaded each other by connecting carry out of an adder to another carry in of next stage adder. In this we do more than one bit addition at a time so it going to be quicker than others. The full adder feed by carry at each stage of bit, so in simple ripple carry or carry propagate adder delay for the carry at each stage will be high. Therefore the waiting delay for each stage of carry makes adder very delayed. Such that ripple carry adder takes much delay but it is simplest and efficient design to use in low level systems.
The schematic diagram of a parallel adder is shown below.
As shown in above a Ripple Carry Adder is constructed in cascaded stages of full adders, such that as we allow a parallel processing of addition but on;ly delay occurred by waiting of next stage next stage carry in. Outputs are sum at each stage and a final carry out will obtained as shown.
If Ai, Bi, Ci are the adder stage inputs then, sum Si and carry out for next stage Ci+1 are, ( As like a serial adder out puts)
Si = Ci xor Ai xor Bi
Ci+1 = Bi. Ci + Ai . Ci + Ai . Bi = Ci . ( Ai + Bi ) + Ai . Bi
Carry look ahead adder:
From Ripple Carry adder, Such that to avoid the delay at each stage, other way is to find carry at each stage in advance that independent to intermediate carry from the previous stage just depending on the initial input values.
Where, no more delay at each stage occurred by carry feed back from previous stages and all the operations done at same time delay so there will be no much fluctuations in out comes.
As shown above it is model architecture of a 4-bit carry look ahead adder, developed in 3 generator stages. First stage is propagate generator, middle stage is carry generator and it followed by final stage sum generator .We can find carryout at each stage independent to sum output at present stage and generated carry at previous stage so in CLA adder operated as a perfect parallel process with respect to the initial values. The result is a reduced carry propagation time.
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To be able to understand how the carry look-ahead adder works, we have to manipulate the Boolean expression dealing with the full adder. The Propagate P and generate G in a full-adder, is given as:
If A and B are the inputs and C0 is carry input for a full adder then,
Carry out = A.C0 + B.C0 + A.B
Sum = A xor B xor C0
But at each stage,
Pi = Ai xor Bi Carry propagate
Gi = Ai . Bi Carry generate
Notices that both propagate and generate signals depend only on the input bits and thus will be valid after one gate delay.
The new expressions for the output sum and the carryout are given by:
Si = Pi xor Ci-1
Ci+1= Gi + PiCi
These equations show that a carry signal will be generated in two cases:
1) If both bits Ai and Bi are 1
2) If either Ai or Bi is 1 and the carry-in Ci is 1.
Let's apply these equations for a 4-bit adder:
C1 = G0 + P0C0
C2 = G1 + P1C1 = G1 + P1(G0 + P0C0)
= G1 + P1G0 + P1P0C0
C3 = G2 + P2C2 = G2 + P2 (G1 + P1G0 + P1P0C0 )
= G2 + P2G1 + P2P1G0 + P2P1P0C0
C4 = G3 + P3C3 = G3 + P3 (G2 + P2G1 + P2P1G0 + P2P1P0C0)
= G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0C0
These expressions show that C2, C3 and C4 do not depend on its previous carry-in. Therefore C4 does not need to wait for C3 to propagate. As soon as C0 is computed, C4 can reach steady state. The same is also true for C2 â€¦..C3.
The general expression is:
Ci+1= Gi + PiGi-1 + PiPi-1Gi-2 + â€¦â€¦. PiPi-1â€¦.P2P1G0 + PiPi-1 â€¦.P1P0C0.
As shown below the architecture of a Carry Look-Ahead adder will be constructed from the following derivations above such that in three stages, As the first stage as PG generator then followed by others. Where just after one gate delay we go to carry generator and sum generator simultaneously when it get the next stage carry. Such that it generates the sum and carry out parallel operation.
Above showed architecture of a fast CLA Adder but, we have a problem while constructing in Mentor Graphics software core library as max no. of input pin for NAND and NOR is 4 to 1. So we changed C4 as shown below Constructed CLA Adder in Mentor Graphics software with out much changes in speed and efficiency at best computation.
Such that C4 can be changed as,
Here the CLA adder is restricted to 4-bit parallel adder because as we go to the next stage such that 8-bit the CLA becomes not only complex it will be massive architecture. So we may get a bit faster but its almost negligible and even useless when compared to ripple carry adder. The efficiency will be very low and much delay as we use massive gates.
Such that 4-bit CLA is a best design and it will be universal CLA. For a 8-bit or 16 bit and even more bit CLA adder we use multiple 4-bit CLAs cascaded each other by feeding carry from previous stage and even it is always better than a ripple carry adder.
From the above obtained mechanism looks very good concept of developing CLA Adder but we have a big difficulty in achieving the speed in which the carry propagate and generate are not basic universal gates. So there is much gate delays are expected at each stage, and even more power dissipation and less efficiency.
Such that we need to develop the CLA logic using the basic universal gates at the initial propagate generator stage. Then only we can reduce the delay at a great extent. Even we get better efficiency.
Now we need to approach for a better CLA logic which based almost on basic universal gates. Research as follows,
In Mentor Graphics v.2005 software lab maximum pins available is 4-1 NAND in Core Library, so we have to change the C4 such that we can construct in mentor Graphis.
From the above research of better CLA logic we developed a best CLA Adder as we using the most of universal adders in operation.
The main concept involved in this research is using the best gate out of universal gates NAND and NOR gates in CMOS Transistor architecture.
So we developed by using NAND gate architecture of CLA adder.
As we know,
Diffusion constant of holes is always less than electrons.
In PMOS Transistor holes are majority carriers and in NMOS transistor electrons are majority carriers.
Holes, which represents an empty space in atom. An electron occupies this empty space leaving a hole, the same occurs for this empty hole. This results in an effective movement across semiconductor.
As electron mobility faster than hole mobility, NMOS Transistor is faster than PMOS Transistor as small electrons offer less resistance.
Such that we developed CMOS Technology by combination of Pull-up network of PMOS Transistors and Pull-down network of NMOS Transistors. All the CMOS gates are constructed using as shown below.
Constructed by, PMOS transistors in Pull-up network stage and NMOS transistors in Pull-down network stage.
OUTPUT going 1->0
Â The Pull-down NMOS transistors discharges the output capacitance.
OUTPUT going 0->1
The output capacitance is charged through Pull-up PMOS transistors.
CMOS logic is better logic than PMOS and NMOS implementations individually. Because PMOS transistors are great at transmitting a logic 0 to1 voltage without signal loss, NMOS transistors are great at transmitting a logic 1 to 0 voltage.
Constructed by, As shown above PMOS transistors in parallel and NMOS transistors in series.
OUTPUT going 1->0
Â The series NMOS transistors discharges the output capacitance.
OUTPUT going 0->1
The output capacitance is charged through parallel PMOS transistors.
Constructed by, As shown NMOS transistors in parallel and PMOS transistors in series.
OUTPUT going 1->0
Â The parallel NMOS transistors discharges the output capacitance.
OUTPUT going 0->1
Â The output capacitance is charged through series PMOS transistors.
why NAND gate is BEST,
As PMOS in parallel and NMOS in series the resultant transition delay at NAND gate is lesser than delay of NOR gate architecture.
To make PMOS as fast as NMOS we need enlarge channel and P-regions, but that leads to large silicon layout, and more cost and power wastage. So At same speed NOR is always larger than NAND. So it makes NAND more efficient than NOR. W/L ratio of NAND gate is smaller than NOR gate.
If inputs for gates are more then, NAND will be very faster than NOR.
So we use sop implementation rather than pos.
Thus we get a faster CLA logic developed NAND gate architecture of CLA Adder is shown below. This is faster in operation and efficient than all ICs discussed above.
Where inputs A0, A1, A2 and A3 are A bits and B0, B1, B2 and B3 are B bits. The outputs of CLAA are as S0, S1, S2 and S3 are Sum bits and C4 is the final Carry out.
This CLA Adder IC thermal and electrical properties are as same as CMOS ICs, as it developed using CMOS Technology.
For the 4-bit serial CLA Adder can be constructed based on 1-bit serial adder concept, by feeding C4 to the next stage bits addition using Flip-Flop at proper clock speed (i.e., half to input data rate).
For the 8-bit CLA Adder can be constructed based on parallel adder concept, by cascading adders on another and feeding C4 to next stage carry input.
The architecture is a fast CLA Adder but, we have a problem while constructing in Mentor Graphics software core library as max no. of input pin for NAND and NOR is 4 to 1. So we changed C4 as shown below Constructed CLA Adder in Mentor Graphics software with out much changes in speed and efficiency at best computation.
Where inputs A0, A1, A2 and A3 are A bits and B0, B1, B2 and B3 are B bits. The outputs of CLAA are as S0,S1,S2 and S3 are Sum bits and C4 is the final Carry out.
In the project of CLA Adder we obtained the knowledge about the functionality of adders and developed a fast adder using CLA Logic. We even obtain the knowledge about CMOS technology and functionality of IC Gates.
Finally from obtained results CLA waveforms, And Gate Architecture of CLA Adder is fastest in timing diagrams.
The CLA Adder IC can be used for one bit demo, as well as serial addition of 4-bit parallel inputs as well.
For 8-bit or more bits addition, CLA Adder can be used by cascading each others carry with another CLA adder as similar as Ripple Carry Adder.
Thus this CLA Adder can be used to find sum of 1 bit to x-bits in different- different stages of addition.