The P6 Micro Architecture Computer Science Essay

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The Intel was founded by Gordon E. Moore who is also known a chemist and physicist, he was accompanied by fellow physicist Robert Noyce. Together they started a company called NM Electronics; later on they named it Integrated Electronics in short it was called as Intel. In the year 1971 Intel introduced its first designed microprocessor named "The Intel 4004" and in the very next year, that is in the year 1972 introduced first microcomputer. Intel's primary aim in 1980's was Random Memory Access (RAM). In early 1970's, a client from Japan wanted Intel to design twelve chips for their calculators. So they thought of designing a one single chip instead of twelve microchips and this idea made history and the project for designing a chip was successful with the Intel 4004 microprocessor which measured 1/8th inch by 1/6th long and it consisted of 2,300 transistors.

Intel' most successful 16- bit processors, that is, 8086 and 8086 were the forefathers of the IA- 32 architecture, developed in the year 1978, the Intel 8086 microprocessor sported 1MB addressing capability with 20 address lines and 16-bit external data bus and both 8086 and 8086 were introduced with a 16 bit register which directed to a memory segment of 64 kilo bytes. In the year 1982, the Intel 286 processor was introduced and along with that, to protect virtual memory management, the protected mode of operation, then 386 was brought in the year 1985, which was in fact was Intel's first 32-bit processor. The 386 processor supported some important features like, it supported 32-bit address space with 4GB memory, a segmented and a flat memory model and it also supported paging mode for virtual memory management for further support. In the year 1989 Intel brought 486 processor and for the first time level 1 cache was introduced along with power saving mode and other system management.

The Pentium Pro (P6)

In the year 1995 the Pentium pro, which is a sixth generation microprocessor was manufactured. It introduced i686, the main aim of i686 micro architecture was to replace the Pentium in all the applications. The Pentium pro or generally referred as P6 introduced three-way pipelined architecture, that is, P6 on an average is capable of dispatching, decoding and completing three instructions per clock cycle. In order to perform this task, the Pentium pro used a decoupled and twelve stage super pipeline which would support out of order execution of an instruction.

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P6 Micro-architecture

In the P6 micro-architecture, there are main three data processing concepts, which can be referred as heart of P6. First one is deep branch prediction, which allows the P6 processor to decode the instruction beyond branches. Second one is dynamic dataflow analysis, which allows the processor to monitor the flow of data, so that it can take the advantage of execution opportunities. Third one is, speculative execution, it allows the processor to enable and execute the instructions which are beyond the conditional branch, which not yet have been resolved.

Basic Modes of Operation

The IA-32 can operate in one of the three modes they are protected mode, real-address mode and system management mode. Protection mode or generally referred as native or optional mode of the central processing unit like (x86 compatible), which allows the system software to utilize certain features like paging, multitasking, virtual memory etc., to increase operating system control over the software applications, when the protected mode is powered on, it starts executing the instructions in the real mode to maintain backward compatibility. Programming model of the 8086, used for backward compatibility

Real addressing mode is generally referred as real mode; this mode was designed based on the programming model of the 8086, which was used for backward compatibility. It is an operating mode initially supported by 80286 and later on supported by x86 compatible central processing units. Real mode is designed in such a way that, it can provide 20 bit segment memory address space or 1MB and direct access to all I/O addresses , memory and peripheral hardware's but it does not provide any security and protection for code at the privilege level, memory protection and multitasking.

System management mode is one of the operating modes in which all the low privilege modes are suspended such as memory chipset errors, managing system safety functions like in case of system shutdown at high CPU temperature, power management control management operations such as regulating voltage and high priority mode are executed such as hardware assisted debugger and usually firm ware.

Memory Model

The IA-32 memory model can be classified in three different models; they are flat memory model, segment memory model and real-address memory model.

Flat memory model is also referred as linear memory model, it is a low-level software design for memory addressing such that all the memory locations are directly available to the central processing unit (CPU) without paging and segmentation schemes. The flat memory model memory appears as a single, continuous address space from 232 bytes and this same address space consists of code, stack and data, that's why it is also referred as linear address space. The advantage of using flat memory model is that it provides clean design and simple interface for programmers, it is flexible and requires minimum hardware and also it provides maximum execution speed but it is not suitable for multitasking OS, unless it is enhanced with some advanced features like memory management in hardware and software. But this is the case with all the modern CISC processors; they generally implement enhanced memory management and also protection over flat memory model.

Segmented Memory Model is reverse of flat memory model, in fact in the segmented memory model the memory appears as a group of individual memory segments to the program, where as code, stack and data contain different memory segments. It is one of the powerful and most frequently used methods to achieve memory protection apart from paging. In the modern computer systems, by using segmentation an instruction operand which directs to a memory identifies a segment with the value and an offset in the same segment. The advantage of using segment memory model is that it is similar to the paging and it is flexible and also provides variable page boundaries but according to a programmers point of view it is very awkward and complex as it difficult for the compliers and it is poor in resource protection. Programming error does happen on a large scale.

16,383 different segments can be accessed and each can be addressed up to 232 bytes, by running the program in this mode. Only reason for using segmented memory is to enhance the system reliability like preventing corruption of stack

Real- address memory model is one of the memory models and it is actually original 8086 memory model and it is used to provide backward compatibility

Paging and Virtual Memory

By using the paging mechanism , the processors physical address can be directly mapped to its linear address by using the first two memory models that is, flat memory model and segmented memory model. When paging mechanism is enabled in IA-32, the linear address space is divided into pages and then they are mapped to the virtual address space and it is consequently mapped into the physical address space according to the require ment.

The Register Model

Numerous number of special and general purpose registers are provided by IA-32 they are:

General Purpose Registers - they are set of eight registers mainly for storing operand as well as pointers

Segment Registers - all together there are six segment registers provided by IA-32

In segment registers, the individual segments in the memory are identified by segment selectors but actually they are special pointers. It is used based on the memory model being used presently for example- for the flat memory model, the segment registers direct towards overlapping segments, each of which starts with address 0 but other memory model that is, the segment memory model each memory address is loaded to different segments

EFLAGS Register - this is also known as enable flag register it controls the status and control register.

EIP Register - It is also referred as instruction pointer register, it is a 32-bit Instruction Pointer, pointing towards the next instruction which has to be executed

Real versus Protected Mode

Real Mode:

Protected mode and real mode are not entirely different from application point of view but in real mode, segment registers handle the memory segments internally and segments are nothing but the part of the physical address

Protected Mode:

In the protected mode of operation the memory segments are assigned by a set of tables generally referred as descriptor table and these segment registers just a pointer to these tables and hence in the protected mode of operation, segment registers are not the part of address

ARM Ltd

ARM company was founded in the year 1990 in the month of November as Advanced RISC machines limited and it was actually joint venture structured between the Apple computers, VLSI technology and Acron computers, its first recognized was in the year 1993, which was in fact its first profitable year. Later on it spun out of Acron , In the 1994 the companies' Silicon Valley and Tokyo offices were opened. In the year 1994, Advanced RISC machines limited which is presently now known as ARM holdings, invested in a company called Plamchip Corporation in order to provide a system on the chip plat form and to make a platform in the disk drive market.

ARM designs, ARM range of RISC processor cores and also it licenses its designs to semiconductor partners who intern fabricate and sell to their customers but ARM does not fabricate silicon itself. It develops technologies to assist with design of ARM architecture such as boards, application software peripherals, software tools, debug hardware, bus architectures etc.

Instruction Sets and Data size

ARM is 32 bit architecture and when using in relation to ARM following has to be taken into consideration

Byte means 8 bits

Halfword means 16 bits (two bytes)

Word means 32 bits (four bytes)

Most ARM's implement two instruction sets

32-bit ARM Instruction Set

16-bit Thumb Instruction Set

Processor Modes

The Advanced RISC Machine has seven basic operating modes:

User: it is an unprivileged mode, all the tasks run under this mode.

FIQ : when an high priority interrupt is raised it is used

IRQ :when a low priority interrupt is raised it is used

Supervisor : it comes into picture when reset is called and when software instruction is executed

Abort : memory access violations are handled

Undef : undefined instructions handled

System : privileged mode using the same registers as user mode

The Registers

ARM has 37 registers; every register is 32 bits in length. It also has the following:

It has 1 dedicated program counter which points to next instruction to be executed.

It has 1 dedicated current program status register

It has 5 saved program status registers

It has 30 general purpose registers

The present processor mode enables which of the following banks are accessible at appropriate time.

It consists of a particular set of from r0-r12 registers and a particular r13 the stack pointer, and r14 the link register, lr

the program counter is r15 (pc) and

the current program status register, cpsr

Program Counter (r15)

When the processer is running and executing in the ARM state, all the instructions must be 32 bit long, it must be word aligned, hence the program counter stores the values in form of bits and bits being undefined as the program counter cannot read the instructions which are byte aligned and half word. When it is in the thumb state all the instructions must be 16 bits long and it must be halfword aligned, hence the program counter in the thumb state store the values in the bits and with zero bit being undefined. When it is in Jazelle state the instructions must be s8 bits wide and the processor reads 4 instructions at once

Introduction - RISC and CISC

There used to be a time when CPUs utilized either RISC or CISC but now the things have changed as modern CPUs utilize both the features based on the requirement. The following are some RISC features:

Fewer Instructions

Fixed instruction length

Fixed execution time

Lower Cost

Some exceptions of CISC

It is an Embedded Processors , which generally makes it bit complex

CISC is unsuitable

It has high MIPS/watt ratio

High Power consumption

Heat dissipation is more

Simple Hardware equal to integrated peripherals

CISC to RISC

The Intel Corporation, who is the famous advocates of CISC and HP also uses the same in IA-64. These are the few properties of CISC OVER RISC.

Migrate to a Common Instruction Set.

Creating Small Instructions

More concise Instruction Set.

Shorter Pipeline

Lower Clock Cycle

Abandon the Out-of-order Execution In Hardware

Depend on Compiler to Handle Instruction Execution Order. Shifting the Complexity to Software.

RISC to CISC

Additional registers

On-chip caches (which are clocked as fast as the processor)

Additional functional units for superscalar execution

Additional "non-RISC" (but fast) instructions

On-chip support for floating-point operations

Increased pipeline depth

CONCLUSION

Low power solution .

Using its low power atom chips.

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