Built-in Self Test, or BIST, is the technique of implementing additional hardware and software features onto the integrated circuits to perform self-testing, that is testing of their own parametric and functional operations using their own circuits, which reduces the dependency on an external automated test equipment (ATE). BIST is a Design-for-Testability (DFT) technique, because it makes the electrical testing of a chip easier, faster, more efficient and less costly. The concept of BIST is applicable to just about any kind of circuit, so its implementation can vary as widely as the product diversity that it caters to. In integrated circuits, BIST is used to make faster, less-expensive manufacturing tests. The IC has a function that verifies all or a portion of the internal functionality of the IC. For example, a BIST mechanism is provided in advanced field bus systems to verify functionality. At a high level this can be viewed similar to the PC BIOS's Power-On Self-Test (POST) that performs a self-test of the RAM and buses on power-up.
Built In Self Test (BIST), which was initially reserved for complex digital Integrated Circuits, can now be found in many devices with relatively small amounts of digital content. The move to finer line process geometries has enabled several analog devices that converters to include BIST functionality.
For the chip manufacturer, BIST can help simplify the process of device characterization by allowing autonomous testing of some small contents of the chip. Even larger benefits of BIST are realized at the system level when on-chip BIST functionality is incorporated into the system level design. As systems become more complex, integrating individual components with BIST, a hierarchical test strategy can be implemented which provides a powerful feature for improving the reliability of the system.
Functionality of BIST At the system level can be used in the design phase to characterize digital interface timing between the data converters and digital processors. Without BIST, bit errors in the digital interface must be detected by changes in the converter's noise floor. This type of error detection is much less sensitive than a digitally based BIST signature check, which can detect single bit error. This same digital interface check can be performed on the production test floor, or in system level self tests in the field.
Fig 1 : Block Diagram of Built in self test
The above block diagram shows implementation of Built In Self-Test. Implementation of BIST into a device requires the addition of three functional blocks: a pattern generator, a signature analyzer and a test controller. The pattern generator stimulates the circuitry under test. The signature analyzer gathers the test's response to the test pattern and compresses it to single value, which is referred to as signature. The test controller co-ordinates the actions of the test circuitry and provides a simple external interface.
Pattern generators and signature analyzers are often implemented with linear feedback shift registers (LFSR). This type of pattern generator can produce pseudorandom patterns of width n, with 2n-1 unique combinations before repeating (every possible combination except all zeros). The pattern is completely deterministic when the initial conditions are known.
Signature analysis also makes use of LFSRs. Utilizing a second similarly constructed LFSR makes it possible to compress the test's response to the entire pattern into a single value. This value is stored in a register at the completion of the test. The signature can then be compared with the expected signature to verify correct operation of the device. The process of compressing the response introduces the possibility to produce a correct signature, but the probability of a fault going undetected becomes vanishingly small as the pattern length increases.
LFSRs are also used in signature analysis. Utilizing a LFSR it makes it a possibility to compress the entire pattern of the test's response into a single value. This value is stored in a register at the completion of the test. The signature can then be compared with the expected signature to verify correct operation of the device. Compressing the response introduces the possibility of enabling a faulty CUT to produce a correct signature, but the probability of a fault going undetected decreases as length of the pattern increases.
The different techniques of Built In Self Test which are discussed in this paper are,
Programmable BIST (P-BIST)
Memory BIST (M-BIST)
Analog and Mixed Signal BIST (AM-BIST)
III. PROGRAMMABLE BIST
Programmable Built-In Self-Test (PBIST) is a memory Design For Testability feature that incorporates all the required test systems into the chip itself. The test systems implemented on-chip is,
algorithmic address generator
algorithmic data generator
program storage unit
loop control mechanisms
PBIST was originally adopted by large memory chips that have high pin counts and operate at high frequencies, thereby exceeding the capability of production testers. The purpose of PBIST is to avoid developing and buying more sophisticated and very expensive testers. In order to support all of the required test algorithms, PBIST must have the capability to store the required programs locally in the device.
PBIST are mainly used in memory handling hardware modules like ROMs, SRAMs and DRAMs test and diagnosis. Below given is the architecture of PBIST implemented for a DRAM.
Fig 2: Block Diagram of PBIST for DRAM core
The proposed architecture explains testing cores embedded in SoCs, which can also be used also for stand-alone DRAMs. In the former case, BIST architecture and protocols can be included in the ATE stimuli unit to autonomously generate patterns and compare responses.
A compact but effective and widely employed set of the possible defect effects on memory cell arrays is the collection of reduced functional faults, which are,
Stuck-at Fault (SAF): the logic value of a cell or line is always 0 or always 1
Transition Fault (TF): a cell fails to make a 0 to 1 (up) transition or a 1 to 0 (down) transition when it is written
Coupling Fault (CF): a transition in memory bit j causes an unwanted change in memory bit i
Bridging Fault (BF): a short circuit between two or more cells or lines.
State Coupling Fault (SCF): the coupling cell/line j is in a given state y that forces the coupled cell/line i into state x
Neighbourhood Pattern Sensitive Coupling Fault (NPSF): the content of cell i (or the ability of cell i to change) is influenced by the contents of the neighbouring cells, or by the operations performed on them.
IV. MEMORY BIST
Memory BIST can be best used for testing memory modules. Due to the area constraints of the chips and increase in number of pins of an IC, having a configurable memory BIST architecture that can test different memory configurations is essential which is proposed here. The proposed idea has enough flexibility for applying different test algorithms. Given below is the architecture of a simple Memory BIST implementation.
Fig 3: Memory BIST architecture
Figure 3 explains the main part of the configurable memory BIST architecture. The memory to be tested is shown in gray and solid line blocks which represent circuitry of the test. Test data which is to be applied is generated by this MBIST circuitry and applied to the memory. As data is being read from the memory, it is compared with the reproduction of the same data that was written into specific memory locations. After writing and Reading all locations expectation is that, all data read from the memory to be the same as those that were written into it.
With this architecture, it is required to set the desirable test algorithm and memory size that is the length and the width in the script file. As the architecture is fully configurable, all memory parameters are automatically set.
V. ANALOG AND MIXED SIGNAL BIST
Most significant analogue and mixed-signal built-in self-test Approaches have been explained briefly which gives an overview of testing methodologies of BIST. The use of built-in self-test (BIST) for high volume production of mixed signal ICs is desirable to reduce the cost per chip during production-time testing by the manufacturer. In addition to this, it helps in diagnosis in the field.
The digital patterns are generated by the shift register with an associated feedback network for digital BIST. The pattern is manipulated to provide defined conditions for both the generator and the analogue sub-circuits.
Given below is the basic Architecture of AM-BIST.
Fig 4: test stimulus generator
Output response analysis can be done by matching the outputs of two identical circuits. This can be made possible if the function designed leads to replicated sub-functions or because the circuit is duplicated redundantly for concurrent checking. When identical outputs are not available, test response can be analyzed by three main approaches.
In the first approach, the analogue BIST includes analogue checkers which verifies the parameters for the known input test signals. An analogue checker extracts the value and compares this value with two reference values which correspond to the minimum and maximum deviations acceptable for the parameter. The checker includes a circuit to extract the parameter. A window comparator with tolerance window Pmin and Pmax takes into account the imprecision of the analogue signals.
The second approach consists on the generation of a signature that describes the waveform of the output response. Since, it is impossible to compare the fault-free and test response at each sample of the signal, it is required to stick to some techniques for comparing the output response. The method has the property that if the input is not precise within certain acceptable bounds, then the generated signature is also imprecise within certain acceptable bounds.
As shown below in Fig 5, the compression scheme uses a digital integrator similarly as it has been done for digital circuits.
Fig 5: Analog Signature Analyzer
The third approach is based on the conversion of the analog test responses into digital vectors which are then fed into a multiple-input signature register (MISR). However, the scheme using integrators seems to lead to a smaller area overhead. On both cases, merits can be taken from hardware which already exists in the functional design.
Built In Self Test is a technique of testing the circuit or the system by a small component of the hardware embedded inside itself to provide full and complete testing of all the components and pins of the circuit. This helps in self testing without any extra care taken by the user or customer to test the circuit if it is working properly. By this, testing time is improved. Since BIST is embedded inside the circuit, it would be precise in its testing as the circuit for test is well known.
Thus by using BIST cost of testing is cut down by a large amount and also quality of the product is assured which plays a very important role in the production of the company.
VII. FUTURE WORK
BIST is fast becoming an alternative solution to the rising costs of external electrical testing and increasing complexity of devices. This approach will find greater deployment in a wider variety of circumstances as more and better BIST techniques are developed. This does not mean, however, that BIST will eventually replace external electrical testing altogether. Still, BIST proponents are optimistic that BIST will someday be the preferred mode of testing, instead of being merely an alternative to external ATE testing as it is today.
. "A Programmable BIST for DRAM testing and diagnosis",
P. Bernardi, M. Grosso, M. Sonza Reorda and Y. Zhang
. "Configurable Architecture for Memory BIST", Atieh Lotfi, Parisa Kabiri and Zainalabedin Navabi
. "Built-in Self-test Approaches for Analogue and Mixed-Signal Integrated Circuits",
S. Mir, M. Lubaszewskiltt, V. Liberali and B. Courtois