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There has been an ongoing struggle in Information Technology field to minimize manufacturing cost, to enable much smaller size and to reduce power consumption of a processor while getting maximum processing power out of it. In recent times, this goal has been achieved by the creation of much complex integrated circuits such as Application Specific Integrated Circuit chips, Random Access Memory chips, and so on. These advancements have made way for development of the System on Chip. System on chip refers to integration of all components of computer or any other electronic system into a single integrated circuit. It contains a processor, a bus and other elements on a single substrate as well as various components like volatile memory systems, non-volatile memory systems, and data signal processing systems, mixed signal circuits and logic circuits which are formed into separate units and then integrated on a single chip. Digital devices using System on Chip have replaced much larger, bulkier and power consuming systems built on multiple chips. This is no less than a revolution in the IT field. This research paper critically analysis the transformation of typical digital systems into System on Chip, the revolution in technology that it brought , its strengths and weaknesses and suggestions that cater to eliminate those weaknesses so that a much more useful and beneficial system is established.
Keywords: High Speed Computing, Homogenous System-On-Chip, Heterogeneous System-On-Chip, Network on Chip, System on Chip.
INTRODUCTION OF SYSTEM-ON-CHIP:
In today's fast pacing world, there is an ever increasing need of technology advancement in term of performance. Previously there were mainframes, then microcomputers, then PC's and laptops. Hence more advanced the technology is, smaller is the size so much so that all the computer components have been integrated on a single chip, known as System-on-chip. This advancement has made waves in the field of computer science and engineering. A System-On-Chip integrated circuit incorporates all the electronic components, including analog and interface circuitry, required to implement a system on a single chip. System-On-Chip designs usually consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. And with fewer packages in the system, assembly costs are reduced as well. A System-On-Chip consists of both the hardware and the software that controls the microcontroller, microprocessor or DSP cores, peripherals and interfaces. The design flow for System-On-Chip aims to develop hardware and software in parallel.
Construction of System-On-Chip:
System-On-Chip not only chips, but more on "system".
Applications of System-On-Chip:
The technological advances means that the whole system housed on a single chips this provides easy access for the user. System-On-Chip provides this facility and includes different applications.
Programmable System-On-Chip technology from Cypress Semiconductor tackles the design complexity and the required hardware skill issues by fixing the components that are common to most embedded systems including the processor, and incorporating a high-level configurable Digital Block and interconnect design.
2-Multi Processor System-On-Chip:
The multiprocessor system-on-chip uses multiple CPUs along with other hardware subsystems to implement a system.Multi Processor System-On-Chip arewidely used in networking, communications, signal processing, and multimedia among other applications.Multi Processor System-On-Chip constitutes a uniquebranch of evolution in computer architecture, particularly multiprocessors, that is justiï¬ed by the requirements on these systems: real-time, low-power, and multitasking applications.
3-System-On-Chip for Real-Time application:
Real-Time does not mean that keeping deadlines or speed cost. It may provides short time to implement and deterministic in behavior. Real -Time opens the path for high efforts when porting to different operating system.
The newly built Multiprocessors contain huge amount of software and rely on complex hardware designs. As complexity of applications grows system-on-chip prototyping flow based on Programmable System-On-Chip demand is also increases.The diagram describes the relation of System-On-Chip applications and core concepts:
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Future use of System-On-Chip:
There are so many applications which are working on System-On-Chip technology and trying to improve it more.
Hybrid ASIC helps in enhancing the basic performance through its System On-Chip technology. It reduces the size and cost of the system. We can utilize the benefit of standard cell logic and already structured ASICS in data encryption and compression.
The chip may include standard cell logic, peripheral and the latest technology of already configured IP logic.
interconnect IP node:
The intelectual property node architecture is introduced for felexible communication via chip. This architecture is designed for the communication in future gigatransistor System-On-Chip designs. The IPs will be used as a testing platform when the efficiency of network topologies and routing schemes are investigated for on-chip environment. The node is constructed from a collection of parameterized and reusable hardware blocks. In the future the IP node forms a basic building component in System-On-Chip implementations.
Technology leading to the millions of gates a chip, the system evolution integrating as a new paradigm allowing that the entire system to be build on a single chip. Rapidly develop, manufacture, test, debug and verify complex SOCs is crucial for the continued success of the electronics industry. This growth is expected to continue full force at least for the next decade, while making possible the production of multimillion transistor chips. However, to make its production practical and cost effective the industry road maps identify a number of major hurdles to be overcome. The key hurdle is related to test and diagnosis. This embedded tutorial analyzes these hurdles, relates them to the advancements in semiconductor technology and presents potential solutions to address them. These solutions are meant to ensure that test and diagnosis contribute to the overall growth of the SOC industry and do not slow it down. This embedded tutorial in addition presents the state of the art in system-level integration and addresses the strategies and current industrial practices in the test of system-on-chip. Future research challenges and opportunities are discussed in enabling testing of future SOCs which use deep submicron technologies.
Basic techniques of System-On-Chip:
There are two types of System-on-Chip techniques to impalement which are Heterogeneous and Homogeneous System-On-Chip. The pre-faceted circuits are known as circuit cores which provide diversity in computing. The homogeneous designs are simpler to use and these are suitable for a wider range of applications, advantages that come at the cost of performance and efficiency. Heterogeneous solutions which incorporate more specialized processing elements gives some generality and ease of use in exchange for being more efficient in their target applications.
Design of System-On-Chip:
The System-On -Chip design concept follows traditional design flows. In early days silicon and design automation technology has facilitated the integration of more functionality on a single piece of silicon, as the advancement of silicon technology and the availability of transistors on a single die, these emerge the new design challenges. In the early days the designers challenged to place as such functionality as possible. Now a day the number of available transistors exceeds the requirement to complete a full system traditionally, designers focused on creating original design content and verifying it. The new approach shifts the content based approach to the compositional approach. In the new approach, designers deal with evaluating, integrating and verifying the components.
The System-On-Chip revolution will bring this technology to a broader spectrum of users. Furthermore, recent industry developments are setting the stage for more Widespread use. The emergence of multi-core System-Level Integration (SLI)
Platform chips and the increasing standardization of peripheral interconnect Enables critical design efficiencies and standardized architectures. These
Efficiencies are critical elements both in the proliferation of electronic systems and in the use of System-On-Chip design methodology to create them in a single chip.
The SoC consists of both the hardware and software that controls theÂ microcontroller,Â microprocessorÂ orÂ DSPÂ cores,Â peripheralsÂ and interfaces. The designÂ for a SoC aims to develop this hardware and software in parallel. A key step in the design flow isÂ emulation it involves hardware mapped onto an emulation platform based on aÂ FPGA that mi the behavior of the SoC, and the software modules are loaded into the memoryÂ of the emulation platform. Once programmed, the emulation platform enables the hardware and software of the SoC to be tested and debugged at close to its full operational speed. When the emulation of the hardware of System-On-Chip route and placement phase of the design of an integrated circuit before it fabricated. The correctness of logic of the chip is verified before it send to the foundry, this process is called functional verification and it will account for the energy and time that expend in chip. The System-On-Chip design flow is shown below:
Stage One. C:\Documents and Settings\user\My Documents\Downloads\images (2).jpg
Stage One: This phase includes creating a design and estimates the optimal solution.
Stage Two: This phase includes development of specific processors, blocks and register transfer level. Model design description for home project by using home way design level language which includes Hardware Description Language (HDL).
Stage Three: This phase covers the source description of whole project is using discrete register transfer level for manufacturing NET List is used.
Stage Four: This phase includes the description of physical topology of System-On-Chip individual block in specific Performa is obtained. After completing these phases desired product System-On-Chip is found.
The general methodology, based on Hardware Description Languages (HDL) and Field Programmable Gate Array (FPGA) prototyping is developed. HDL focused on solutions to emerging areas in multicore System-on-Chip (SoC) infrastructure and product development.
During synthesis, the HDL files are translated into gates and optimized for the target architecture. User Constraint File (UCF) style syntax is used to define synthesis and timingÂ
constraints. Such as the physical pin location for a particular Input output connection from FPGA internal signal to the outside world.
IP cores are pre-designed complex functional blocks. According to their properties, IP cores can be distinguished into three types of cores: soft-cores, firm-cores, and hard-cores.
The Reusable synthesizable RTL or net list of generic library elements is involved.
It involves the structurally and topologically optimized for performance and area through floor planning and placement.
The Reusable blocks optimized for performance, power, size and mapped to a specific process technology are used.
System-On-Chip design relies on using existing Intellectual Property (IP) blocks. This will raise the design time and cost. Designing using IP components raises issues in validation and testability. The SoC approach forces the designer to start thinking about a test strategy, prior to the commencement of the design phase. The validation strategies will need to test subsystems and the whole system.http://images.vertmarkets.com/crlive/files/Images/AF4D729A-2204-11D5-A770-00D0B7694F32/032701akembedded1.gif
The productivity gap is removed by the Intellectual property (IP).
InÂ integrated circuit design,Â register transfer levelÂ (RTL) is a level of abstraction used in describing the operation of aÂ synchronousÂ digital circuit. In RTL design, a circuit's behavior is defined in terms of the flow of signals betweenÂ hardware registers Â performed on those signals. Register transfer level abstraction is used inÂ hardware description languagesÂ (HDLs) likeÂ VerilogÂ andÂ VHDLÂ to create high-level representations of a circuit, from which lower-level representations and ultimately actual wiring can be derived.
In general, these design methodologies can be grouped into four groups:
â€¢ Area-Driven Design (ADD)
â€¢ Timing-Driven Design (TDD)
â€¢ Block-Based Design (BBD)
â€¢ Platform-Based Design (PBD)
These design methodologies are differentiated by their design capacity, level of Reusable block and the design technology used in creating the design.
Area-Driven Design (ADD) is the most basic and the simplest methodology used in creating ASIC designs. The main ADD activity is in logic minimization. The synthesis optimization is to produce the smallest design which can meet the intended functionality. In this methodology, no floor planning information is used at the RTL or gate level analysis. ADD can be identified by two linchpin technologies includes RTL logic synthesis tools and gate-level simulators.
Timing-Driven Design (TDD) is a methodology for optimizing a design in a top down, timing convergent manner. It is driven by the design requirement for meeting performance or power consumption. The methodology is used to achieve a moderately sized complex ASIC design.
Block-Based Design (BBD) is the design methodology used to produce designs
that are reliable, predictable, and can be implemented by top-down partitioning of the design into hierarchical blocks. It introduces the concept of creating
a system by integrating blocks of pre-designed system functions into a more complex one.
Platform-Based Design (PBD) is a methodology which is driven to increase productivity and time to market by extensively using design reuse and design hierarchy. It expands the opportunities to speed-up the delivery of derivative product.
SoCs can be fabricated by severalÂ technologies, including, Full custom, Standard cell, FPGA. SoC designs usually consume less power and have a lower cost and higher reliability than the multi-chip systems that they replace. And with fewer packages in the system, assembly costs are reduced as well. However, like mostÂ VLSIÂ designs, the total cost is higher for one large chip than for the same functionality distributed over several smaller chips, because ofÂ lower yield sand higherÂ NREÂ costs.
Applications of System-On-Chip:
There are many applications utilize the System-On-Chip facilities which are discussed above. One of the main application is Network-On-Chip which introduces next.
Network-on-ChipÂ orÂ Network-on-a-ChipÂ is an approach to designing the communication subsystem betweenÂ IP coresÂ in a System-on-a-Chip. Network-On-Chip can span synchronous and asynchronous clock domains or use unlockedÂ asynchronousÂ logic. applies networking Â theory and methods to on-chipÂ communicationÂ and brings notable improvements over conventionalÂ busÂ andÂ crossbar interconnections. Network-On-Chip improves the scalability of SoCs, and the power efficiency of complex SoCs compared to other designs