Single Clock Cycle Mips Risc Computer Science Essay

Published:

In this project, the Datapath and control unit have been designed for implementation of the MIPS instruction set. A processor has been designed that includes a subset of the MIPS core instruction set: i) the memory reference instructions such as load word (lw) and store word(sw) ii ) the arithmetic logic instructions add, sub, and, or, slt iii) the conditional instructions such as branch equal and jump. This subset does not include all the integer instructions (for example multiply and divide are missing), nor does it include any floating point instructions. All the major components that are required for the data path design and control unit have been coded in VHDL language and simulated using XILINX 13.2 and synthesized using XILINX ISE 13.2 individually. The complete architecture has been simulated using XILINX 13.2 and synthesized using XILINX ISE 13.2. We used XILINX Spartan3 xcs400pq208 for placement routing to generate plan overhead. The complete architecture of the processor uses 85 no. of IO's and 457 no. of 4 input LUT's. The simulation result has been verified by downloaded the complete VHDL code of processor into the field programmable gate array trainer kit of XILINX Spartan3 xcs400pq208.

ACKNOWLEDGEMENT

Lady using a tablet
Lady using a tablet

Professional

Essay Writers

Lady Using Tablet

Get your grade
or your money back

using our Essay Writing Service!

Essay Writing Service

Firstly I would like to express my gratitude to my tutor, Mrs. Rumi Rastogi Project Faculty, Electronics & Communication, Inderprastha Engineering College Ghaziabad and for the opportunity to work on my M.tech thesis under her guidance. She has provided me invaluable help with ideas and discussions throughout my entire time working on this thesis. It was both an honor and a privilege to work with her.

I would like to thank the entire Electronics and Communication Engineering Department, and specifically, Prof. A.K. Giri (HOD) and Prof. M.S. Giri (M.tech Co-ordinators), for massive support with tools and ideas.

A very special thank you goes out to my Govind Sir for the given motivation and support. He patiently tolerated the absence of my person during the project development as well as during the thesis writing when I retreated to long days with my computer. The burden of writing this thesis was substantially mitigated by the support and humor of my lab mates; Ankit, Preeti, Nikhil, Nitin. Thank you for your recommendations and good company.

List of Tables

Table 2.1 MIPS Instruction Fields

Table 4.1 How the ALU control bits are set depends on the ALUOp control bits and the different function codes for the R-type instruction

Table 4.2 The Effect of the Seven Control Signal

Table 5.2 Control Input for R-type

Table 5.3 Control Input for Load

Table 5.4 Device Utilization for ALU

Table 5.5 Device Utilization for Control Unit

Table 5.6 Device Utilization for Register File

Table 5.7 Device Utilization for MIPS Processor

Table 5.8 Comparison table for MIPS RISC Processor

List of Figures

Figure 2.1 The MIPS Processor

Figure 2.2 Program Counter

Figure 2.3 Arithmetic Logic Unit

Figure 2.4 Register File

Figure 2.5 Program Memory

Figure 2.6 Data Memory

Fig. 2.7 MIPS Instruction Types

Figure 3.1 a portion of the data path used for fetching instructions and incrementing the PC

Figure 3.2 The Data-Path of R-type Instruction

Figure 3.3 Sign-extension Unit

Figure 3.4 Data-path for Load or Store Instruction

Figure 3.5 Datapath for Conditional Instruction (beq)

Figure 3.6 The Simple Datapath for MIPS Architecture

Figure 3.7 The data path with all necessary multiplexers and all control lines indentified

Figure 5.1 Simulation Result for ALU unit

Figure 5.3 Simulation Waveform of Control Unit

Figure 5.4 Simulation Waveform of Register File

Figure 5.5 Simulation Waveform of MIPS RISC Processor

Figure 5.6 RTL View of ALU

Figure 5.7 Technological View of ALU

Figure 5.8 RTL View for Control Unit

Figure 5.9 Technology View for Control Unit

Figure 5.10 RTL View for Register File

Figure 5.11 Technology View for Register File

Figure 5.12 RTL View for MIPS Processor

Figure 5.13 Technology View for MIPS Processor

TABLE OF CONTENTS

Page no.

DECLARATION

CERTIFICATE

ABSTRACT

ACKNOWLEDGEMENT

LIST OF TABLES

LIST OF FIGURES

LIST OF SYMBOLS, ABBREVIATIONS AND NOMENCLATURE

CHAPTER 1

INTRODUCTION

Literature Survey and Problem Statement

Motivation

Objectives

Organization of the thesis

CHAPTER 2

AN OVERVIEW OF THE MIPS PROCESSOR

Lady using a tablet
Lady using a tablet

Comprehensive

Writing Services

Lady Using Tablet

Plagiarism-free
Always on Time

Marked to Standard

Order Now

2.1 Introduction

2.2 The MIPS processor

2.3 major components of the data-path design

2.3.1 Register

2.3.2 ALU

2.3.3 Register File

2.3.4 Program Memory

2.3.5 Data Memory

2.4 MIPS Instruction Set Architecture

2.4.1 Arithmetic-logical Instruction (R-type)

2.4.2 Memory Reference Instructions such as Load and Store (I-type)

2.4.3 Jump Instruction (J-type)

CHAPTER 3

IMPLEMENTATION OF THE DATA-PATH DESIGN

3.1 Introduction

3.2 Data-Path for R-Type Instructions

3.3 Data-Path for Memory Reference Instruction

3.4 Data-path for Conditional Instruction

3.5 The Simple (Combine Data-path) Data-path for MIPS Architecture

CHAPTER 4

IMPLEMENTATION OF THE CONTROL UNIT

4.1 Introduction

4.2 The ALU Control Unit

4.3 Designing the Main Control Unit

CHAPTER 5

RESULTS AND RESULTS

5.1 Simulation Results

5.1.1 Simulation Results for Arithmetic Logic Unit

5.1.2 Simulation Results for Control Unit

5.1.3 Simulation Results for Register File

5.1.4 Simulation Results for MIPS RISC Processor

5.2 Synthesis Results

5.2.1 Synthesis Results for Arithmetic Logic Unit

5.2.1.1 RTL View for Arithmetic Logic Unit

5.2.1.2 Technology View for Arithmetic Logic Unit

5.2.1.3 Device Utilization Summary for Arithmetic Logic Unit

5.2.2 Synthesis Results for Control Unit

5.2.2.1 RTL View for Control Unit

5.2.2.2 Technology View for Control Unit

5.2.2.3 Device Utilization Summary for Control Unit

5.2.3 Synthesis Results for Register File

5.2.3.1 RTL View for Register File

5.2.3.2 Technology View for Register File

5.2.3.3 Device Utilization Summary for Register File

5.2.4 Synthesis Results for MIPS RISC Processor

5.2.4.1 RTL View for MIPS RISC Processor

5.2.4.2 Technology View for MIPS RISC Processor

5.2.4.3 Device Utilization Summary for MIPS RISC Processor

5.3 Timing Summary

5.4 Comparison

5.5 Conclusion

5.6 Future Work

REFERENCES

APPENDIX 1

Programming Code

CHAPTER 1

INTRODUCTION

The Microprocessor without interlocked pipeline stages (MIPS) instruction set architecture (ISA) is a Reduced Instruction Set Computer (RICS) based microprocessor architecture that was developed by MIPS computer systems Inc. in the 1980s. MIPS is now an industry standard and performance leader within the embedded industry. This design can be find in canon digital camera, Windows CE devices, CISCO routers, Sony play station 2 game consoles and many more products used in our everyday lives. Microprocessor without interlocked pipeline stages RISC microprocessor architecture characteristics include: fix-length straightforward decode instruction format, memory accesses limited to load and store instructions, hardwired control unit, a large general purpose register file and all operations are done within the register of the microprocessor.

In this thesis we have described all the major components (Register File, Arithmetic Logic Unit, Control unit, Memory) of the processor and define the individual datapath of the MIPS instruction set. After this we have merged all type of Datapath of the instructions and control unit and we have designed a final architecture of the Microprocessor without Interlocked Pipeline Stages (MIPS) RISC processor.

This complete architecture and its components are simulated and verified using XILINX 13.2. After successful completion of simulation phase, I have done synthesize the code to achieve optimum results such as timing and power.

Literature survey and Problem statement

I have studied too many research papers on this topic before I have started my thesis, which are given below:

Victor P. Rubio[2] presented the Implementation Design of a MIPS RISC Processor using VHDL. In this paper author implement the single cycle and pipelined MIPS processor using ALTERA UP2 development board and shows the simulation waveform of the complete architecture.

Anders Wallander[3] presented the Implementation of a MIPS processor. In this paper they simply implemented a microprocessor using VHDL and field programmable gate array and show only the code of the different module of the data path design

Mamun Bin Ibne Reaz, Md. Shaibul Islam and Mohd. S. Sulaiman [4] presented the single clock cycle MIPS RISC processor design using VHDL. In this paper they describe the design methodology of a single clock cycle MIPS RISC processor using VHDL to ease the description, simulation, verification and hardware realization. This paper shows the simulation waveform of the all module (instruction fetch, instruction decode, execution, data memory and write back) of datapath design, control unit and top-level module.

Kirat pal Singh and Shivani Parmar [5] presented the VHDL Implementation of a MIPS-32 Pipeline Processor. In this paper the simulation results shows that maximum frequency of pipeline processor is increased from 100MHz to 200MHz.

Lady using a tablet
Lady using a tablet

This Essay is

a Student's Work

Lady Using Tablet

This essay has been submitted by a student. This is not an example of the work written by our professional essay writers.

Examples of our work

Anjana R and Kurnal Gandhi [6] presented the VHDL Implementation of a MIPS RISC Processor. In this paper the implementation is done using XILINX 13.2 RTL schematic and synthesized using modelsim, all the modules were designed and tested separately. Once each module is functionally verified they are combined together and tested again.the results shows overall power is reduced by 6%.

After an exhaustive study of the MIPS RISC processor architectures proposed in the literature so far a new MIPS 32-bit RISC processor with efficient area has been proposed.

The objectives of the thesis are:

To develop a single clock cycle per instruction Processor;

To Develop all the major components of the data path;

To Develop the control unit

Finally to integrate all the modules of the data path and control unit;

Organization of the thesis

The complete thesis has divided into five chapters.

In chapter one we have introduced the Microprocessor without interlocked pipeline stages RISC processor. Study of previous implementations on microprocessor without interlocked pipeline stages RISC processor has been compiled in literature survey.

In chapter two we have introduced the major component of the datapath and the MIPS Instruction Set Architecture has been described.

In chapter three we have defined the datapath design for arithmetic-logical instruction (Register-type), memory reference instructions (Immediate-type) and branch instructions and after that the final datapath for all three types of instructions.

In chapter four we have discussed the control unit of the processor.

In chapter five we have got the final result of simulation and synthesis of datapath components, control unit and top module of the microprocessor without interlocked pipeline stages RISC processor.

CHAPTER 2

AN OVERVIEW OF THE MIPS PROCESSOR

2.1 Introduction

In this thesis we have designed an architecture [1] that includes a subset of the core MIPS instruction set: the memory reference instructions, the arithmetic logical instructions and branch instructions. We have defined all the instructions in detail in the section 2.4. For the execution of every instruction, the first two steps are common:

1) Previously we have sent the program counter (PC) to the memory that contains the code and fetch the instruction from that memory.

2) Read one or two registers, using fields of instruction to select the registers to read. For the load word instruction we need to read only one register but most other instructions require that we read two registers.

After these two steps, the arithmetic-logic instruction uses the ALU for the operation execution, the memory reference uses the ALU for address calculation and branch instruction uses the ALU for comparison of the two register values.

After using the ALU, the memory reference instructions have needed to access the memory either to write the data or read the data. For an arithmetic logical instruction the result of the ALU back into a register file. In the end for branch instruction, we may need to change the next instruction address based on the comparison.

The MIPS processor

The Processor has been divided in two parts:

Datapath

Control Unit

We have shown these in figure 2.1

DATA-PATH

CONTROL UNIT

CONTROL SIGNAL

STATUS SIGNAL

Figure 2.1 The MIPS Processor

The signal which goes from control unit to data path has considered as control signal and the signal which goes from data path to control unit has considered as status signal. The datapath of the MIPS processor has separated into five stages:

Instruction fetch

Instruction decode

Execution

Data memory

Write back

The control unit has controlled the operation performed by these stages.

Major Components of The Data-Path

The Major components of the data-path includes:

Program counter

2. Arithmetic Logic Unit

3. Register file

Program memory

Data memory

Program Counter

The program counter (also called the instruction pointer or part of the instruction

sequencer in some computer architectures) is a register, which indicates where the instruction sequence are present in the processor . Program counter holds the address of the instruction being executed, or the address of the next instruction to be executed. For each instruction cycle the increment has done in the program counter automatically, so that instructions have normally retrieved sequentially from memory. Certain instructions, such as branches and jumps, interrupt the sequence by placing a new value in the program counter.

PC

CLOCK

I/P

32

O/P

32

Figure2.2 Program Counter

Arithmetic Logic Unit

The arithmetic logic unit has seven ports; these have described as two 32-bits input

Ports, one 32-bit output port, arithmetic logic unit control and also the three flag bits zero flag, carry flag and overflow flag.

Arithmetic Logic Unit has 3 control inputs.

ALU Control input Function

000 AND

001 OR

010 add

110 subtract

111 set-on-less-than

Depending on the instruction class, arithmetic logic unit will need to perform one of these above said five functions.

For memory reference instructions, arithmetic logic unit has been used to compute memory address by addition.

For arithmetic-logical instructions, arithmetic logic unit has been used to perform one of five actions (AND, OR, add, subtract, set-less-than), depending on the value of 6-bit function field in low order bits of instructions.

For branch instructions, arithmetic logic unit has been used to perform subtraction.

ALU

A

B

OPERATION

A=B

32

32

RESULT

32

Figure 2.3 Arithmetic Logic Unit

2.3.3 Register File

The register file [1] contains all the registers and has two reading port and one writing

port this is shown in Fig.1.6. The register file has a reg-write signal to control writing data on one of its four register. In contrast, a register write has been explicitly indicated by asserting the write control signal. Writes are edge triggered, so that all the write inputs (i.e. the value to be written, the register number, and the write control signal) must be valid at the clock edge. Since writes to the register file are edge triggered, our design can legally read and write the same register within a clock cycle: the read will get the value written in an earlier clock cycle, while the value written will be available to a read in a subsequent clock cycle. The inputs carrying the register number to the register file are all 5bits wide, whereas the lines carrying data values are 32 bits wide.

Read

register 1

Read

Read data 1

register 2

Register File

Write Read

Register data 2

Write

data

Register

Number

Data

Data

Regwrite

5

5

5

Figure 2.4 Register File

Program Memory

Instruction memory is the state elements. Instruction memory has been used only

provide read access because the datapath does not write instructions. So the instruction memory has been treated like a combinational logic: the output at any time reflects the content of the location specified by the address input, and no read control signal is needed. (We will need to write the instruction memory when we load the program; this is not hard to add, and we ignore it for simplicity). Since the instruction memory unit can only be read, we do not include a read control signal; this simplifies the design.

Instruction

Address

Instructions

Instruction

Memory

Figure 2.5 Program Memory

Data Memory

Data memory unit [4] has only accessed by memory reference instruction. Data

memory has taken two inputs for the address and the write data, and one output for the read. Two separate read and write controls either MemWrite or MemRead asserted on any given clock.

Memory Read

To load an instruction the read memory control MemRead has asserted to enable the data to be read from the data memory. The data memory has taken an address from one of the inputs. Then the data has sent from the data memory to register file through its output read data.

Memory Write

To store an instruction the write memory control MemWrite has asserted to enable the data to be written into the data memory. The data memory has taken an address from one of the inputs. The data to be written into the data memory has been sent into it through the input write data.

Address

Read

data

Write Data

data Memory

MemWrite

MemRead

Figure 2.6 Data Memory

The MIPS Instruction Set Architecture (ISA)

As mentioned before MIPS is a RISC microprocessor architecture, the MIPS architecture has 32-bit general purpose register. MIPS processor have three types of instructions: memory reference instruction is used for the load and store instructions, arithmetic-logical instruction are used for add, subtract, AND, OR, and set-less-than instructions branch instruction is used for branch instruction as shown in Fig.2.9. Table 2.1 provides a description of each of the fields used in the three different instruction types.

MIPS is a memory reference architecture, So main memory can only be accessed by the memory reference instructions (e.g. lw, sw). A load instruction loads a value from memory into a register. A store instructions store a value form register to memory. The load and store instructions use the sum of the offset value in the address/immediate field and the base register in the $rs field to address the memory. Table 2.2 shows a summary of the core MIPS instructions.

The Arithmetic-Logical Instruction

A detailed description about arithmetic-logical instruction has been discussed in Fig.2.9. The arithmetic-logical instruction consists of six instruction fields:

Opcode field- Opcode means "Operation code". The Opcod is always contained in bits 31-26. Opcode is common to all type of instruction and defines the operation to be taken by the processor when executing the instruction.

rs field- rs is the first source register. The source register is the register that holds one of the arguments of the operation.

rt field- rt is the second source register.

rd field- rt is the destination register, where the result of the operation will be stored.

shamt field- it holds the number of bits to perform in case of shift operation

funct field- function field is used to specify the operation.

Memory reference instructions such as load and store

A detailed description about memory reference instruction has been discussed in Figure 2.7. The memory reference instructions are basically of two types load instruction and store instruction. The function of the Opcode field will be similar for both instructions. But the register operands will be changed for both instructions, which have defined in below:

In case of load instruction, rt field specifies the destination register and rs field specifies the source register, which will be find out the memory base address by adding the 16-bit address field to the content of the base register (rs).

In case of store instruction, rt field specifies the source register and rs field specifies the destination register.

Branch Instruction

A detailed description about branch instructions has been discussed in Fig. 2.9.

The branch equal instruction has three operands, two register and one 16-bit address field.

Two registers rs and rt are source register that are compared for equality.

A 16-bit address field is sign-extended, shifted and added to program counter to compute the branch target address.

Table 2.1 MIPS Instruction Fields

CHAPTER 3

IMPLENTATION OF THE DATA-PATH DESIGN

In this chapter we will discuss the implementation of the data-path design for three types of ISA (R-Type, I-Type, J-Type). First we will discuss the datapath of the R-type instruction, I-type instruction and J-type instruction individually and after that we will merge the data path of all three type of instructions.

3.1 Introduction

All instructions start by using the PC to supply the instruction address to the instruction memory. After the instruction is fetched, the register operands used by an instruction are specified by fields of that instruction. Once the register have been fetched, they can be operated on to computer a memory address (for load or store), to compute an arithmetic result (for an integer arithmetic-logical instruction) or a compare (for a branch). If the result is an arithmetic-logical instruction, the result form the ALU must be written to a register. If the operation is a load or store, the ALU result is used as an address to either store a value form the register or load a value from memory into the registers. The result from the ALU or memory is written back into the register file.

3.2 Data path for R-type instructions

PC supplies the address of the instruction to be executed. Now we will take the content of the PC that decide where in the memory instruction is located so we get the instruction from the memory, technically this process is called fetching the instruction. So to execute any instruction, we must start by fetching the instruction from memory. To prepare for executing the next instruction, we must also increment the program counter so that it points at the next instruction, 4 bytes later. The data path for this step is shown is shown in Fig. 3.1.

PC

Read

Address

Instructions

INSTRUCTION

MEMORY

ADD

4

Figure 3.1 A Part of the data path used for fetching instructions and incrementing

the PC

Now we will use the register file component. In the R-format instructions have three register operands, we will need to read two data words from the register file and write the one data word into the register file. For each data word to be read from registers, we need an input to the register file that specifies the register number to be read and an output from the register file that will carry the value that has been read from the registers. To write a data word, we will need two inputs: one to specify the register number to be written and one to supply the data to be written into the register. The register file always output the contents of whatever registers number are on the read register inputs. Writes, however, are controlled by the write control signal, which must be asserted for a write to occur at the clock edge. Thus we need a total of four inputs (three for register numbers and for data) and two output (both for data). The register number inputs are 5 bits wide to specify one of 32 registers (32=2), whereas the data output buses are each 32 bits wide. Now finally the output of the register file is given to the ALU and this ALU perform any operation through the control signal. The result which is produced by ALU would be sent to register file for storage. The data path of this instruction format is shown in Fig. 3.2.

Figure 3.2 The Data-Path of R-type Instruction

3.3 Data-path for Memory Reference Instruction such as load or store

In this section we have discussed the data-path of two types of instructions first one is the load and second one is the store instruction for ex. Lw $t0, offset_value($sp) or sw $a0, offset_value($sp). These instructions compute a memory address by adding the base register, which is $sp, to the 16-bit sign offset field contained in the instructions. If the instruction is a store, the value to be stored must also be read from the register file where it resides in $t0. If the instruction is a load, the value read form memory must be written be written into the register file in the specified register, which is $a0. Thus we will need both the register file and the ALU.

In addition, we need a unit to sign-extend the 16 bit offset field in the instruction to a 32 bit-signed value, and a data memory unit to read from or write to. The data memory must be written on store instructions; hence it has both read and writes control signals, an address input as well as an input for the data to be written into memory. Fig 2.8 and 3.3 shows these two elements. Fig. 3.4 shows how to combine these elements to build the data path for a load word or store word instruction, assuming that the instruction has already been fetched. The register number inputs for the register file come from fields of instructions, as does the offset value, which after sign extension becomes the second ALU input.

Sign

extend

16

32

Figure 3.3 Sign-extension Unit

Read

register 1

read

Read data 1

register 2

Write read

register data 2

Write

data

Address read

Data

Data

memory

Write

data

zero

ALU

ALU

result

Sign

Ex.

16

32

ALU Operation

Mem. Write

Mem. read

3

Ins.

Reg.write

Figure 3.4 Data-path for Load or Store Instruction

3.4 Data-path for conditional Instruction

The branch datapath do two operations [a]: compute the branch target address and compare the register contents, Fig. 3.5 shows the branch datapath. To compute the branch target address, the branch datapath includes a sign extension unit and an adder. To perform the compare we use the register file to supply the two register operand. The comparison can be done using the ALU. Since that ALU provides output signal that indicates whether the result was 0, we can send the two register operand to the ALU with the control set to do a subtract. If the zero signals out of the ALU unit is asserted, we know that the two values are equal. Although the zero output always signals if the result is zero, we will be using it only to implement the equal test of branches.

Sum

Add

Zero

ALU

Shift

Left 2

Read

Register 1

read

Read data 1

Register 2

Registers

Write read

Register data 2

Write

data

Sign

extend

PC+4 from instruction datapath

Branch target

To branch

Control logic

ALU Operation

3

16

32

Ins.

Figure 3.5 Datapath for Conditional Instruction (beq)

3.5 The Simple Datapath for MIPS Architecture

Now we can combine all three type of datapath to make a simple datapath for the MIPS architecture.

PC

Read

Address

Instruction

Instruction

Memory

Read

Register 1 read

data 1

Read

Register 2

Write read

Register data 2

Write Registers

data

Address read

Data

Data

Memory

Write

data

Zero

ALU

ALU

Result

M

U

X

M

U

X

Sign

extend

Add

Shift

Left 2

Add

ALU

RESULT

M

U

X

ALUSrcc

PCSrc

Reg,write

Mem.write

MemtoReg.

ALU Operation

MemRead

Figure 3.6 The Simple Datapath for MIPS Architecture

CHAPTER 4

IMPLEMENTATION OF THE CONTROL UNIT

In this chapter we have discussed the implementation of the control unit, which generates the control signals and those signals control the operation of the datapath design.

4.1 Introduction

The control unit must be able to take input and generate a write signals for each state element, the selector control for each multiplexor, and the ALU control. The ALU control is different in a number of ways, and it will be useful to design it first we design the rest of the control signal.

4.2 The ALU Control

Depending upon the instruction class, the ALU will need to perform one of these five functions. For load/store word instructions, ALU is used to find out the memory address by addition. For R-type instruction, ALU is used to perform one of the five actions (AND, OR, Subtract, add, or slt). For branch it must perform a subtraction.

We can generate the 3-bit ALU control input using a small control unit that has as inputs the function field of the instruction and a two bit control field, which we call ALUOp. In table 4.1, we show how to set the ALU control inputs based on the 2-bit ALUOp control and 6-bit function code. In this table opcode listed in the first column, determines the setting of the ALUOp bits. All the encodings are shown in binary. Notice that when the ALUOp code is 00 or 01, the output fields do not depend on the function code field; in this case, we say that we "don't care" about the value of the function code, and the function field is shown as XXXXXX, when the ALUOp value is 10, then the function code is used to set the ALU control input.

Table 4.1 How the ALU control bits are set depends on the ALUOp control bits and the

different function codes for the R-type instruction

4.3 Designing the Main Control Unit

We know that for a load instruction the bit position of the destination register is 20-16 (rt), while for an R-type instruction its bit position is 15-11 (rd). Thus we will need to add a multiplexer to select which field of the instruction is used to indicate the register number to be written. Using this information, we can add the instruction labels and extra multiplexor to the simple datapath. Fig. 4.1 shows these additions plus the ALU control block, the write signals for state elements, the read signals for the data memory, and the control signals for the multiplexors. Since all the multiplexors have two inputs, they each require a single control line. Fig. 4.1 shows seven single-it control lines plus the 2-bit ALUOp control signal and the table 4.2 describes the function of these seven control lines.

Table 4.2 The Effect of the Seven Control Signal

In the above table, when the 1-bit control to a two-way multiplexor is asserted, the multiplexor selects the input in corresponding to 1. Otherwise if the control is deasserted, the multiplexor selects the 0 input.

In table 4.3 we define how the controls signals should be set for each opcode,

Table 4.3 the setting of control lines is completely determined by the opcode fields of

Instruction.

The first row of table corresponds to the R-format instructions. For R-type instructions, the rs and rt are the source registers and rd is the destination register; this defines how the signals ALUSrc and RegDst are set. Furthermore when Regwrite=1, then R-type instruction writes a register, but neither reads nor writes data memory. When the branch control signal is 0, the PC is unconditionally replaced with PC+4; otherwise, the PC is replaced by the branch target if the zero output of the ALU is also high. The ALUOp field for R-type instructions is set to10 to indicate that the ALU control should be generated from function field. The second and third rows of this table give the control signal settings for lw and sw. these ALUSrc and ALUOp fields are set to perform the address calculation. The MemRead and MemWrite are set to perform the memory access. Finally, RegDst and Regwrite are set for a load to cause the result to be stored into the rt register. The branch instruction is similar to an R-format operation, since it sends the rs and rt registers to the ALU. The ALUOp field for branch is set for a subtract (ALU control=01) , which is used to test for equality. Notice that the MemtoReg field is irrelevant when the Regwrite signal is 0-since the register is not being written, the value of the data on the register data write port is not used. Thus, the entire MemtoReg in the last two rows of the table is replaced with X for don't care. Don't cares can also be added to RegDst when Regwrite is 0.

CHAPTER 5

RESULTS AND CONCLUSION

5.1 Simulation Results

5.1.1 Simulation Results for ALU Unit

The simulation waveform of the ALU Unit has shown in figure. This unit has two inputs a_input [7:0] and b_input [7:0] along with the clock and an alu_control signal.

In the first stage we give the 00001101 to a_input and 00110100 to b_input and the value of alu_control is 110 that time ALU will perform the arithmetic operation (a_input - b_input) and the result will be 11011001.

After that we give the 00000111 to a_input and 00000001 to b_input and the value of alu_control is 000 that ALU will perform the logical operation (a_input AND

b_input) and the result will be 00000001.

Further description of the ALU unit has been defined through the table 5.1. in this table we define the values of the inputs, value of the alu_control , ALU operation and the results of the ALU operation.

Tale 5.1 ALU Unit Operation

Fig. 5.1 Simulation Waveform of ALU Unit

5.1.2 Simulation Results of Control Unit

The simulation waveform of Control Unit is shown in shown in figure. This unit has one input opcode [5:0] along with the clock. When opcode is 000000 that time the R_format will be 1 and the control input for R_type are describe in below table 5.2

Table 5.2 Control Input for R-type

When opcode is 100011 that time load word is 1and the other control input values are given in the below table 5.3.

Table 5.3 Control Input for Load

C:\Users\Shubhangi\Pictures\project picture\SIMUCON.JPG

Figure 5.3 Simulation Waveform of Control Unit

5.1.3 Simulation Results for Register File

The simulation waveform of register file is shown in figure. Register file has two reading port and one writing port which are labeled as read data 1, read data 2and write data and the addresses of these data's are define by the three input register which are labeled as read register1 ,read register 2 and write register. In this simulation the address of read register 1 and read register 2are 00010 and 00001 respectively and the data of read data1 and read data2 are 00000110 and 00110011respectvily. This simulation has been taken three types of control signals i.e. Reg.Write, Reg.Dst and MemtoReg. The values of these signals are Reg.Write is 1, Reg.Dst is 0 and MemtoReg. is 1. These values indicates that the lw instruction will be come, load instruction compute the memory address by adding the base register and 16-bit signed offset. This base register value is the 00000110 (read data 1) and the 16 bit signed offset value is 00000001 so the alu_result will be 00000111. This is shown in simulation waveform

Figure 5.4 Simulation Waveform of Register File

Simulation Results for MIPS RISC Processor

In single cycle MIPS, only one (single) instruction execution cycle is active at any time. That cycle may take multiple clocks. The simulation waveform of the MIPS Processor has been shows that all instructions (like subtract, AND and OR) are executed in a single clock cycle.

Figure 5.5 Simulation Waveform of MIPS RISC Processor

Synthesis Results

The VHDL code for the MIPS RISC Processor has been synthesized in precision synthesis using XILINX Sparten 3 xcs400pq208 as a target device. The synthesis results along with RTL and Technological view of all major component and main processor is shown below.

5.2.1 Synthesis Results for Arithmetic Logic Unit

5.2.1.1 RTL View of Arithmetic Logic Unit

Figure 5.6 RTL View of ALU

5.2.1.2 Technological View of ALU

Figure 5.7 Technological View of ALU

5.2.1.3 Device Utilization Summary for ALU

The device utilization summary tells us the number of resources which are used to generate the proposed architecture. The table tells about the area which is covered by the input output blocks, LUT'S, CLS Slices and many more

Device Utilization for 3s400pq208

Resource Used Avail Utilization

Number of Slices 7 3584 0%

Number of Slices Flip-Flops 0 7168 0%

Numbers of 4-Input LUT'S 12 7168 0%

Number of bonded IOB'S 17 141 12%

Number of GCLK'S 0 8 0%

Table 5.4 Device Utilization for ALU

5.2.2 Synthesis Result for Control Unit

5.2.2.1 RTL View for Control Unit

Figure 5.8 RTL View for Control Unit

5.2.2.2 Technology View for Control Unit

Figure 5.9 Technology View for Control Unit

5.2.2.3 Device Utilization Summary for Control Unit

Device Utilization for 3s400pq208

Resource Used Avail Utilization

Number of Slices 7 3584 0%

Number of Slices Flip-Flops 0 7168 0%

Numbers of 4-Input LUT'S 12 7168 0%

Number of bonded IOB'S 17 141 12%

Number of GCLK'S 0 8 0%

Table 5.5 Device Utilization for Control Unit

5.2.3 Synthesis Result for Register File

5.2.3.1 RTL View for Control Unit

Figure 5.10 RTL View for Register File

5.2.3.2 Technology View for Register File

Figure 5.11 Technology View for Register File

5.2.3.3 Device Utilization Summary for Register File

Device Utilization for 3s400pq208

Resource Used Avail Utilization

Number of Slices 7 3584 0%

Number of Slices Flip-Flops 0 7168 0%

Numbers of 4-Input LUT'S 12 7168 0%

Number of bonded IOB'S 17 141 12%

Number of GCLK'S 0 8 0%

Table 5.6 Device Utilization for Register File

Synthesis Result for MIPS Processor

RTL View for MIPS Processor

C:\Users\Shubhangi\Pictures\project picture\rtlmips.JPG

Figure 5.12 RTL View for MIPS Processor

Technology View for MIPS Processor

Figure 5.13 Technology View for MIPS Processor

Device Utilization Summary for MIPS Processor

Device Utilization for 3s400pq208

Resource Used Avail Utilization

Number of Slices 274 3584 7%

Number of Slices Flip-Flops 248 7168 3%

Numbers of 4-Input LUT'S 308 7168 4%

Number of bonded IOB'S 81 141 57%

Number of GCLK'S 1 8 12%

Table 5.7 Device Utilization for MIPS Processor

5.3 Timing Summary

Speed grade: -4

Minimum input arrival time before clock: 9.38ns

Maximum output time after clock: 10.318ns

Maximum combination path delay: 11.951ns.

5.4 Comparison

After the synthesization of the design, the next step is the comparison of this design with its older counterpart.

Selected Device

Selected Device xcs400pq208-4

No. of slices

4283 out of 19200

22%

274 out of 3584

7%

No. of IOB'S

388 OUT OF 360

107%

81 out of 141

57%

No. of LUT'S

275 out of 27553

0%

308 out of 7168

4%

Table 5.8 Comparison table for MIPS RISC Processor

5.5 Conclusion

a Single Clock Cycle MIPS RISC Processor design by using

VHDL. The major components of the processor have been coded in VHDL and the complete processor has also been coded in VHDL. Here we use the simulation XILINX ISE Design suit 13.2, to see the outputs in the form of waveform. For synthesis i.e. to generate the hardware of all major components and the complete processor, ISE design suit 13.2 has used.

5.6 Future Work

Future work is to implement the pipeline processor using clock gating technique. Clock gating technique mainly reduces the dynamic power consumption of the processor.