Semantic Models For And Formal Syntax Definitions Computer Science Essay

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Besides a formal syntax definition, a few formal semantic models for HDLs are ever constructed. Thus, this final year project reports the author efforts to construct the digital delay locked loop in hardware description languages Verilog. A high speed synchronous integrated circuit (IC's), for example memory interface, microprocessors and etc, required aligned clock signal so that it can be work properly. This is because a properly aligned clock signal able to cancel the clock skews across all process, voltage and temperature (PVT) variation. The delay-locked loop (DLL) is such a circuit, using a first order closed-loop architecture that dynamically aligns its output clock signal with a reference clock signal. Therefore, phase locked loops have been used for a wide range applications. But there are still a lot of jilters and noise appears in the system therefore, DLL have emerged as a viable alternative to the traditional oscillator-based phase locked loops.

Basically, there are two types of DLL architectures that are currently developing: analog and digital. However the first order loop delay locked loop, is much easier to encounter the problem but analog delay locked loop is very hard to maintain the wide-range operation and low-jilter performance. Thus, a digital delay line are used for digital elements for making the design much simpler and the size is much small for portable but with much higher quantized step in delay time.

Therefore, this report is show how to maintain the wide-range operation and low-jilter performance. This DLL is designed and simulated using Quartus 2 version 8.1 web editions. The lock range is . Suggestions are made for improvement of the jitter performance.

Table contents

ABSTRACT

LIST OF FIGURES

LIST OF TABLE

LIST OF ABBREVIATIONS

ACKNOWLEDGEMENT

INTRODUCTION

Motivation

Technical objectives

Project objectives

Key Challenges

Background of the Research Area

Application of Phase Detector

Application of Delay Chain

Application of Delay Locked Loop (DLL)

Overview of the system in The Project

(1.6.1) Digital Delay Locked Loop Block

(1.6.2) Theory for the Delay Locked Loop functionality

(1.6.3) The different between DLL and PLL

(1.6.4) The practical of Digital Delay Locked Loop

Chapter Organization

LITERATURE REVIEW

METHODOLOGY

Investigation of Methods Proposed by Previous Research

Proposed Algorithm

(3.2.1) Flowchart: Algorithm

PROJECT TESTING : RESULTS AND DISCUSSION

Phase Detector and counter

Delay chain

Combination of whole system

Summary and Discussion

Comparison of Results with Previous Research

CONCLUSION

Recommendations for further work

REFERENCES

APPENDIX

ACKNOWLEGMENT

I would like to take this golden opportunity to thank Mr Bryan Chong Fook Lim (Project supervisor) for his guidance and valuable advice during the implementation of this project. Besides that, thanks for giving me this opportunity and supporting the momentum of the project research and for opening the research into Delay Locked Loop. Thanks to other lecturer who had helped me throughout the implementation.

Besides, I appreciate the support and help given my friends and classmates. They have shared some software information with me.

Last but not least, I would like to take this opportunity to thanks my family members who provide me moral support throughout the progression of the project.

INTRODUCTION

(1.1)Motivation:-

Phase locked loops ( PLL's) and delay locked loop (DLL's) are one of the most important routines that behave in microprocessor and memory interfaces and communication IC's in order to cancel the on-chip lock amplification and yet buffering delay. Thus it also helps to improve the efficiency of I/O timing margins. But by increasing the clock efficiency and integration levels of a digital circuit it will also produce hostile operating environment for these phase alignments circuit. [1] From this operation it will create some side effect from the switching of the digital circuit will affect the PLL or DLL operation. Meanwhile for high performance of the microprocessor and memory IC's, normally PLL or DLL will be used as minimize the effect by the skews and jilters of clock signals. [2]

Therefore, DLL had been introduces into the market of microprocessor and memory IC's industries. But after some research had made, it found out that conventional DLL's had many disadvantages such as limited phase capture range as DLL only required to adjust the phase while not frequency. Besides from this, conventional DLL's also found a difficulty to design to work over process, voltage and temperature (PVT) variation. This is because DLL's is only work to capture the phase while not frequency. So from this all disadvantages of the conventional DLL's, this author would like to propose a new DLL architectural which required a better frequency range while keeping the low-jitter performance.

In this report, the author would like to begin with the brief overview of conventional DLL design overall it mentions some of the disadvantages of conventional DLL's approaches. Section 2, it will present by the new approach of DLL architectural. Section 3 will discuss more on the circuit design issues that arose in the research. And lastly section 4 will discuss about the experimental result and concluding the remarks follow in section 5.

(1.2)Technical Objective

No

Technical Objectives

Status and Explanation

( to be done at conclusion of FYP report )

1

Able to generate a counter based on the requirement

2

Able to phase shift accordingly based on the reference frequency

3

Able to build a delay chain

4

To investigate the delay locked loop

5

To be able a delay circuit for shifting the phase of the reference signal according to the integral phase error

6

To locked particular delay on the system

7

To decide on a suitable method programming for the device

8

To write a suitable programming code for the delay locked loop

Table 1-1:- Technical objective

(1.3) Project objective

In working towards the goal of improving and designing an algorithm for delay locked loop, several deliverables have been identified in table 1-2 below:-

No

Project objective

1

To apply delay locked loop methods from the previous researchers and develop methods of delay locked loop upon applying digital delay locked loop

2

To apply statistical algorithm of the delay to the digital delay locked loop for obtaining possible delay patterns.

3

To develop a framework for statistical data collection and performance benchmarking of an algorithm for digital delay locked loop

4

To develop a digital delay locked loop that able to lock the phase and able to give a appropriate delay for the data-clock.

(1.4) Key Challenges

1) Able to design a digital delay locked loop with a wide range frequency.

2) The final design of the system should be low power consumption.

3) Wider range for the delay steps.

4) Smaller area

(1.5) Background of the Research Area

(1.5.1) Application of Phase Detector

Several application of Phase Detector's are:-

Phase detector is widely use in the technology world. For example it is an essential element of the Phase-Locked loop (PLL). It will operated as frequency mixer, analog multiplier or logic circuit that able to generate a voltage signal which is also representing the difference in phase between two incoming signal. [http://en.wikipedia.org/wiki/Phase_detector]

Besides from that, phase detector also plays a very important role for communication and radar application because phase detector able to detect the differential phase error between VCO and corrects the VCO to be in phase with the crystal oscillator. [http://www.family-science.net/ITTTech/Downloads/TestingaPhaseDetector.pdf ]

Phase Detector

Ref_CLK

Data_CLK

UP

Down

Incoming signal

Phase different

Figure 1-1:- Application of Phase Detector

(1.5.2) Application of Delay Chain

Several applications of Delay Chain's are:-

Delay chain can be applied is several application such as a digitally-controlled oscillator (DCO), all-digital phase-locked loops (ADPLL), all-digital delay-locked loops (ADDLL), all-digital multi-phase clock generator (ADMCG) and digital phase-locked loops. As long as devices need an external delay to delay respectively into the system. Besides that, delay chain also use in many wafers include a delay chain as part of the scribe line test structures. Delay chains are used during wafer testing to measure the effects of manufacturing process variations. ["Ring oscillators for CMOS process tuning and variability control" by BHUSHAN Manjul; GATTIKER Anne; KETCHEN Mark B.; DAS Koushik K ]

Figure 1-2:- one of the application that use by delay chain [http://www.ovation.co.uk/DelayLine/DelayLine-Applications.html]

(1.5.3) Application of digital delay locked loop

Several applications of DLL's are:-

Delay clocked loop able to use in DDR SDRAM controller applications. [http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=4027531 ]. The SDRAM is interface between the system and the external hardware. Therefore the interface is makes higher transfers rates possible by more strict control of the timing of the electrical data and clock signal. If DLL's are used, all different data rate of electrical data and the clock signal can be able to align without any glitches and problem.

Nowadays, the speed of operating speed is tremendous increase. So in order for the semiconductor memory devices to work, the semiconductor industries required to have fast input and output speed of data processing unit. Thus, the operating speed of the data processing unit is getting faster and faster in the engineering development process of the semiconductor integrated circuits. [http://www.freepatentsonline.com/y2010/0054060.html] but, the semiconductor memory industries cannot able to deliver the data to data processing unit is not in compliance with the input output speed of the data processing unit. Therefore, DLL's is used to overcome this problem that arose in the semiconductor memory industries as it able work appropriately based on operation modes.

Memory

Controller

Memory

Device

DLL

Control Clock

Output synchronized to control clock

Figure 1-3: one of the applications that used DLL

(1.6) Overview of the system in the project

(1.6.1) Digital Delay Locked Loop Block

Basically the idea that proposed by this author is Digital Delay Locked Loop. It consist of Phase Detector, 4 bit counter (Binary Counter), Demultiplexer, and a set of Delay chain. The reference clock for each DLL may come from the PLL outputs, clock or any of the two dedicated clock input pins within the same quadrant-edge as the DLL. The DLL routes the reference clock through a delay chain of sixteen identical delay cell but they will produce different delay with the respectively delay. The delayed clock is compared to the reference clock. The setting for DLL delay chains are from a 4-bit counter, which moves up and down to alter the delayed clock and the reference clock are aligned in the same phase.

Phase Detector

4 bit Counter

16 delay chain

Demultiplexer 4:16

Figure 1-4:- Digital Delay Locked Loop block suggested by the author

(1.6.2) Theory for the Delay Locked Loop functionality

Basically DLL have much of the similarity behind between (Delay Locked Loop) DLL and (Phase Locked Loop) PLL. This is because some of the component that use in PLL is also used in DLL such as phase detector and etc but there are also some different between DLL and PLL in term of functionality and component. For more drastic different that we can see from the component are PLL is using Voltage-Controlled Oscillator (VCO) while DLL is using voltage-controlled delay-line. Meanwhile there are also much different in term of DLL consist of first-response but PLL consist of more than one order response such as 2, 3, 4, 5 and etc. From the order of response the author can be justifies that DLL is much more stable compare to PLL because DLL doesn't consist of VCO. So there are no accumulations of phase error due to the supply noise. Thus from this, the author can be justifies that jilters transfer function for a DLL is almost equal to zero as the reference clock both generates and synchronizes the output clock. Basically there are no phases different from the input and output.

(1.6.3)The different between DLL and PLL

Apart from the components, DLL also attempt to eliminate the skew or known as phase different between the input clock and the output clock. In conjunction with the phase different the out clock will be added additional delay such as the phase of two clocks will be equal. Therefore, the different for the two clocks might be a slightly different or maybe it will be a minimum different for the phase. But the PLL circuit compares the phase of the input signal with the phase of a signal derived from its output oscillator and adjusts the frequency of its oscillator to keep the phases matched.[ http://en.wikipedia.org/wiki/Phase-locked_loop]

Figure 1-5: DLL Block Diagram

Figure 1-6: PLL Block Diagram [the source drawing is from http://www.xilinx.com/support/documentation/application_notes/xapp132.pdf]

(1.6.4)The practical of Digital Delay Locked Loop

Practical DLL consist of two different type of DLL such as digital and analog. Both type of design is also can be accomplished in the DLL design where there are pros and cons for their certain design. For example, if the implementation of a DLL by using the analog technology there will be more finer timing resolution comparing with the digital implementation. Thus by using analog technology, the space consumption for the component will be much smaller compare to the digital implementation.

But, digital implementation will have more benefits in the noise sensitivity, lower power consumption and jilters' performance. Yet, by using this technology it can be provide the ability to stop the clock, facilitation power management.

Disadvantages Analog design for DLL

More power required

Close control of power supply

Conversion from old technologies to new technologies

Disadvantages Digital design for DLL

Space consumption is much larger

Required more gates to implement the DLL

Largest skew due to quantization delay time

Comparison between the Analog DLL block diagrams with the digital DLL block diagram

Figure 1-7: Digital DLL Block diagram

Figure 1-8: Analog DLL block diagram [http://ieeexplore.ieee.org/xpl/freeabs_all.jsp?arnumber=826820]

Chapter Organization

Chapter (2.0) Literature Review:-

This section is basically describing the present information of previous work from the various sources on delay locked loop. Previous algorithms for delay locked loop are discussed.

Chapter (3.0) Methodology:

This section discusses the steps taken towards achieving the project objectives and the technical objectives. This is includes investigation of methods that proposed by the author and used by the previous researchers as well as the procedures carried out to collect the date on statistical parameter of various phase different and the appropriate delay to supply. The results of the data collection are discussed and analysis the data have been locked and provided an appropriate delay given.

Chapter (4.0): Project Testing: Results and discussion:

The results are presented for the performance benchmarking of the proposed algorithm. The probability of successful delay is discussed.

Chapter (5.0): Conclusion:

The final section concludes the project work and how well the project objectives have been achieved. This is also included are recommendations for further work in the project area.

(2.0) Literature Review:-

In 1997, Mark A.Horowitz released (in[10]) A Semidigital Dual Delay-Locked Loop. This journal is basically describing that dual delay-locked loop architecture manage to achieves much low jitter, unlimited (modulo 2 ) phase shift and yet manage to have a larger operating range. The research for this dual delay locked loop is experimental in 0.8μm CMOS technology and the operating range is from 80 kHz ~400MHz.

Figure 2-1:- Architecture for the dual delay locked loop

In year 2006, Chun-Ming Hsu, Charlotte Y.Lau, Michael H.Perrott (Microsystems technology Laboratories Massachusetts Institute of Technology Cambridge, MA USA ) [12] had research on the Delay locked loop. They successfully implement a Delay-Locked Loop using a Synthesizer-based Phase Shifter for 3.2 Gb/s chip-to-chip Communication. The researcher manage to provides fine-resolution and infinite-range delay and is less sensitive to process, temperature and voltage (PVT) variation than that of conventional techniques using a phase interpolator. Besides that, the researcher also manages to implement digital Sigma-Delta modulator architecture that allows a higher clock data rate with compact area and reasonable power dissipation. This Delay-locked loop is implement using 0.18μm technology.

Figure 2-2 :- Architecture for Delay Locked Loop with digital Sigma-Delta modulator

In year 2007, Kuo-Hsing Cheng, Member, IEEE and Yu_Lung Lo, Student Member ,IEEE[11] presented a fast-lock mixed-mode delay-locked loop (DLL) for wide range operation and multiphase outputs. The design that proposed by the researcher is using the mixed-mode time-to-digital-converter scheme for a frequency-range selector and a coarse tune circuit to reduce the lock time. Thus, multi-controlled delay cell for the voltage-controlled delay line is applied to provide the wide operating frequency range and low-jitter performance. Besides from that, charge pump design is also included in this research as charge pump is use a digital control scheme to achieve adaptive bandwidth. The research for this fact-lock wide-range Delay-locked loop using frequency-range selector multiphase clock generator is implement using 0.25μm and able to operate arrange 32-320MHz.

Figure 2-3:- Architecture for fast-lock mixed-mode delay-locked loop

In year 2001, Yeon-Jae Jung, Seung-Wook Lee , Daeyun Shum, Wonchan Kim , Changhyun Kim, member ,IEEE and Soo-In Cho proposed A Dual-Loop Delay-Locked Loop using Multiple Voltage-Controlled Delay Lines [13]. Basically the author use dual-loop delay-locked loop (DLL) able to encounter the problem of a limited delay range by using multiple voltage-controlled delay lines (VCDLs). This proposed architecture enables the DLL to emulate the infinite-length VCDL with multiple finite-length VCDLs. This DLL is combination of a replica biasing circuit for low-jilter characteristics and a duty cycle corrector immune to prevalent process mismatches.

Figure 2-4:- Architecture for A Dual-Loop Delay-Locked Loop using Multiple Voltage-Controlled Delay Lines.

(3.0)METHODOLGY

This section will be discussing the procedures for investigating and applying methods proposed by previous researchers, digital phase detector, 4-bit counter (Binary counter), Demultiplexer , delay chain.

(3.1) Investigation of Methods Proposed by Previous Research

Conventional Architecture

Ranging problem of Conventional DLL's

Figure 3-1

[This conventional DLL's circuit taken from simulation and modeling of delay locked loop][3]

A simplified block diagram of a conventional DLL's as shown in figure 1. The basic component that required compiling a conventional DLL's are phase detector, charge pump, first order loop filter, and a voltage controlled delay line (VCDL). Firstly, the reference signal clock will be pump into the voltage controlled delay line ( which are consist of many delay buffer) then the output signal of the VCDL will drive the phase detector ( depicted in the example as a conventional flip-flop). Thus the output from the phase detector will be driving the charge pump and first order loop filter to generate the loop voltage Vc. Thus, analog DLLs is also use as a continuously variable delay line, therefore the DLL can be designed to exhibit less phase error (or jitter) than digital DLLs, which are also suffer from quantization error due to the discrete delay steps. Besides that, analog or also known as conventional DLLs can be designed to use less layout area and consume less power, but they are more process dependent, making them less portable than digital DLLs. Moreover, analog DLLs also have a tendency to be more susceptible to digital noise than a digital DLL. [http://cmosedu.com/jbaker/students/Wide%20Range,%20Low%20Jitter%20Delay-Locked%20Loop%20Using%20a%20Graduated%20Digital%20Delay%20Line%20and%20Phase%20Interpolator.pdf ][4]

PD

KPD

Filter

G F(S)

Delay Line

KDL

Delay_in

Delay_out

Vc

In

Figure 3-2:-DLL architecture [Phase-Locking in High_Perfomance Systems, IEEE Press,2003]

Figure 3-3:-open -and closed loop transfer characteristics. [Taken from IEEE Press,2003]

From the figure 1, the author able to justify that the phase detector is to compare the "In" signal with the "Delay_in" signal and the comparison between the both signals is actually proportional to the phase error. Then, the phase error will be filtered from the low pass filter to produce a controlling voltage or current that will be fed to adjust the delay of the delay line. Therefore the delay line can be able to increase the delay or decrease the delay that will fed to the reference input or a clean clock signal.

Base on the architecture, the author manage to derive a transfer function for the equation base on the s-domain as below:-

H(s) = ; s = 0

Whereas:-

H(s) = the transfer function for the equation

K PD = the gain for phase detector

G F(s) = the gain for filter

KDL = the gain for the delay line

Besides that, the feedback loop would be able to guarantee a fixed phase relationship between the delay-line and the reference clock signal. This is because the phase different between them will be appear at the delay line output in all pass response.

(2.2) Digital Delay Locked Loop

In this research this author proposed to use digital phase detector, counter and delay chain to implement a Digital Delay Locked Loop.

Digital phase detector:-

Phase detector is one of the devices that able to know the relationship between two signals either in phase or out of phase. Thus this device is widely using in many systems such as delay locked loop, phase lock loop and many more. PLL is a circuit that causes a particular system to track with another system. This author implement this phase detector is to control the sampling data in the receiving domain. It is because by using the phase detector, this author mange to track how much different between two incoming phases. The phase detector is used to acquire the phase relationship between the receiving clock and the data. [http://www.electronics-manufacturers.com/products/electrical-electronic-components/phase-detector/ ] [4]

Proposed digital phase detector:-

As we know tuning precision is most depending on the characteristic of phase detector, therefore this author suggested digital phase detector. From this suggested phase detector, it manages to overcome the circumstances that facing from the conventional delay locked loop. This author using "xor" gate theory to implement the digital phase detector. By using this theory, it manages to differentiate the phase for both frequencies. Thus, when both frequencies is compare and detector that both frequencies is in-phase then it will produce a constant output which is level output will remain zero. Thus, by using this implementation is very sensitive whereby although there are slightly different of phases, the output will be inverted. For example, the phase of the clock signal and the data sampling is different by 1°, the XOR gate's output will be high for 1/180th of each cycle - the fraction of a cycle during which the two signals differ in value. When the signals differ by 180° - that is, one signal is high when the other is low, and vice versa - the XOR gate's output remains high throughout each cycle. [http://en.wikipedia.org/wiki/Phase_detector][5]

The XOR detector compares well to the analog mixer in that it locks near a 90° phase difference and has a square-wave output at twice the reference frequency. The square-wave changes duty-cycle in proportion to the phase difference resulting.

Figure 3-4:- Phase detector which are implemented by XOR [http://cmosedu.com/jbaker/students/Wide%20Range,%20Low%20Jitter%20Delay-Locked%20Loop%20Using%20a%20Graduated%20Digital%20Delay%20Line%20and%20Phase%20Interpolator.pdf]

As mention in the earlier stage, the function for phase detector is to differentiate both input and it will compare the phase. Therefore the two inputs is represented by ᵠ1 and ᵠ2 and if both input consist of phase different of 90° the output will produces the signal as the figure1. The output will produce an average signal of . But there are a assumption condition of the phase error will be at zero. From this, this author can justifies that the equation for phase error is |ᵠ1 - ᵠ2 |-90°, meanwhile the average output will vary across in proportional to phase error.

Counter:-

The counter setting delay chain is using 4-bit up/down Binary counter instead of 4- Bit up/down Gray-code counter.

For example during the initialization state, when the 3rd bit of delay chain setting is selected, the 1st ,2nd and 4th bit will always be 0 and the initialization setting will be 0010 to be as the select bit for the demultiplexer to selected the respective delay chain. Therefore the optimum initialization setting is dependent on the frequency of the reference clock.

Meanwhile during the normal operation, when the counter reaches its max value, which is 1111 (in Binary counter) for 4- bit setting, it will stay at max value instead of rolling over to 0000. When the counter is 0000 and the two different frequencies is align, it will stay at 0000. And when the signal for both frequencies is different, counter will start to count up or down based on the different phase of the two frequencies.

After the counter start to count the different phase in between both frequencies, a demux controlled by a configuration bit is used to selected between the appropriate delay chain that been designed.

DC #1

DC #2

DC # 3

Select bit from counter

Demux

Figure 3-5:- determine the output of the counter will be as the select bit for the demultiplexer.

The operation for this 4-bit Binary counter is to count the phase difference between the data-clock and the reference-clock in form of 4 bit. Initially the counter will remain at "RESET" condition, "0000" and if the phase detector detect there are phase different it will trigger the counter. Then the counter will start to count from "0000" until the phase is aligned. For example,

Delay line:-

Variable delay elements are inverter- based circuit is used for fine, precise and accurate pulse delay control in a high-speed digital integrated circuits. Therefore, to achieve wide phase shift variable delay elements are used as a chain of inverters. The chain of inverters is called delay lin. Delay line consists of fully analog, semi analog and digital delay line. Most of the researcher is using analog delay line to operate the Delay Locked Loop.

Full analog delay line:-

Voltage controlled delay line (VCDL) is used to achieve the infinite delay range by using four finite-length VCDLs. Basically VCDL is composed into four main delay cells and each cells consist of 45° phase shift at locked condition. All delay cells including delay buffers are differential elements which are commonly controlled by the output of the charge pump. However, to achieve the entire 360° phase range, the clocks from reference loop are partially inverted and inputted to four sets of VCDL in the main loop. [13]

Figure 3-6:-The circuitry for the VCDL

Figure 3-7:- the main loop VCDL controls procedure.

Semi analog delay line (Current-Starved Inverter Delay Line)

Current starved delay elements are implemented using current inverters of transistors M4 and M3. [14]Basically the capacitor is controlling the charging and discharging current of the output parasitic capacitor, C. We can derive the time delay in analog voltage controlled delay elements for the following formula as below:-

T delay = [V sw] ------- (1)

C = is the load output capacitance

Icp = corresponds for charging and discharging current of C

Vsw = clock buffer (inverter) swing voltage

Figure 3-8:- The circuitry for Current-Starved Inverter Delay Line

The output of counter is fed to the input of delay line to determine how much of the delay should be selected to align the clock and the data frequency.

Figure 3-9:- Scheme of bias circuit.

Proposed for the digital delay line:-

The proposed scheme for delay line is counter base delay line. It consist of 16 set of digital delay line with respective delay. The proposed delay buffer is uses several new techniques such as counter base delay line is to reduce its power consumption. Therefore, delay buffers are accessed sequentially where it adopts a ring counter addressing scheme. This counter is able to decrease the loading capacitive, thus saving even more power.

When the phase detector detects the phase different between two frequencies, the output of the phase detector will be trigger the counter. The output of the counter will trigger the digital delay line with respective delay required. For example, the data clock is leading the reference clock for 20 ns, the phase detector will be detecting the phase different. After the phase detector detect the different the counter will be start to count the step difference for two frequencies. Thus, the output of the counter will trigger the demultiplexer to select the respective digital delay line to align the two frequencies.

(4.0)Project Testing: Result and discussion

This section presents the results of the performance benchmarking of the proposed algorithm.

(4.0.1)Phase Detector and counter

The simulation for the phase detector and counter as following below:-

Figure 4-1:- Functional simulation for the phase detector with counter

Clk = CLOCK for the operating system at 50 MHz

Rst = RESET input for the user to reset the whole system

X1= Ref_CLK for the system that required

X2= Data_CLK for the external hardware

Count = Result of counting from the counter

Basically two input different frequencies that fed into the system are Ref_CLK and Data_CLK. The phase detector detect the phase different in between Ref_CLK and Data_CLK, it will trigger the counter to start count. For example, at between ranges of 40ns-10ns, Data_CLK is leading the Ref_CLK with 30 ns. The phase detector is detected and it will trigger the 4-bit counter to count the step different for the two frequencies. As the figure 4-1, the counter is start counting from 0 to 2 and it will remain constant at 3 when the two frequencies are in phase.

Figure 4-2:- Timing simulation for the phase detector with counter.

Clk = CLOCK for the operating system at 50 MHz

Rst = RESET input for the user to reset the whole system

X1= Ref_CLK for the system that required

X2= Data_CLK for the external hardware

Count = Result of counting from the counter

Basically, timing simulation is the closest emulation to actually downloading a design to a device. Therefore it will check that the implemented design will meets all functional and timing requirements and behaves will be expected in the device. Thus, having inertia to overcome during signal changes and foreseeable data path to cover from end to end. Comparing the result at figure 4-2 with figure 4-1, the delay that adding into the system is actually 6.198ns.

Figure 4-3:- RTL viewer for the phase detector with counter

The RTL viewer is a useful tool in Quartus2. This tool can be used effectively to facilitate the development of VERILOG code for a circuit that is being designed. It provides a pictorial feedback to the designer, which gives an indication of the structure of the circuit that the code will produce. Viewing the pictures makes it easy to spot missing elements, wrong connections, and other typical errors that one makes early in the design process. From figure 4-3, it shows clearly the design of the entity project.

Figure 4-4:- The pos mapping for the phase detector with counter

Figure 4-4 is a viewer which embedded into the Quartus 2 simulation for the user to check the schematic of the design. Thus, this RTL viewer is also enable the user to view the initial and fully mapped synthesis results during the debugging, optimization, or constraint entry process.

Figure 4-5:- The timing analysis structural

Figure 4-6:- The analysis from time-quest for phase detector with counter

Figure 4-7:- The power analysis for phase detector with counter

Overall the thermal power for this phase detector with the counter is approximately 30.06mW. From the figure 4-7, it shows that the digital phase detector and 4 bit counter is consume small thermal power.

Figure 4-8:-summary of timing analysis.

The table in Figure 4-8 also shows the measurements of other timing parameters. While fmax is a function of the longest propagation delay between two registers in the circuit, it does not indicate the delays with which output signals appear at the pins of the chip. The time elapsed from an active edge of the clock signal at the clock source until a corresponding output signal is produced (from a flip-flop) at an output pin is denoted as the tco parameter at that pin. In the worst case, the tco in this author circuit is 6.870 ns. Click on tco in the Timing Analyzer section to view the table given in Figure 4-9. Besides that, the other two parameters given in Figure 4-8 are setup time, tsu, and hold time, th.

Figure 4-9 :- The tco delays

Figure 4-10:- critical path

(4.0.2)Digital Delay Line

Figure 4-11:- Functional simulation for the Delay line of 20ns

Clk = Clock of the system

Enable = This system is operating in active low

X = To start delaying by respectively delay

B= Output

When the delay locked loop is simulating, the enable for each delay cell is not active until the respective delay cell is trigger in the enable mode. Once the enable is selected to LOW, the delay cell will start operating by shifting the respective delay and sent to the output of B.

Figure 4-12:- Timing simulation for Delay line of 20ns

Clk = Clock of the system

Enable = This system is operating in active low

X = To start delaying by respectively delay

B= Output

Basically, timing simulation is the closest emulation to actually downloading a design to a device. Therefore it will check that the implemented design will meets all functional and timing requirements and behaves will be expected in the device. Thus, having inertia to overcome during signal changes and foreseeable data path to cover from end to end. Meanwhile timing simulation also adds additional - propagation delays along the various paths in the fitted circuit are analyzed to provide an indication of the expected performance of the circuit. As the output, B is shifted by 5.775 ns from the actual output.

Figure 4-13:- RTL viewer for the delay line of 20ns

The RTL viewer is a useful tool in Quartus2. This tool can be used effectively to facilitate the development of VERILOG code for a circuit that is being designed. It provides a pictorial feedback to the designer, which gives an indication of the structure of the circuit that the code will produce. Viewing the pictures makes it easy to spot missing elements, wrong connections, and other typical errors that one makes early in the design process. From figure 4-13, it shows clearly the design of the entity project.

Figure 4-14:- Post mapping viewer for the delay line of 20ns

Figure 4-14 is a viewer which embedded into the Quartus 2 simulation for the user to check the schematic of the design. Thus, this RTL viewer is also enable the user to view the initial and fully mapped synthesis results during the debugging, optimization, or constraint entry process.

Figure 4-15:- Timing analysis structural for the delay line of 20ns

Figure 4-16:- Time quest for the delay line of 20ns

Figure 4-17:- The power analysis for the delay line of 20ns

Overall the thermal power for this phase detector with the counter is approximately 30.06mW. From the figure 4-17, it shows that the digital phase detector and 4 bit counter is consume small thermal power.

Figure 4-18:- summary of timing analysis.

The table in Figure 4-18 also shows the measurements of other timing parameters. While fmax is a function of the longest propagation delay between two registers in the circuit, it does not indicate the delays with which output signals appear at the pins of the chip. The time elapsed from an active edge of the clock signal at the clock source until a corresponding output signal is produced (from a flip-flop) at an output pin is denoted as the tco parameter at that pin. In the worst case, the tco in this author circuit is 5.775 ns. Click on tco in the Timing Analyzer section to view the table given in Figure 4-19. Besides that, the other two parameters given in Figure 4-18 are setup time, tsu, and hold time, th.

Figure 4- 19:- The tco delays

Figure 4-20:- critical path

(4.0.3) Combination of whole system, DLL

(5.0)CONCLUSION

The aims of the project have been met. This project has applied methods by previous researchers, and also formulated with new technology of the Delay Locked Loop.

The proposed mythology using digital delay locked loop is able to save more power consumption, able to work in wide range of operating frequency, low jilters, will have more benefits in the noise sensitivity, lower power consumption and jilters' performance and by using this technology it can be provide the ability to stop the clock, facilitation power management.

The algorithm was tested in simulation of digital delay locked loop. The results for the phase align of successful for each operating frequency are as follows:-

50MHZ :

25MHZ:

30MHZ:

No

Technical Objectives

Status and Explanation

( to be done at conclusion of FYP report )

1

Able to generate a counter based on the requirement

Achieved.

2

Able to phase shift accordingly based on the reference frequency

Achieved.

3

Able to build a delay chain

Achieved.

4

To investigate the delay locked loop

Achieved.

5

To be able a delay circuit for shifting the phase of the reference signal according to the integral phase error

Achieved.

6

To locked particular delay on the system

Achieved.

7

To decide on a suitable method programming for the device

Achieved.

8

To write a suitable programming code for the delay locked loop

Achieved.

Table 5-1: Achievement of project objectives.

(5.1) Recommendations for Further Work

Several areas that could be improved or extended in further work:

Apply more delay cells to create more precise steps

Create counter with more higher bits using Gray Code Counter for wider frequency range

Enhancement of power saving feature to improve power consumption

Cyclone 2 FPGA

Why want to choose Cyclone 2 FPGA (EP2C20F484C7N FPGA)

This Cyclone 2 FPGA consists of maximum 18754 logic elements that are able to use. Besides from that the maximum input/output that able to be use are 315 free slots. Thus, the Cyclone II FPGA family is the second-generation family in Altera's low-cost Cyclone series. Cyclone II FPGAs offer 30 percent lower costs and more than three times the logic density than first-generation Cyclone devices. [http://www.altera.com/products/devices/cyclone2/utilities/cy2-q_a.html#General_What_Is]

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