Purpose Of Bus Architecture Computer Science Essay

Published: Last Edited:

This essay has been submitted by a student. This is not an example of the work written by our professional essay writers.

The purpose of bus is to connect, transfer signal and data between devices inside the computer. In the computer, bus is also known as channel or pathway which transfers data from one device to another device.

These devices inside the computer communicate with each other via many different ways. Almost the components inside computer include in CPU, cache memory, input and output devices transfer data with each other via one or many bus. In technically, two devices are connected on one bus normally called a port instead of bus. In a bus structure, there are a lot of separate lines.

There are 3 types of buses are Data bus, Address bus and Control bus. Depending on the type of the bus and computer the bus's operation can be unidirectional or bidirectional.

Data line is used to transmit the instruction in two ways: from processor to devices and from the device to the processor. It is unidirectional bus.

Address bus transfer the memory address to the processor. It is bidirectional bus.

Control bus which transmit signal for the central unit (CU), it also decide whether the data should be write or read on the data bus. It is bidirectional bus.

C:\Users\Garry Nguyen\Desktop\000.jpg

Bus Structure

Parallel Bus can transmit data in parallel via multiple wires ex: 32-wire cables can carry 32-bit in parallel. Serial Bus can transmit data in bit-serial form.

The width of data bus is very important because it refers to numbers of data bits the bus line can transmit at time.Ex:32 -bit unit of data can be transmitted over thirty-two bus lines. And the bus speed can be measured by clock speed in frequency (MHz) -the number of data packet was sent or receive in one second.)

At one time, bus just transmits data with one device whose address has been confirmed. It is the same as bus only stop at one town or bus station to catch the passenger at one time.

Nowadays, almost modern computer have general 2 buses: internal bus and external bus. There are 2 kinds of Bus I/O: Local I/O Bus (Internal Bus) and Standard I/O Bus (External).

Standard I/O Bus

ISA (Industrial Standard Architecture) is used to connect external peripheral which require slower speed such as modem, mouse, keyboard.... The disadvantages of this bus is despite the speed of CPU is so high but it just communicate with peripheral devices' speed is not over 33MBps.It cannot support the graphical card was plug in bus cache .Bus ISA was developed by IBM, is used for the system which only control by the CPU on the main board, it means all devices and application was control by this CPU. The width of unit data is 8 bits (XT) or 16 bits (AT).

This is the extension of the ISA standard to allocate the 32 bits of data but retains the

bus compatible with the old pair. EISA bus has 2 rungs, signals of ISA are sent through the upper rung and signals auxiliary of EISA through bottom rung. There are some specifications of EISA:

Mechanical term: it has more pins but it still compatible with ISA.

Data width: it can access 2 lines in 8 bits or 2 lines in 16 bits. It helps increase the transmission rate up to 33MBs.

Address width: Beside of having 24 lines same as ISA, it add 8 lines so that it can access 4GB of memory.

Local I/O Bus

Local I/O Bus is used to connect between these devices which require high speed such as CPU, memory and chipset. Local bus gives more expansion slot to connect direct to local bus. So that expansion bus allow transmit over 32-bit and use the speed of CPU.

Intel has already developed PCI bus in 1993. Bus PCI is bus of i486 in their data and address were sent by fetching multiplexing channel. Data and address were fetching together on pathway of PCI. CPU, main memory, PCI bus are connected together by PCI Bridge. Maximum 10 devices can connect to PCI bus, PCI Bridge is referred as one of them. PCI bus can run with 32bits of width and achieve 133MBs (32 bits at 33MHz or it can transmit data with speed up to 533MBs (64 bits at 66MHz)

Video Electronic Standard Association (VESA) has developed VL bus.

Hardware support to Memory Management

RAM

RAM (Random Access Memory) is the main memory of computer. RAM is called Random Access Memory because it's specification: time to write or read each cell is all the same despite it's in any position of the memory. Each memory cell of RAM has only one address. Generally, one cell is one byte (8bits); although the system memory can read and write more than one byte (2, 4, 8 byte). C:\Users\Garry Nguyen\Desktop\540454b381e1397c3b.jpg

RAM is different form SMD (Sequential Memory Device) such as tape, CD. These devices have the system move physically sequentially to read and write the data.

Because RAM can read and write data so that RAM is known as read-write-memory. Otherwise ROM just can read (read-only-memory)

RAM often is used for main memory in computer to store information changes and information is currently used. Some devices used RAM as secondary storage.

RAM is often associated with volatile types of memory these program are stored temporarily will lost when the power is removed

RAM Specification:

There are 4 specifications of RAM

* Memory: The total number of bytes of memory (if calculated in bytes) or the total number of bits in the memory (if the calculated bits).

* Organization of memory: memory cell number and the number of bits per memory cell

* Time entry: The time between making the address of the memory cell to be read as the contents of that memory cell.

* Memory Cycle: Time between two consecutive memory accesses.

Types of RAM

Depending on technology to develop RAM, there are 2 types of RAM:

SRAM (Static Random Access Memory): there are 6 transistors in one memory cell of Static RAM.SRAM was built in ECL technology (used in CMOS and BiCMOS). Each memory bit consists of logic gate with 6 transistors MOS. SRAM is the fast memory to read and not destroy contents of the memory and time to access is the same as memory cycle.

DRAM (Dynamic Random Access Memory): One transistor and one capacitor in one memory cell on Dynamic RAM. DRAM is built in MOS technology. Each memory bit consists of one transistor and one capacitor. The memory data is based on maintaining the charge of capacitor and the reading one memory bit make the contents of this will be destroy. Hence, every time read one memory cell; the memory controller has to write the contents of this memory cell. So that memory cycle is at least double time to access memory cell. Storing information in memory bit is temporary because capacitor will charge its full potential and thus loaded to refresh the memory 2μs period. The refresh is done with all the memory cells in memory. This work is done automatically by a memory chipset.