Pi Pid Fuzzy Logic Controllers Based Computer Science Essay

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This paper presents phase locked loop along with proportional integral, proportional integral derivative and fuzzy logic controller based shunt active power line conditioners (APLC) for the power-quality improvement such as current harmonics and reactive power compensation due to the non-linear/unbalanced loads. The shunt APLC system is implemented with three phase PWM current controlled voltage source inverter (VSI) and is connected at the point of common coupling for compensating the current harmonics by injecting equal but opposite filter current. The compensation process is based on PLL synchronization with PI or PID or fuzzy logic controller. These controllers are having the capable of controlling dc-side capacitor voltage and extracting reference currents. Hysteresis current controller (HCC) is used to generate switching signals for operate the PWM voltage source inverter. Extensive simulation studies under different non-linear and unbalanced load conditions are conducted, these simulation result analysis reveal that the APLC performs perfectly with PI, PID and FLC control strategy. A comparative assessment of the three different controllers is brought out.

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Keywords-active power line conditioners (APLC), PLL synchronization, PI, PID, Fuzzy logic controller (FLC), hysteresis current controller (HCC)

Introduction

AC power supply feeds different kind of linear and non-linear loads in utilities, commercial and industrial applications. The non-linear loads produce harmonics. The harmonic and reactive power cause poor power factor and distort the supply voltage at the customer service point [1-3]. Conventionally passive filters are used to compensate the lagging power factor of the reactive load and harmonic problems, but these passive filters are having some drawbacks; such as resonance, large size, weight, and limited too few harmonics. The different configurations of static VAR compensators (SVCs) have been participated for solve these problems of power-factor correction; but some SVCs produce lower-order harmonics themselves and response time of some SVCs may be too long to be acceptable for fast-fluctuating loads [2-3]. Recently active power filters (APF) or active power-line conditioners (APLC) are developed for compensate the current-harmonics and reactive power simultaneously due to power factor correction. The active power filter can be connected in series for voltage harmonic compensation and in parallel for current harmonic compensation. Most of the industrial applications need current harmonic compensation, so the shunt active filter is popular than series active filter. The shunt APF has the ability to keep the mains current balanced and sinusoidal after compensation regardless of whether the load is non-linear and balanced or unbalanced [5].

The controller is the heart or primary component of the APF topology. Conventional PI and PID controllers are used to extract the fundamental component of the load current thus facilitating reduction of harmonics and simultaneously controlling dc capacitor voltage of the shunt active filter [6-8]. Recently, fuzzy logic controllers (FLC) are used in power electronic system, drive applications and active power filters. The phase locked loop (PLL) controller can operate satisfactorily under highly distorted system [3].

This paper presents the feasibility of PI, PID and fuzzy logic controller along with PLL synchronization controller based shunt active power filter for the harmonics and reactive power mitigation due to the non-linear and unbalanced loads. The fundamental component of the reference current is extracted from load current using PI or PID or fuzzy logic controller methods and dc-side capacitor voltage of the inverter is continuously maintained constant. The PWM-VSI gate control signals are generated from the hysteresis current control technique. The proposed concept for shunt APLC system is validated through extensive simulation under different loads conditions and a comparative assessment is done.

Proposed Control Strategy

PI-Controller:

Figure 2 shows the block diagram of the proposed PI control scheme for the active power filter. The DC side capacitor voltage is sensed and compared with a reference voltagr. The error at the sampling instant is used as input for PI controller. The error signal examine with Butterworth design based low pass filter (LPF). The LPF filter has cutoff frequency at 50 Hz that can suppress the higher order components and pass only fundamental components. PI controller used to estimate the magnitude of peak reference currentand control the dc-side capacitor voltage of PWM-VSI. Its transfer function is represented as

Where, [=0.7] is the proportional constant that determines the dynamic response of the DC-bus voltage control and [=23] is the integration constant that determines it's settling time. The proportional integral controller is eliminating the steady state error in the DC voltage.

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PID Controller

Fig. 2 shows the block diagram of the proposed Proportional Integrator Derivative (PID) control scheme of an active power filter. The error at the sampling instant is used as input for PID controller. The error signal examine with LPF filter; that can suppress the higher order components and pass only fundamental components frequency.

LPF

X

X

X

Vsc

Vsa

Vsb

isa*

isc*

isb*

Vdc,ref

Vdc

PID-Controller

Integrator

Gain

PI-Controller

Derivative

Gain

Proportional

Gain

PLL Circuit

Ic1

Ib1

Ia1

Fig 1 PI and PID with PLL Controller block diagram

The PID controller is a linear combination of the P, I and D controller. Its transfer function can be represented as

where, is the proportional constant that determines the dynamic response of the DC-bus voltage control, is the integration constant that determines it's settling time and is the derivative of the error representing the trends. The controller is tuned with proper gain parameters [=0.7,=23, =0.01] for estimate the magnitude of peak reference current and control the dc-side capacitor voltage of PWM-VSI. The peak reference current multiplied with PLL output determines the desired reference current.

Fuzzy Logic Controller:

Fuzzy logic control is deduced from fuzzy set theory in1965; fuzzy theory concept that transition is between membership and non membership function. Therefore, limitation or boundaries of fuzzy sets can be undefined and ambiguous; FLC's are an excellent choice when precise mathematical formula calculations are impossible. Fig 1 shows the active power filter compensation system and the fuzzy logic control scheme. In order to implement the control algorithm of a shunt active power filter in a closed loop, the dc capacitor voltage is sensed and then compared with the desired reference value. The compared error signal that allows only the fundamental component using the Butterworth 50 Hz low pass filter (LPF). The error signaland integration of error signal is called change of error signalthat are used as inputs for fuzzy processing shown in fig. 2. The output of the fuzzy logic controller limits the magnitude of peak reference current. This current takes care of the active power demand of the non-linear load and losses in the distribution system. The switching signals for the PWM inverter are generated by comparing the actual source currents with the reference current using the HCC method.

e(n)

ce(n)

Defuzzification

Data Base

Rule Base

Fuzzification

Rule Evaluator

(Decision making

+

-

-

Vdc

Vdc,ref

LPF

Integrator

Fig 2 Fuzzy logic controller

Fuzzification:

Fuzzy logic uses linguistic variables instead of numerical variables. In a control system, error between reference signal and output signal can be assigned as negative big (NB), negative medium (NM), negative small (NS), zero (ZE), positive small (PS), positive medium (PM), positive big (PB). The triangular membership function used in fuzzifications. The processes of fuzzification are numerical variable (real number) convert to a linguistic variable (fuzzy number).

Rule Elevator:

In conventional controllers PI and PID having control gains or control rules which are combination of numerical values. In fuzzy logic controller uses linguistic variables on nature instead of the numerical variables. The basic fuzzy logic controller operations of fuzzy set rules derived as

-Intersection:

-Union:

-Complement:

Defuzzification:

The rules of fuzzy logic controller generate required output in a linguistic variable (Fuzzy Number), according to real world requirements; linguistic variables have to be transformed to crisp output (Real number). This selection of strategy is compromise between accuracy and computational intensity.

Database:

The Database stores the definition of the triangular membership function required by fuzzifier and defuzzifier.

Rule Base:

The Rule base stores the linguistic control rules required by rule evaluator (decision making logic). The rules used in this proposed controller are shown in table 1.

Table 1 Rule base table

ce(n) e(n)

NB

NM

NS

ZE

PS

PM

PB

NB

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NB

NB

NB

NB

NM

NS

ZE

NM

NB

NB

NB

NM

NS

ZE

PS

NS

NB

NB

MN

NS

ZE

PS

PM

ZE

NB

NM

NS

ZE

PS

PM

PB

PS

NM

NS

ZE

PS

PM

PB

PB

PM

NS

ZE

PS

PM

PB

PB

PB

PB

ZE

PS

PM

PB

PB

PB

PB

The output of the fuzzy controller is estimate the magnitude of peak reference current. This current takes response of the active power demand of the non-linear load and losses in the distribution system. The peak reference current multiply with PLL synchronizing output current for determine the desired reference current.

PLL Synchronization

Sin (ωt - π/2+2π/3)

Sin (ωt - π/2-2π/3)

Sin (ωt - π/2)

Sin (ωt)

Sin (ωt+2π/3)

PI

Controller

Vab

Vcb

ia1

ib1

ic1

Fig 3 synchronizing PLL circuit

The phase locked loop circuit design should be consists perfect operation under distorted and unbalanced voltages [6]. The PLL-synchronizing circuit shown in fig 3, determines automatically the system frequency and the fundamental positive sequence components of three phase line voltages and. The outputs of the PLL synchronizing circuit areof the three phase currents. This algorithm is based on the instantaneous active three-phase power expression, it's written by

The current feedback signals and is built up by the PLL circuit and time integral of output calculated of the proportional integral (PI)-controller. It is having unity amplitude and lead to 1200 these represent a feedback from the frequency. The PLL synchronizing circuit can reach a stable point of operation when the input of the PI controller has a zero average value () and has minimized low-frequency oscillating portions in three phase voltages. Once the circuit is stabilized, the average value of is zero and the phase angle of the supply system voltage at fundamental frequency is reached. At this condition, the currents become orthogonal to the fundamental phase voltage component. The PLL synchronizing output currents are set as

Therefore the PLL output current signals and the distorted/unbalanced source voltages of the power supply are measured and which are in phase with the fundamental component. The PLL output current multiply with fuzzy logic controller output of peak reference currentfor determine the desired reference current.

Lower Band

Upper Band

Actual Current

Reference Current

Hysteresis current controller (HCC)

Fig 4 Diagram of hysteresis current control

The three-level PWM-VSI system of the HCC is utilized independently for each phase and directly generates the switching signal of the phases. An error signal is the difference between the desired current and the actual current. If the error current exceeds the upper limit of the hysteresis band, the upper switch of the inverter arm is turned OFF and the lower switch is turned ON. As a result, the current starts to decay. If the error current crosses the lower limit of the hysteresis band, the lower switch of the inverter arm is turned OFF and the upper switch is turned ON. As a result, the current gets back into the hysteresis band.

Here the hysteresis band limit h=0.5. The range of the error signaldirectly controls the amount of ripple voltage in the output current from the PWM-VSI.

Simulation result and analysis

Shunt APLC system is connected in the distribution network at the point of common coupling through filter inductances and operates in a closed loop. The three phase active power filter comprises of six power transistors with power diodes, a dc capacitor, RL-filter, compensation controller (PLL synchronization with PI or PID or fuzzy logic controller) and switching signal generator (hysteresis current controller) shown in the fig 1.

6

VDC,ref

isa*,isb*,isc*

PWM-VSI

Vsa,Vsb,Vsc

isa,isb,isc

ica,icb,icc

Rs,Ls

PCC

Reference current generator

Current

Sensor

Voltage

Sensor

N

Unbalanced load

RL, LL

Vdc Sensor

CDC

iLa, iLb, iLc

RL

LL

Non-sinusoidal Load

3-phase supply

PLL Synchronization Technique

Hysteresis current controller

PI or PID or Fuzzy Logic Controller

Fig 1 shunt active power line conditioners system

The three phase supply source connected to the non-linear load; the instantaneous source current the instantaneous source voltage is. The nonlinear load current will have a fundamental component and harmonic current components, which can be represented as

If the active power filter provides the total reactive and harmonic power, will be in phase with the utility voltage and would be sinusoidal. At this time, the active filter must provide the compensation current; therefore the APLC estimates the fundamental load current and compensates the harmonic current and reactive power.

The performance of the proposed PI, PID and fuzzy logic control with PLL circuit strategy is evaluated through digital simulation using Matlab/Sim power tools in order to model and test the system. The system parameters values are; Line to line source voltage is 440 V; System frequency (f) is 50 Hz; Source impedance of RS, LS is 1 Ω; 0.1 mH; Filter impedance of Rc, Lc is 1 Ω; 1 mH; Unbalanced RL, LL,values are 10 Ω, 50 Ω, 90 Ω and 10 mH respectively. Diode rectifier RL, LL load: 20 Ω; 100 mH; DC side capacitance (CDC) is 1200 μF; Reference voltage (VDC, ref) is 400 V; Power devices build by IGBTs with freewheeling diodes.

Case 1: Proportional Integral controller

The three phase unbalanced RL load connected parallel with diode rectifier non-linear load in the three phase ac main network and active power filter connected in parallel at the PCC for suppress the harmonics and reactive power. The simulation result of the unbalanced RL load current is shown in 6 (a). The six-pulse diode rectifier load current or source current before compensation is shown in fig 6 (b)The source current after compensation is presented in fig 6 (c) that indicates the current becomes sinusoidal. The shunt active filter supplies the compensating current based on the proposed controller that is shown in fig. 6(d). This system achieved power factor correction as shown in fig 6(d).

Fig.6 Simulation results for three-phase APF under Non-linear with Unbalanced load condition (a) RL Load current (b) Load currents (c) Source current after active filter (d) Reference currents (e) Compensation current and (f) unity power factor

The dc side capacitance voltage (Cdc) and its settling time are controlled by PI controller; this controller reduces the ripple and makes less settling time plotted in fig 7, both non-linear (t= 0.25s) and non-linear with unbalanced load (t=0.037s)

Fig 7 the DC side capacitor voltage settling time controlled by FLC non-linear with Unbalanced load (t=0.031s)

The Fast Fourier Transform (FFT) is used to measures the order of harmonics with the fundamental frequency 50 Hz at the source current. This order of the harmonics plotted in fig 8, under non-linear with unbalanced load condition.

Fig 9 Order of harmonics (a) the source current without active filter (THD=%), (b) with active power filter(THD=%)

Case 2: Proportional Integral Derivative controller:

The PLL with PID controlled simulation waveforms are verified and presented. The source current after compensation is fig 5 (a); that indicates the current is sinusoidal. The load current is shown in fig 5 (b). The shunt active power filter supplies the compensating current is shown in fig. 5(c).

Fig.6 Simulation results under Non-linear load condition (a) Source current after active filter (b) Load currents (c) Compensation current

Case 3: Fuzzy logic controller:

PLL with FLC based APF system of simulation results are verified and presented;

Fig.5 Simulation results (a) Source current after active filter (b) Load currents (c) Reference currents (d) Compensation current (e) DC side capacitor voltage settling time

The summarized DC voltage settling time compared PI, PID and Fuzzy logic controller, shown in table 2

Table 2 comparison of PI, PID and FLC for DC voltage settling time

Load

conditions

VDC settling time in seconds

PI

PID

FLC

Non-linear

0.25s

0.23s

0.23s

Non-linear with Unbalanced

0.037s

0.033s

0.029s

This order of the harmonics plotted under non-linear load condition in the distribution supply current is shown in fig 8.

Fig 9 Order of harmonics (a) the source current without active filter (THD=%), (b) with active power filter(THD=%)

The PI, PID and FLC with PLL synchronizing control based APF system of the total harmonic distortion (THD) measured from source current and compared, shown in table 3.

Table 4 THD comparison of PI, PID and FLC Techniques

Load conditions

Source Current(IS) without APF

Source Current(IS) with APLC

PI

PID

Fuzzy logic

Non-linear

26.79%

2.42%

2.36%

2.15%

Non-linear with Unbalanced

22.37%

4.68%

4.54%

4.41%

The simulation is done various Non-linear and unbalanced load conditions. The PI, PID and fuzzy logic controller with PLL synchronizing control based compensator filter made balance responsibility even the system is unbalanced. FFT analysis of the active filter brings the THD of the source current into compliance with IEEE-519 standards.

Conclutions

The investigation demonstrates a novel fuzzy logic controller is conjunction with the PLL synchronizing circuit facilitates APLC practicality. The FLC ensures that the dc-side capacitor voltage is nearly constant with very little ripple besides extracting fundamental reference currents. The PLL synchronizing circuit assists the APLC to function even under distorted voltage or current conditions. The shunt APLC is implemented with three phase PWM current controlled voltage source inverter and is connected at the point of common coupling for compensating the current harmonics and reactive power. The PWM-VSI gate control signals are derived from hysteresis band current controller. The proposed controller based shunt active power filter performs perfectly under different load conditions. Important performance parameters are presented graphically. This approach brings down the THD of the source current to become 2.11 % under non-linear load that is compliance with IEEE-519 and IEC 61000-3 standards. This fuzzy logic with PLL control algorithm based APLC system can be implemented field programmable gate array (FPGA) devices in the future work.