On Chip Static Ram Computer Science Essay

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The LPC2106 consists of an emulation supported ARM7 Local Bus ARM7TDMI-S CPU, for on-chip memory controllers interface,, to interface with interrupt controller AMBA Advanced High-performance Bus (AHB) , and for on-chip peripheral functions connection VLSI Peripheral Bus (VPB, a compatible superset of ARM's AMBA Advanced Peripheral Bus). It is in byte order little-endian that the ARM7TDMI-S processor is configured by LPC2106. 2 megabyte range of addresses is allocated to AHB peripherals at the memory space 4 gigabyte ARM on very top position itself. A 16 kilobyte address space is also allocated to each AHB peripheral within the address space of AHB. It is to VPB bus that connection of LPC2106/05/04 peripheral functions (except interrupt controller) is given. . The VPB bus to the AHB bus is interfaced by AHB to VPB bridge. Other than this address with a range of 2 megabyte is allocated to VPB peripherals starting at the address point of 3.5 gigabyte. A 16 kilobyte address space is allocated to each VPB peripheral within the VPB address space. It is the Pin Connection Block that controls the connection of device pins and on-chip peripherals. For this to fit to specific requirements of application it is necessary that this is configured with the aid of software and then only it will be useful to peripheral pins and functions.

1.2 ARM7TDMI-S PROCESSOR

32-bit microprocessor for general purpose is the ARM7TDMI-S and this offers very less power consumption with high performance. It is based on principles of Reduced Instruction Set Computer (RISC) that the ARM architecture is based on. The decode mechanism related to instruction set is much simpler than Complex Instruction Set Computers that are micro programmed. With this simplicity it is possible to gain impressive real-time interrupt response and high instruction throughput from a cost-effective small processor core. Employment of pipeline techniques provides continuous operation of complete parts of memory and processing systems. Decoding of successor is done during execution of one instruction and at the same time fetching of third instruction from memory also takes place. The THUMB is also employed by ARM7TDMI-S processor. THUMB is a unique architectural strategy and this makes the processor suitable for applications for which code density is an issue or high-volume applications that has memory restrictions. THUMB performs on the basis of an instruction set that is super-reduced. There are two instructions set for ARM7TDMI-S processor:

• The standard instruction set with32-bit ARM.

• A THUMB instruction set that is 16-bit.16-bit THUMB instruction set allows an approach that is almost twice denser than standard ARM code and at the same it retains most of the performance advantage of ARM over a 16-bit processor of traditional type using registers of 16-bit. This is feasible for both ARM and THUMB code is operating on same 32-bit register set. UP to 65% of ARM's code size can be provided by THUMB and other than that it can provide 160% of an equivalent ARM's performance when connected to a memory system of 16-bit.

Figure 1: Block diagram

1.3 ON-CHIP FLASH MEMORY SYSTEM

Flash memory system of 128K byte is incorporated by LPC2106/2105/2104. This can be used for both data and code storage. There are several ways to accomplish programming of the Flash memory: JTAG interface that is over the serial built-in one, using In Application Programming (IAP) capabilities or UART0 and In System Programming (ISP). Using In Application Programming (IAP) functions is made use of by the application program to program or erase the Flash during the running of application and this is done by allowing flexibility at great degree for firmware upgrades of data storage field, etc.

1.3.1 ON-CHIP STATIC RAM

The LPC2106, LPC2105 and LPC2104 provide a 64K byte, 32K byte and 16K byte static RAM memory respectively that is useful for data and/or code storage. The SRAM supports 8-bit, 16-bit, and 32-bit accesses. A write-back buffer is incorporated by SRAM controller to prevent stalling of CPU during back-to-back writes. The last data that is sent to RAM by software is always hold back by the write-back buffer. It is only when the software ask for another write that his data is written to the SRAM. In case of a chip reset write request that is most recent will not be reflected in actual SRAM contents. It is necessary to take this into account by any software checking contents of SRAM. A dummy write to an unused location may be appended to any operation in order to guarantee that all data has really been written into the SRAM.

Figure 1 block diagram

Chapter 2 LPC 2106 Memory Addressing

2.1 MEMORY MAPS

Distinct memory regions in several numbers are incorporated by LPC2106/2105/2104given below. It is the entire address space's overall map from user program viewpoint after reset that is given in Figure 2. Address re-mapping is supported by interrupt vector area, and this will be described later.

Figure 2: System Memory Map

2.2 Peripheral memory map

Below figure shows peripheral address space's different views. It is into 128 peripherals that both the VPB and AHB peripheral areas (2 megabyte spaces) are divided into. Size of each peripheral space is 16 kilobytes. With this it is easy to decode address for each peripheral. It is to be noted that regardless of size it is to 32-bit boundaries that all peripheral register addresses are word aligned. Thus byte lane mapping hardware is not necessary for allowing 16-bit half-word or 8 bit byte accesses at smaller boundaries. Both half word and word registers are to be accessed together. For example, upper byte of word registry cannot be written or read separately.

Figure 3: peripheral memory map

Figure 4: AHP peripheral map

Figure 5: VPB peripheral map

2.3 Lpc2106memory Re-Mapping And Boot Block

2.3.1 Concepts of Memory Map and Operating Modes

The basic concept on the LPC2106/2105/2104 is that in the memory map there is a "natural" location for each memory area. Writing of a code that is residing in that area is in this address range. It is in same location that each memory space in bulk is permanently fixed, and thus there is no need to design portions of the code in various address ranges. It is necessary to remap a small portion of SRAM spaces and Boot Block due to location of the interrupt vectors on the ARM7 processor (at addresses 0x0000 0000 through 0x0000 001C). This is to allow alternative interrupts usage in various operating modes as given in Table 3. It is through the feature of Memory Mapping Control that Re-mapping of the interrupts is accomplished and this feature is described in the System Control Block section.

Address

Exception

0x0000 0000

Reset

0x0000 0004

Undefined instruction

0x0000 0008

Software interrupt

0x0000 000c

Prefectch abort

0x0000 0010

Data abort(instruction fetch memory )

0x0000 0014

reserved

0x0000 0018

Irq

0x0000 001c

Irq

Table 1: ARM Exception vector location

2.4 Memory Re-Mapping

To allow compatibility with future derivatives, it is to the top of the on-chip memory space that entire Boot Block is mapped. Thus, the use of flash modules, smaller or larger can avoid location change of the Boot Block. Location change will necessitate Boot Loader code changing) or changing Boot Block interrupt vectors mapping. It is in fixed location that memory spaces except interrupt vectors remain. On-chip memory mapping in above defined modes is given in Figure 6. Interrupt vector area (32 bytes) along with another 32 bytes together forming 64 bytes is remapped for allowing interrupt processing in various modes. The addresses 0x0000 0000 are overlaid through 0x0000 003F by re-mapped code locations. Entire FIQ handler is placed at address 0x0000 001C in the Flash Memory by a typical user program without considering memory boundaries. There need to have branches for the vector contained in external memory, SRAM and Boot Block to other instructions and actual interrupt handlers that accomplish the branch to the interrupt handlers.

This configuration was chosen for three reasons:

1. To avoid memory boundary resulted by re-mapping into account and this will be an advantage to FIQ handler in the Flash memory.

2. Boot Block vectors and SRAM can reduce their deals with arbitrary boundaries that are present in code space middle.

3. Store constants will be provided space to jump beyond single word branch instructions' range. It will be possible for re-mapped memory areas interrupt vectors and Boot Block to appear in re-mapped address as well as in their original location.

2.5 Prefetch Abort And Data Abort Exceptions

In case of an attempt to access a reserved address or an address region that is unassigned appropriate bus cycle abort exception will be generated by LPC2106. Such address regions are:

• Memory map areas that are not specific ARM derivative implemented. Address space between Special registers and On-Chip Non-Volatile Memory is the memory map areas for LPC2106. This is labelled in Figure 2 and 6 as "Reserved for On-Chip Memory". There is an address space between External Memory and On-Chip Static RAM and this is labelled in Figure 2 as "Reserved for On-Chip Memory". External Memory is made use of due to absence of any external bus interface implementation on LPC2106 Figure 3: Reserved regions of VPB and AHB spaces.

• Figure 4: Unassigned AHB peripheral spaces. • Figure 5: Unassigned VPB peripheral spaces.

An exception is generated for these areas by both instruction fetch and attempted data access. For instructions fetch maps to a VPB or AHB peripheral address a prefetch Abort exception is also generated. When tried to access an undefined address there generates a data abort exception within the address space of an existing VPB peripheral. Within each peripheral address decoding is limited to the ones necessary for distinguishing defined registers within peripheral. For example, an access to an undefined address that is with in UARTO, 0xE000D000 is likely to result in access of register that is defined at address 0xE000C000. Such address that is aliasing within a peripheral space is not provided in detail and is not defined in the documentation LPC2106 and the feature is not supported.

Prefetch Abort flag is stored together with associated instruction that is in reality meaningless by ARM core. Instruction and Prefetch Abort flag in the process and pipeline abort only on an attempt to execute illegal address instruction that is fetched. This help to prevent accidental that is likely to result from the execution of a code near to memory boundary.

2.6 Scan Chains and JTAG Interface

There are three JTAG style scan chains inside ARM7TDM and an additional scan chain in the ARM710T. These allow testing, debugging, and Embedded ICE programming and along with that an optional fourth scan chain is also provided support. This is for usage around packaged device pads external boundary scan chain. In the later portion control signals for the purpose of this scan chain is described. The scan chains are controlled from a JTAG-style Test Access Port (TAP) controller. [1]

2.6.1 Scan limitations

The three scan paths are referred to as scan chain 0, 1 and 2: these are shown in Figure 7-2: ARM710T scan chain arrangement on page 7-5.

Scan Chain 0 allows access to the entire periphery of the ARM7TDM core,

including the data bus. The scan chain functions allow

inter-device testing (EXTEST) and serial testing of the core (INTEST). The order of the scan chain (from SDIN to SDOUTMS) is:

• data bus bits 0 through 3

• the control signals

• the address bus bits 31 through 0

Scan Chain 1 is a subset of the signals that are accessible through Scan Chain 0. Access to the core's data bus D [31:0], and the BREAKPT signal is available serially. There are 33 bits in this scan chain. The order is (from serial data in to out):

• data bus bits 0 through 31

• BREAKPT

Scan Chain 2 allows access to the Embedded ICE registers.

Scan Chain 15 allows access to the System Control Coprocessor Registers.

Figure 6: Scan Chain Arrangement

2.7 The JTAG state machine

The process of serial test and debug is best explained in conjunction with the JTAG state machine. A test access port (TAP) controller state transition shows the state transitions that occur in the TAP controller. The state numbers are also shown on the diagram

Figure 8: Test access port (TAP) controller state transitions

2.8 Reset

The state-machine controller also called as TAP controller is included in boundary-scan interface. To force the TAP controller after device power up into the correct state, to the nTRST signal applies a reset pulse. nTRST must be driven LOW and HIGH in order to use boundary scan interface. nTRST input need to be tied LOW permanently in case of non-usage of boundary scan interface.

Note: For resetting the device it is not necessary to have a clock on TCK.

Reset action is given below:

1 .Select system mode for there won't be any interception of boundary scan chain cellsat any of the signals passing between core and external system.

2. Selection of IDCODE instruction. On putting TAP controller into the Shift-DR state, TCK is pulsed and ID register contents will clock out of TDO.

Chapter 3 Interfacing GSM With ARM Micro Controller

3.1 Introduction to AT commands

It is to control modem that AT commands are used and they are instructions. Attention is abbreviated as AT. It is with 'at' or 'AT' that every command line begins and hence the name AT commands for modem commands. Most commands used to control various kinds of modems like ATA (Answer), ATO (Return to online data state), ATD (Dial) and ATH (Hook control) are supported by GPRS/GSMmobile phones and GPRS/GSMmodems. Specific AT commands set to GSM technology is also supported by mobile phones and GPRS/GSM modems and this includes commands related to SMS like AT+CMSS (Send SMS message from storage), AT+CMGS (Send SMS message), AT+CMGR (Read SMS messages) and AT+CMGL (List SMS messages).

It is to be noted that prefix "AT" provides modem with information about a command lines start and is not a part of AT command name. For example, In ATD, D is the actual AT command name and in AT+CMGS it is +CMGS. However, in some websites and books these can be found to be used as AT command name and otherwise. With a mobile phone or GPRS/GSMmodem following tasks can be performed using AT commandsGPRS/GSM:

Basic information about GPRS/GSMmodem or the mobile phone: For example, model number (AT+CGMM), name of manufacturer (AT+CGMI), software version (AT+CGMR) and IMEI number (International Mobile Equipment Identity) (AT+CGSN).

Basic subscriber information about the subscriber: For example, IMSI number (International Mobile Subscriber Identity) (AT+CIMI) and MSISDN (AT+CNUM).

Current status of GPRS/GSM modem or the mobile phone: For example, mobile network registration status (AT+CREG), mobile phone activity status (AT+CPAS), battery charge level and battery charging status (AT+CBC) and radio signal strength (AT+CSQ).

Establish voice connection or a data connection to a remote modem (ATD, ATA, etc.).

Receive and send fax (ATD, ATA, AT+F*).

Read (AT+CMGR, AT+CMGL), send (AT+CMGS, AT+CMSS), delete (AT+CMGD) SMS messages, write (AT+CMGW) SMS messages and obtain newly received SMS messages notifications (AT+CNMI).

Write (AT+CPBW), read (AT+CPBR) or search (AT+CPBF) phonebook entries.

Perform tasks related to security like closing or opening facility locks (AT+CLCK), changing passwords (AT+CPWD) and checking whether a facility is locked (AT+CLCK.

Examples of facility lock: PH-SIM lock [where it is to the mobile phone that a certain SIM card is associated] and SIM lock [where a password is to be typed to SIMcard every time you want to switch the phone on. If a new SIM card is to be used you will have to enter the password].

Control the error messages or result codes of AT commands. It is for you to decide whether certain error messages (AT+CMEE) is to be enables or displayed in verbose or numeric format (AT+CMEE=1 or AT+CMEE=2).

Changing or getting GPRS/GSMmodem or the mobile phone configurations GPRS/GSM. For example, change the bearer service type (AT+CBST), GSM network (AT+COPS), radio link protocol parameters (AT+CRLP), storage of SMS messages (AT+CPMS) and SMS centre address (AT+CSCA).

Configurations restore or saving of GPRS/GSMmodem or of the mobile phone GPRS/GSM. For example, restore (AT+CRES) and save (AT+CSAS) SMS messaging settings like address of SMS centre.

It is to be kept in mind that all AT commands, parameter values and command parameters are not implemented by manufacturers of mobile phones. ,. Also, it is not necessary that the implemented AT commands behave in accordance with standard definition. In general, than ordinary mobile phones it is GPRS/GSMmodems that are specially intended for wireless applications that support AT commands better. .

For some AT commands support is necessary from operators of mobile networks. Some GPRS modems and GPRS mobile phones allow enabling of SMS over GPRS with the +CGSMS command (command name in text: Select Service for MO SMS Messages). But with the absence of support from mobile operator for SMS transmission over GPRS, this feature is of no use.

Conclusion

In this project I come to learn more about the arm processor lPC 2106. While doing this project I come to know the reason of using the arm controller. Basically arm controller is widely used in the today world because of its speed .AT commands which are most important commands in the project. In this project I came to learn various things concerning the arm processor IPC 2106.While working on this project I found out the reasons for using this device and it is widely used because of its speed in today's world. The commands are the most important features of this projects especially the AT command.

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