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In electronics, an integrated circuit is a miniaturized electronic circuit consisting mainly of semiconductor devices, as well as passive components that has been manufactured in the surface of a thin substrate of semiconductor material. Integrated circuits are used in almost all electronic equipment in use today and have revolutionized the world of electronics. Complementary metal-oxide-semiconductor (CMOS) is a major class of integrated circuit and CMOS tecnology is used for a vide variety of analog applications. Throughout this lab session and simulation, the fundamental of MOS chip fabrication is examined. The following discussion will concentrate on introduction of MOS device processing.
2.1 fundamentals of MOS chip fabrication
Figure 1: Simplified process sequence for fabrication of n-well CMOS integrated circuit
2.1.1 Formation of n-well region for pMOS transistor
The fabrication process starts with the well implant and drive in the n-well CMOS inverter to create n-well regions for pMOS transistors in CMOS integrated circuit through impurity implantation onto the substrate, p+ implant.
Figure 2: Formation of active region in n-well CMOS inverter window in the mask (a) and cross section (b).
2.1.2 P+ implant and mask for Field Oxide growth
Then a thick field oxide is growth in the regions surrounding the nMOS and pMOS active regions. Silicon dioxide is patterning through optical lithography process. Optical lithography, also known as Photolithography is a process used in microfabrication to selectively remove parts of a thin film or the bulk of a substrate. Light is used to transfer a geometric pattern from a photomask to a light-sensitive chemical named as photoresist, on the substrate. A series of chemical treatments then engraves the exposure pattern into the material underneath the photoresist. In a complex integrated circuit, for example, modern CMOS, a wafer will go through the photolithographic cycle up to 50 times
Basic procedures of photolithography process start with:
a) Cleaning process:
The cleaning process is used to remove organic or inorganic contaminations that present on the wafer surface. These contaminations are usually removed by wet chemical treatment, e.g. the RCA clean procedure based on solutions containing hydrogen peroxide.
Initially the wafer is heated to a temperature sufficient to drive off moisture that present on the wafer surface. Wafers that have been in storage are chemically cleaned to remove contamination. A liquid or gaseous "adhesion promoter", such as Bis (trimethylsilyl) amine ("hexamethyldisilazane", HMDS), is applied to promote adhesion of the photoresist to the wafer.
c) Photoresists application
The wafer is then covered with photoresist by spin coating. A viscous, liquid solution of photoresist is dispensed onto the wafer, and the wafer is spun rapidly to produce a uniformly thick layer. The spincoating process results in an uniform thin layer of photoresist on top of the wafer. The photoresist-coated wafer is then heated to drive off excess solvent, typically at 90 to 100 Â°C for 5 to 30 minutes in an oven or for 30 to 60 seconds on a hotplate. Sometimes a nitrogen atmosphere is used.
d) Exposure and developing
After heating, the photoresist is exposed to a pattern of intense ultraviolet light. Positive photoresist is soluble in the basic developer when exposed while negative photoresist is insoluble in the developer. The resulting wafer is then heated again, typically at 120 to 180 Â°C for 20 to 30 minutes to solidifies the remaining photoresist and make it more durable protecting layer in future ion implantation, wet chemical etching, or plasma etching.
In etching, a liquid or plasma chemical agent is used to remove the uppermost layer of the substrate in the areas that are not protected by photoresist. Dry etching techniques are generally used to avoid significant undercutting of the photoresist pattern. This is essential when the width of the features to be defined is similar to or less than the thickness of the material being etched. Wet etch processes are generally used in indispensable microelectromechanical systems, where suspended structures must be free from the underlying layer.
d) Photoresists removal
The photoresist must be removed from the substrate by a liquid, resist stripper, which chemically alters the resist so that it no longer adheres to the substrate. Alternatively, photoresist can also be removed by ashing using a plasma containing oxygen, through oxidization process.
Figure 3: Patterning silicon dioxide
2.1.3 Formation of gate, drain and source junctions
Thick silicon dioxide layer, field oxide is created on the surface of wafer. Next the field oxide is selectively etched to expose the silicon surface on which the MOS transistor will be created. On top of the thin oxide, a layer of polysilicon is patterned and etched to form the interconnect MOS transistor gates. The thin gate oxide not covered by polysilicon is etched away too in order to expose the bare silicon surface where source and drain junctions are to be formed. The entire surface is then doped with high concentration of impurities creating two n-type regions, source and drain junctions.
2.1.4 Create contact windows
Once the source and drain regions are completed, the entire surface is covered by insulating material of silicon dioxide in order to provide contact window for the drain and source junctions. The surface is covered with aluminum to form interconnects, patterned and etched a metal to complete the interconnection if the MOS transistors on the surface
2.2.1. Silvaco TCAD
Silvaco TCAD utilize SSuprem3, a general purpose one-dimensional (1D) process simulator used in the prediction of doping profiles and layer thicknesses produced by semiconductor processing. SSuprem3 is accurate, extremely fast and user friendly. It is able to simulate a complete flow of process steps in a matter of minutes. SSuprem3 can run interactively under DeckBuild for editing process simulation input files and under TonyPlot for graphics and post-processing. SSuprem3 provides interfaces to device simulators that enable simulated profiles to be input for device level simulation. SSuprem3 uses a built-in electrical solver to extract threshold voltages.
3.0 Simulation results
Effect of different influent factors on NMOS structure and Ids/Vgs curve
3.1 Effects of well concentration
3.1.1 Well concentration = 8e10 cm-3
3.1.2 Well concentration = 8e14 cm-3
At doping concentration of 8e10 cm-3, it is lower than the default doping concentration 8e12cm-3. Doping concentration is proportional to drain resistances. Thus, in doping concentration of 8e10cm-3 give lower drain resistances, thus more Id can flow through the junctions. Doping concentration of 8e14 give larger drain resistances, thus less drain current flow through the junctions.
3.2 Effects of Source/ Drain concentration
3.2.1 Source/ Drain concentration = 5e12 cm-3
3.2.2 Source/ Drain concentration = 8e17 cm-3
Source and drain concentration is propotional to drain current. The higher doping intensity of source and drain junction, the more ready carriers available to give larger current flow. Thus, one can view from the graph that 8e17 source and drain concentration give largest current flow while 5e14 source and drain concentration is the lowest among all, give lowest drain current.
3.3 Effects of rapid thermal annealing temperature
Theorically when we increase the temperature, the carriers gain more energy thus it will collide more with the carriers in the surrouding. A rapidly moving carriers conduct more current thus result in larger Id current. Thus from the graph above, the 1000Â°C which is the highest among all, gives largest drain current.
3.4 Effects of threshold voltage adjust implant concentration
3.4.1 Vt Adjust Concentration = 9.5e10 cm-3
3.4.2 Vt Adjust Concentration = 9.5e12 cm-3
When the Threshold Voltage Adjust Concentration is increased, the threshold voltage increases as well. Thus more carriers are required to turn on the MOS devices. We can see from the graph, 9.5e12 gives the highest Threshold Voltage Adjust Concentration, means its threshold voltage also increased. This at approximately 2V, Id increase rapidly which imply the MOS device is on. Comparison to default 9.5e11 and 9.5e10, they have lower threshold voltage.
Complementary-metal-oxide-semiconductor (CMOS) devices have been a key driving force behind the explosive growth of various network centric computing products such as ASIC high-speed microprocessors and memories, low power hand-held computing devices and advanced multi-media audio and video devices.
It is well known that as the contact area decreases, contact resistance increases, and as the active semiconductor dopant level at the contact surface increases, contact resistance between a metal or other contact layer and the semiconductor decrease.
The source/drain (S/D) implants are performed then annealed at a high temperature (e.g. >950 C) to achieve a high percentage of active dopant relative to the chemical dopant provided, such as at least 30% for both the n+ and p+ regions.
An integrated circuit (IC) includes a semiconductor substrate, a least one MOS transistor formed in or on the substrate, the MOS transistor including a source and drain doped with a first dopant type having a channel region of a second dopant type interposed between, and a gate electrode and a gate insulator over the channel region. A silicide layer forming a low resistance contact is at an interface region at a surface portion of the source and drain. At the interface region a chemical concentration of the first dopant is at least 5Ã-1020 cmâˆ’3. Silicide interfaces according to the invention generally provide MOS transistor with low silicide interface resistance, low pipe density, with an acceptably small impact on short channel behavior.
For NMOS, the first dopant type can be n-type, such as As or P. For PMOS, the first dopant type can be p-type, such as boron. In one embodiment, the chemical concentration of the first dopant is >1Ã-1021 cmâˆ’3.
A method of forming a MOS transistor comprises the steps of providing a semiconductor substrate, forming a gate electrode over a gate insulator, forming a source and drain by implanting a first S/D implant of a first dopant type, the source and drain being separated by a channel region of a second dopant type having the gate electrode and the gate insulator thereon. A second S/D implant of the first dopant is implanted into a surface portion of the source and drain. Annealing the first and second S/D implants follows.
In this experiment, the characteristic of NMOS I-V curve under different influent factors can be concluded as below:
When the Well Concentration increased, the threshold voltage increases.
When the Source/Drain Concentration increased, the threshold voltage decreases.
When the annealing temperature increased, the threshold voltage remains the same.
When the Threshold Voltage Adjust Implant Concentration increased, the threshold voltage increases.
FACULTY OF ENGINEERING
Processing and Fabrication Technology
TRIMESTER 3 (2008-2009)
PFT1 - NMOS Processing Simulation
Name : Chin Yin Yee
ID : 1051100722
Group : 1.9
Lecturer : Mr. Chan Kah Yoong