Model Based Designing Analog Circuits Using Simulink Computer Science Essay

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This paper applies embedding knowledge into model based design method, an efficient and cost-effective way to develop embedded systems. The approach is based on a single design description in the graphical Matlab/Simulink environment that is used for FPGA emulation, ASIC design, verification and chip testing. This simulation-based approach gives a better understanding of design alternatives and trade-offs than traditional prototype-based design methodologies. It enables to optimize design to meet predefined performance criteria. The methodology is tested for designing CMOS inverter and the simulation results confirm the efficiency of presented methodology.

Traditional approaches to implement embedded system design on FPGA and ASIC involves gathering requirements using visual representations or word processors, creating design using various tools like MATLAB ®[8] , C, C++.and generating HDL code, verifying and testing the design . The translation phase is manual and is prone to introduction of human errors. Each translation step, whether manual or automated, requires additional verification to confirm that the original design has been preserved[2]. It is proposed to use Simulink to model, simulate, and analyze dynamic systems because it is familiar to system designers and provides graphical user interface (GUI) for building models as block diagrams. Chip design verification in the manufacturing process has to be conducted in the early stages to eliminate logic errors and thereby reducing costly respins[9]. Logic verification using simulation software may not be the right choice as this process may be extremely slow. In comparison to that Hardware emulation is multiple times faster than software based emulation.

FPGAs - Field Programmable Gate Arrays - are hardware emulation boards that allow good level of customization of the hardware at affordable prices. Using FPGA results in reducing costs and also time to market ratio. A time consuming and expensive redesign of a board can often be avoided through with the use of FPGA [1].

In today's world VCO is one of the major building bock of the many communication systems such as Mobile communication PLL-Phase Lock Loop, Clock generator, etc. The designing a VCO with reduced area meting the all the target the specification is a major challenge . The VCO can be broadly categories as Ring Oscillator and LC oscillator. Ring Oscillator is attractive option due its simplicity and design flexibility. The CMOs Inverter is the basic building block of the ring Oscillator circuit rather it is the basic building block of many CMOS logic circuits since it. provides quick transition time, high buffer margins, and low power dissipation: all three of these are desired qualities in inverters for most circuit design. The Structural Partitioned Hierarchical Blocks of the Ring Oscillator as shown in the figure 1. The ring oscillator is designed using N CMOS inverter stages.

In this paper model based design method is demonstrated using an example of CMOS inverter as a test vehicle. The remainder of the paper is organized as follows. In Section 2, the basic of linear system theory is applied to CMOS devices to motivate our approach. Section 3 explains Model based design approach using Simulink HDL coder to design and verify electronic circuit. In section 4, the actual CMOS inverter model using Matlab/Simulink is explained. Section 5, describes the obtained experimental results.

Figure 1. The Structural Partitioned Hierarchical Blocks of the Ring Oscillator


The figure 2 shows the circuit diagram of a static CMOS inverter [4].

Figure 2. The circuit diagram of a static CMOS inverter

The inverter operates in the saturation region saturation, linear and cut off mode , there is a transition from low to high or high to low stat of the output with respect to input. When the input of an inverter switches from low (Vin=0) to high ( V in = VDD), the capacitor discharges through the NMOS transistor. When the input of an inverter switches from high to low, the capacitor charges through the PMOS transistor..[10] The propagation delay occurs when output voltage switches from high to low and low to high and the corresponding delay and the threshold voltage is calculated by the following equation listed below[4] [5]. The propagation delay time can be reduced by reducing the value of CL or increasing the value of and






= propagation delay time for transition from Low to High

=propagation delay time for transition from High to Low = capacitive load

=Threshold voltage for PMOS

= Threshold voltage for NMOS

=Transconductance for PMOS ,NMOs respectively

== Aspect ratio


The flowchart of the design methodology for automation process using Simulink HDL Coder, from modeling to FPGA and ASIC implementation, areas as shown in figure 3 [3].

The HDL Workflow Advisor is an alternative method to generate HDL code. Simulink HDL Coder enables to quickly implement Simulink model in Xilinx® and Altera® FPGAs. The HDL Workflow Advisor is a GUI tool that supports and integrates all stages of the FPGA design process, including the following: Checking the Simulink model for HDL code generation compatibility, Generating RTL code, an RTL test bench, and a cosimulation model forming synthesis and timing analysis through integration with Xilinx ISE® and Altera II Providing a resource estimation report and guidance on modifying the model to achieve design constraints. The advantage of this is back annotation of the Simulink model with critical path and other information obtained during synthesis process.

The coder generates VHDL or Verilog code that implements the design embodied in the model. Usually, a corresponding test bench also can be generated. The test bench with HDL simulation tools can be used to drive the generated HDL code and evaluate its behaviour. The coder generates scripts that automate the process of compiling and simulating code.. EDA Simulator Link™ MQ, EDA Simulator Link IN or EDA Simulator Link DS software can

Figure 3. The flowchart of the design methodology using Simlink HDL coder

be used from the MathWorks™ to cosimulate generated HDL entities within a Simulink model.

The test bench feature increases confidence in the correctness of the generated code and saves time spent on test bench implementation. The design and test process is fully iterative. At any point, the designer can return to the original model, make modifications, and regenerate code. When the design and test phases of the project have been completed, easily the generated HDL code can be exported to synthesis and layout tools for hardware realization. The coder generates synthesis scripts for the Synplify® family of synthesis tools. The procedure followed to obtain VHDL netlists that can be downloaded to FPGA boards. The HDL Workflow Advisor is an alternative method to generate HDL code


The proposed idea is implemented using a MATLAB-Simulink toolbox for the simulation and synthesis of CMOS inverter. The Graphical User Interface (GUI) included in the toolbox allows to navigate easily through all steps of the simulation, synthesis and post-processing of results. The LEVEL 3 spice models are used for MOS. Figure 4 shows CMOS Inverter model using Simulink and Spice compatible components from Simelectronics.

Figure 4. CMOS Inverter model implemented using Simulink

By using this GUI, the user can either open an existing modeler create a new one in the SIMULINK platform. After running simulation, different Voltage transfer characteristics are obtained by changing the value of W and L of PMOS and NMOS transistors. The input and output waveforms can be seen on the scope component.


The one of the results listed is shown in the figure5.The transfer characteristics transfer curve for different values of λ is shown in the figure6. The switching speed due to change of the load is shown in the figure 7.

From the obtained results it can seen that, If there λ is decreased the transition region shifts from left to right however, output voltage transition remains sharp. The switching speed of CMOS transistor is limited by time taken to charge and discharge the load capacitance CL ,the output waveform is shown in the Figure 8 .The effect of change in load on propagation delay is plotted in Figure 9 with λ =1and the relative comparative results are listed in table1.

The relative error observed in the comparative results is can be neglected since the formulae used for calculation are always approximate and the variation of empirical constants parameter changes as per the model whereas in Simulink for this work LEVEL3 MOS models are used.

Figure 5. The input and output waveform: Simulink scope


Figure 6. The transfer characteristics curve for different values of λ with load CL=50pf

Figure7.The transfer characteristics curve for different values of load with λ =1

Table 1 The comparative results of Propagation delay

Capacitive Load



% error

10 pF




20 pF

180 ns

200 ns


30 pF

248 ns

300 ns


40 pF

300 ns

400 ns


Figure 8. The input and output waveform with capacitive load

Figure9. The effect of change in load on propagation delay with λ =1


A practical CAD Model based design (MBD) methodology for CMOS inverters presented in this paper. The obtained experimental results shows that Simulink can be used as a platform for MBD .The proposed algorithm can be used for implementing analog circuit design on FPGA using HDL coder. Using this algorithm, the HDL codes can be automatically generated from Simulink models for analog circuit design. Continuous verification can be achieved via processor-in the- loop, hardware-in-the-loop or co-simulation. Therefore by using the suggested methodology all development phases can be simulated and verified and implemented under one roof rather than actually doing them separately which saves time and costs effectively.

In future we propose to design VCO using CMOS inverter and implementing same on FPGA using HDL coder.