This essay has been submitted by a student. This is not an example of the work written by our professional essay writers.
A microprocessor includes almost all of the functions of a computer's central processing unit (CPU) on a single integrated circuit (IC).The basic steps include
The key element of all computers, providing the mathematical and decision making ability
Current state-of-the-art uPs (Pentium, Athlon, SPARC, PowerPC) contain complex circuits consisting of tens of millions of transistors
They operate at ultra-fast speeds - doing over a billion operations very second
Made up from a semiconductor, Silicon
A microprocessor, sometimes called a logic chip, is a computer processor on a microchip. The microprocessor contains all or most of, the central processing unit functions and is the engine that goes into motion when you turn your computer on. A microprocessor is designed to perform arithmetic and logic operations that make use of small number-holding areas called registers. Typical microprocessor operations include adding, subtracting, comparing two numbers, and fetching numbers from one area to another. These operations are the result of a set of instructions that is part of the microprocessor design. When your computer is turned on, the microprocessor gets the first instruction from the basic input/output system that comes with the computer as part of its memory. After that, either the BIOS, or the operating system that BIOS loads into computer memory, or an application program is driving the microprocessor, giving it instructions to perform.
Computer processors were for a long period constructed out of small and medium-scale ICs containing the equivalent of a few to a few hundred transistors. The integration of the whole CPU onto a single chip therefore greatly reduced the cost of processing capacity. From their humble beginnings, continued increases in microprocessor capacity have rendered other forms of computers almost completely obsolete (see history of computing hardware), with one or more microprocessor as processing element in everything from the smallest embedded systems and handheld devices to the largest mainframes and supercomputers.
Its various sub-systems include:
Bus interface unit]
Data & instruction cache memory
Commonly known as an IC or a chip
A tiny piece of Silicon that has several electronic parts on it
Most of the size of an IC comes form the pins and packaging; the actual Silicon occupies a very small piece of the volume
The smallest components on an IC are much smaller than the thickness of a human hair basically like these components:Â-
How microprocessor works
To understand how a microprocessor works, it is helpful to look inside and learn about the logic used to create one. In the process you can also learn about assembly language -- the native language of a microprocessor -- and many of the things that engineers can do to boost the speed of a processor.
A microprocessor executes a collection of machine instructions that tell the processor what to do. Based on the instructions, a microprocessor does three basic things:
Using its ALU (Arithmetic/Logic Unit), a microprocessor can perform mathematical operations like addition, subtraction, multiplication and division. Modern microprocessors contain complete floating point processors that can perform extremely sophisticated operations on large floating point numbers.
A microprocessor can move data from one memory location to another.
A microprocessor can make decisions and jump to a new set of instructions based on those decisions.
There may be very sophisticated things that a microprocessor does, but those are its three basic activities. The following diagram shows an extremely simple microprocessor capable of doing those three things:
This is about as simple as a microprocessor gets. This microprocessor has:
An address bus (that may be 8, 16 or 32 bits wide) that sends an address to memory
A data bus (that may be 8, 16 or 32 bits wide) that can send data to memory or receive data from memory
An RD (read) and WR (write) line to tell the memory whether it wants to set or get the addressed location
A clock line that lets a clock pulse sequence the processor
A reset line that resets the program counter to zero (or whatever) and restarts execution
Let's assume that both the address and data buses are 8 bits wide in this example.
Here are the components of this simple microprocessor:
Registers A, B and C are simply latches made out of flip-flops. (See the section on "edge-triggered latches" in How Boolean Logic Works for details.)
The address latch is just like registers A, B and C.
The program counter is a latch with the extra ability to increment by 1 when told to do so, and also to reset to zero when told to do so.
The ALU could be as simple as an 8-bit adder (see the section on adders in How Boolean Logic Works for details), or it might be able to add, subtract, multiply and divide 8-bit values. Let's assume the latter here.
The test register is a special latch that can hold values from comparisons performed in the ALU. An ALU can normally compare two numbers and determine if they are equal, if one is greater than the other, etc. The test register can also normally hold a carry bit from the last stage of the adder. It stores these values in flip-flops and then the instruction decoder can use the values to make decisions.
There are six boxes marked "3-State" in the diagram. These are tri-state buffers. A tri-state buffer can pass a 1, a 0 or it can essentially disconnect its output (imagine a switch that totally disconnects the output line from the wire that the output is heading toward). A tri-state buffer allows multiple outputs to connect to a wire, but only one of them to actually drive a 1 or a 0 onto the line.
The instruction register and instruction decoder are responsible for controlling all of the other components.
Although they are not shown in this diagram, there would be control lines from the instruction decoder that would:
Tell the A register to latch the value currently on the data bus
Tell the B register to latch the value currently on the data bus
Tell the C register to latch the value currently output by the ALU
Tell the program counter register to latch the value currently on the data bus
Tell the address register to latch the value currently on the data bus
Tell the instruction register to latch the value currently on the data bus
Tell the program counter to increment
Tell the program counter to reset to zero
Activate any of the six tri-state buffers (six separate lines)
Tell the ALU what operation to perform
Tell the test register to latch the ALU's test bits
Activate the RD line
Activate the WR line
Coming into the instruction decoder are the bits from the test register and the clock line, as well as the bits from the instruction register.
Application of Microprocessor:-
Eighteen months ago, we started the analysis of a mathematical problem which was selected as the target application for the first fully automated ASIC development of the IIIE (Institute de Investigations en Ingeniería Electrical). The PWL (Piece Wise Linear) Function Computation problem was chosen because this kind of function allows the representation of n-dimensional non-linear functions in a convenient way for computing systems, and non-linear functions are of relevance in control systems, one of the most active areas at the IIIE. After defining and analyzing the computation algorithm, we concluded that a special microprocessor architecture was the most appropriate approach for this ASIC; the programming capability of this design included the flexibility required for PWL computations of 2 to 6 dimensional functions and the dedicated hardware structures provided the required performance. Also, the challenge of developing a microprocessor was an extra motivation for the design team. The next step was the implementation of the design; it was done using a top down design flow where Synopsys' tools played the major role. After 12 months of design and implementation we sent the PWL uP's layout to MOSIS. Today, after the testing procedure, we have our PWL u-P working properly in a first pass success.
Working with Synopsys' tools was quite successful as well as challenging. The process that started with the installation of the software, continued with being a user from scratch and ended when we obtained what we wanted, was a valuable experience in electronic design automation. The RTL level description was written in VHDL. Obviously, logic synthesis was done using Design Compiler. Due to the importance of this step we will dedicate the next section to describe this particular
Experience. For simulations of RTL and Design Compiler output's Gate Level description we opted for Mentor's Models due to our long experience with it. We actually didn't know about VCS. While simulating the Gate Level we detected some errors in the digital specification. Finding these errors was not an easy task; we had to simulate many times until we were able to identify what was failing. Of course, if we had known the capabilities that Formality provides we could have worked faster. But that didn't happened until the PWL u-P was ready for tape out, a little late but to be taken into account. Since IC Compiler was not yet available for universities, physical synthesis was done using Cadence's tools. For our next development we will do the placement and routing with IC Compiler and we will certainly compare it against Encounter.
Intel MCS-4 4-B Chip Set
Although Intel began as a memory chip company , in 1969 we took on a project for Busicom of Japan to design eight custom LSI chips for a desktop calculator. Each custom chip had a specialized function -keyboard, printer, display, serial arithmetic, control, etc. With only two designers, Intel didn't have the manpower to do that many custom chips. We needed to solve their problems with fewer chip designs. Ted Hoff chose a programmed computer solution using only one complex logic chip (CPU) and two memory chips; memory chips are repetitive and easier to design. Intel was a memory chip company, so we found a way to solve our problem using memory chips!Â
ROM Chip (4001)
Conventional calculators utilized specialized custom chips for keyboard, display, and printer control. With the MCS-4 all control logic is done in firmware, program stored in ROM . A single ROM chip design is customized (with a mask during chip manufacturing) for a customer's particular program. The CPU's 12-b Program Counter addresses up to 16 ROM chips. Simple applications use only one ROM chip; the desktop calculator used four. The same chip mask also configured each ROM port bit as an input or output.
RAM Chip (4002)
Calculators need to hold several 16-digit decimal floating-point numbers. We organized the RAM accordingly, and ended up with a 20-digit word (80 b):
16 digits for the fraction
2 digits for the exponent
2 digits for signs and control
20 digits x 4 b/digitThe RAM chip stored four 80-b numbers and additionally the chip had an output port. The use of three-transistor dynamic memory cells made the RAM chip feasible . A built-in refresh counter was used to maintain data integrity. Refresh took place during instruction fetch cycles, when the RAM data was not being accessed. Dynamic RAM memory cells were also used inside the CPU for the 64-b index register array and 48-b Program counter/stack array. Intel expertise in dynamic memory was an enabling factor for he MCS-4!
To conserve chip count and to utilize existing power/clock pins, the 16-pin ROM and RAM chips also had integrated 4-b ports for direct connection of I/O devices. To activate an output, a program selected a particular RAM/ROM chip (using an index register) and sent 4-b of Accumulator data from the CPU to the selected output port. In the desk calculator application, the display, keyboard, and printer were connected to these ports. Keyboard scanning, decoding, and debouncing  were all done under program control of the I/O ports; all printer and display refresh was done in firmware . A small shift register (4003) was used for output port expansion. External transistors and diodes were used for amplification and isolation.
Microprocessor -CPU Chip (4004)
In the calculator application, each user key stroke caused thousands of CPU instructions to be executed from ROM. We wrote many subroutines which operated on 16-digit numbers stored in RAM. As an example, a 10-byte loop for digit serial addition took about 80 Âµs/digit (similar speed as IBM 1620 computer sold in 1960 for $100 000). In this add routine a CPU index register would address each of the 16 digits stored in the RAM memory. The program would bring in one digit at a time into the CPU's accumulator register to do arithmetic. A Decrement and Jump instruction was used to index to the next RAM location.
Distributed Logic Architecture
The time division multiplexing of the 4-b bus, the on-chip dynamic RAM memories, and the CPU's address stack are the highlights of the MCS-4 architecture. However, there is another interesting feature -distributed decoding of instructions. The ROM/RAM chips watched the bus, and locally decoded port instructions, as they were sent from the ROM. This eliminated the need for the CPU to have separate signal lines to the I/O ports, and also saved CPU logic. This is not a feature used in conventional computers.
The smallest system would contain two chips -a CPU and a ROM. A typical calculator had 4 ROM's and a RAM chip with five I/O ports, (20) wires for connecting peripheral devices. A fully loaded system could have 16 ROM and 16 RAM chips, and obviously a plethora of I/O ports. Typical applications included:Â Busicom of Japan produced several calculator models using the MCS-4 chip set. Ted Hoff and I made the original proposal for the MCS-4 and did the feasibility study for the first calculator. Federico Faggin did all of the logic and circuit design and implemented the layout; Busicom's M. Shima wrote most of Busicom's firmware. (Later Shima joined Intel as the 8080 designer.) The Intel patent on the MCS-4 (Hoff, Faggin, Mazor) has 17 claims, but the single chip processor is not claimed as an invention.
INTEL 8008 MICROPROCESSORÂ
Intel made a custom 512-b shift register memory chip  for use in (their customer) Datapoint's low cost bit-serial computer. This 8-b CPU, implemented with TTL MSI, had around 50 data processing instructions. In response to their inquiry about an 8 x 16 stack chip, and based upon our progress with the MCS-4, I proposed an 8-b parallel single chip CPU in 12/69 . This custom chip design was never used by Datapoint, and it became a standard Intel product, which marketing dubbed the 8008 (twice 4004!).
Â Although the arithmetic unit and registers were twice as large as in the MCS-4, we expected that the control logic could be about the same if we deleted a few Datapoint defined instructions. Unlike the MCS4's two-memory address space, the 8008 had one memory address space for program and data . The symmetric and regular instruction set was attractive. However, the only memory addressing was indirect through the High-Low (HL) register pair. Today's computers have huge amounts of memory, and a plethora of memory addressing instructions.Â
Though the term "microprocessor" has traditionally referred to a single- or multi-chip CPU or system-on-a-chip (SoC), several types of specialized processing devices have followed from the technology. The most common examples are microcontrollers, digital signal processors (DSP) and graphics processing units (GPU). Many examples of these are either not programmable, or have limited programming facilities. For example, in general GPUs through the 1990s were mostly non-programmable and have only recently gained limited facilities like programmable vertex shaders. There is no universal consensus on what defines a "microprocessor", but it is usually safe to assume that the term refers to a general-purpose CPU of some sort and not a special-purpose processor unless specifically noted.
Microprocessor in future
Microprocessors in future used in aerospace systems.
Cell is a microprocessor architecture jointly developed by Sony Computer Entertainment, Toshiba, and IBM, an alliance known as "STI". The architectural design and first implementation were carried out at the STI Design Center in Austin, Texas over a four-year period beginning March 2001 on a budget reported by Sony as approaching US$ 400 million. Cell is shorthand for Cell Broadband Engine Architecture, commonly abbreviated CBEA in full or Cell BE in part. Cell combines a general-purpose Power Architecture core of modest performance with streamlined coprocessing elements which greatly accelerate multimedia and vector processing applications, as well as many other forms of dedicated computation.
The first major commercial application of Cell was in Sony's PlayStation 3 game console. Mercury Computer Systems has a dual Cell server, a dual Cell blade configuration, a rugged computer, and a PCI Express accelerator board available in different stages of production. Toshiba has announced plans to incorporate Cell in high definition television sets. Exotic features such as the XDR memory subsystem and coherent Element Interconnect Bus (EIB) interconnect appear to position Cell for future applications in the supercomputing space to exploit the Cell processor's prowess in floating point kernels. IBM has announced plans to incorporate Cell processors as add-on cards into IBM System z9 mainframes, to enable them to be used as servers for MMORPGs.
Integrated circuit technology has been evolving in a predictable manner for the past 30 years. Although a computer on a chip was eventually realizable, it was problematical how to use LSI chips which had fewer than 20 000 transistors. Most of the work focused on partitioning 16-b computers into multiple chips, but few of these projects were successful. Early Intel microprocessors succeeded because they were scaled down computers. Like a golf cart, they were very limited, "but got across the green." When the densities reached 200 k+ transistors per chip, microprocessors became the dominant computer technology