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Radio Frequency Identification is generic term for technology employing radio waves for detecting objects. RFID has wide application in payment systems, access control, asset tracking and other areas as many companies are using and developing the technology's potential. As RFID develops, it imports some new elements, one of which is Java technology. Java now can be seen in any links from RFID tags to database centre. But the performance of Java is still a main concern to us. This paper shows a good solution to deal with the efficiency problem when using Java technology in RFID systems.
It firstly introduces advantages of Java processor. It can highly increase the performance of processing Java applications by implementing the technology in ASIC. After introducing some Java processors both for research and commercial, this paper leads us to the newly developed Java processor VP6K. Then details of functions and performance about the VP6K core and chip will be discussed. This paper also provides a hardware verifying platform for VP6K processor, in order to show cases of applications. Test results will be listed. In the end, this paper comes to the conclusion that VP6K is a high performance Java-specific processor, and further research plan will be made.
Keywords-Radio Frequency Identification (RFID), Java processor, System-on-Chip (SoC), Java Virtual Machine (JVM), Reduced Instruction Set Computing (RISC)
RFID plays such an important role as a major component in logistics, storing, management, medicine, computing, etc. It is considered to be a key to automating everything all around the world. Nowadays, RFID and Wireless Sensor Networks (WSN) are widely used in pervasive computing environment. This high-value technique can be applied in so many areas including asset tracking, real-time supply chain management and telemetry based remote monitoring. RFID has its long history compared to other hot techniques. Little story about RFID is that it was used to distinguish enemy planes from allied planes through the use of radar in World War II by the army. RFID and
Final manuscript received data: April 7, 2010.
This work is supported by Guangzhou Key Technology R&D Program (No.2007Z2-D0011), held with Guangzhou Science and Technology Department, China.
Chen Zhirui, born in 1983, Male, is a Ph.D. student of Department of Electronics Engineering, Sun Yat-Sen University, Waihuan Road East 132#, Higher-education Mega Centre, Guangzhou 510006, China. (e-mail: firstname.lastname@example.org)
Wen Xuhua, born in 1986, Male, is an EE MS student of Department of Electronics Engineering, Sun Yat-Sen University, Waihuan Road East 132#, Higher-education Mega Centre, Guangzhou 510006, China. (e-mail: email@example.com)
Tan Hongzhou is a professor in Department of Electronics Engineering, Sun Yat-Sen University, Waihuan Road East 132#, Higher-education Mega Centre, Guangzhou 510006, China. (e-mail: firstname.lastname@example.org)
similar technologies certainly will play a vital role in future with tremendous database infra-structure connecting the world. In recent years, one of the most concerned problem about RFID is security. Using smart card with operating system and upper-layer applications as RFID tag is a well accepted solution.
Java, on the other hand, has something in common with RFID. Java is not only a programming language, but also a widely used technology in the world. The reason why Java technology is developing rapidly since it was "born" in 1995, is that it has great characteristics, such as versatility, efficiency, platform portability, and security. To date, the Java platform has attracted more than 6.5 million software developers. It's used in every major industry segment and has a presence in a wide range of devices, computers, and networks. Java technology's great features make it the ideal technology for network computing from laptops to data centers, game consoles to scientific supercomputers, cell phones to the Internet. One of the most widely used application is Java card, which is also known as smart card for RFID tags.
One of the most important elements of Java technology is JVM, Java Virtual Machine, the middle-ware connecting Java applications and hardware platforms. It is implemented into the Java card. What JVM has to do is to translate Java bytecode, which is compiled from Java source code, into local instruction. Then local instruction is executed on target platform. Each platform has a unique JVM accordingly which can translate the same Java program to different local instruction, so it is clear that the JVM mechanism makes Java "write-once-run-everywhere" possible.
As JVM can be seen as a set of software installed on hardware platforms, the efficiency of code translation should be discussed. While JVM is implemented in a personal computer for example, its performance is pretty good, since gigahertz CPU is in most of PCs nowadays, translation efficiency will not be a problem in such case. Not to mention the performance of JVM in supercomputers. But on the other side, while it is implemented in much smaller equipment such as RFID tag reader, cell phone, etc., the performance may not be satisfying as JVM is such a burden for CPU in embedded devices. As power is the first consideration of chips in mobile device, frequency and performance should make sacrifices, it's all about trade-off.
There is a simple way to deal with the efficiency problem for hand-set devices. Let the hardware replace JVM software part, in order to translate instructions in a way of specific integrated circuits. Such idea is strongly welcomed among the industry. As a result, some Java processors appear to the surface.
Java in rfid
For RFID systems, Java technology can be seen in three different data-flow parts, which are database servers, tag readers and tags. As Java used in RFID database is implemented in high performance server clusters, which conform to the J2EE standard. In this case, Java used in RFID database is out of our discussion in this paper. We mainly focus on the other two applications, tag readers and tags (Java cards or Smart cards).
RFID tag is a small device consisting of an integrated circuit or called chip, working with an antenna. It is so small, like a sand, that can be easily implemented into any object or living creature for tracking and identification by storing and reading ID information or data inside the sand-size chip. Some tags are designed for specific application area. For example, implantable RFID tags are specially designed tags which can be implanted into human body by inserting into hands, legs or behind the neck or any other suitable organs of body. These tags are carrying identity of person in a unique form. Just like an ID card storing information of the person. Only difference is that these implantable tag is inside one's body instead of held in hand. All information contained in the RFID tag is encrypted by types of standards.
Java card technology is proposed by Sun Microsystem Inc., which has already been acquisitioned by Oracle. This technology enables smart cards and other devices with very limited memory to run small applications, called applets, that employ Java technology. It provides smart card manufacturers with a secure and interoperable execution platform that can store and update multiple applications on a single device. Java Card technology is compatible with existing smart card standards. The technology enables developers to build, test, and deploy applications and services rapidly and securely. For an instance, Java card is used for on-off line payment of electronic cash for E-Commerce. The structure of Java card includes a virtual machine mechanism as middle-ware, just like any other Java applications.
An RFID reader's function is to interrogate RFID tags. A reader contains an RF module, which acts as both a transmitter and receiver of radio frequency signals. A microprocessor forms the control unit, which employs an operating system and memory to filter and store the data. If Java applications are employed, reader has to be installed a JVM inside. As a matter of fact, a Java-specified processor combines microprocessor and JVM in one. There are several types of RFID tag reader, like fixed and handheld. A new trend for reader is to be integrated into mobile device as a method for NFC (Near Field Communication).
As it is mentioned before, the efficiency of JVM implemented in embedded system is not satisfying. Developers and vendors are trying hard to find a way to balance the cost and performance when using Java technology in RFID system. As they would not give up the advantages employing Java. It is a great opportunity for showing Java processor or Java core to the industry.
Java processors are primarily used in embedded systems. All the Java processors around the world can be divided into two groups: research projects or commercial chips. Almost all Java processors for research are implemented in FPGA platforms, such as JOP, Moon, Lightfoot, Komodo, FemtoJava. They are some prototypes of Java processors, also the models of commercial ones. On the other hand, much greater performance can be achieved in commercial Java processors, for these processors are implemented in ASICs with higher frequency and advanced process.
Applications of Java processors are concerned by most people, so the following introduction may mainly focus on some of the well-known commercial Java processors.
Jazelle technology is embedded in ARM architecture as a co-processor which executes Java programs exclusively. It is a combined hardware and software solution from ARM. ARM Jazelle technology software is a full featured multi-tasking JVM, highly optimized to take advantage of Jazelle technology architecture extensions available in many ARM processor cores. ARM Jazelle technology hardware extensions are available from over 50 ARM silicon partners.
ARM Jazelle DBX (Direct Bytecode eXecution) technology for direct bytecode execution of Java delivers an unparalleled combination of Java performance and 32-bit embedded RISC architecture. Developers or users can run Java applications alongside established OS, middleware and application code on a single processor.
ARM Jazelle RCT (Runtime Compilation Target) technology supports efficient ahead-of-time (AOT) and just-in-time (JIT) compilation with Java and other execution environments.
The aJile Systems aJ-100 is a family of single-chip microcontrollers that directly execute JVM bytecodes and real-time Java threading primitives to provide real-time performance for low-power embedded applications. The native JVM bytecode implementation eliminates the typical interpreter or JIT software layers and provides the most optimal Java performance in both memory requirements and execution time. In addition, Java threading primitives (wait, yield, notify, monitor enter/exit) are implemented as extended bytecodes eliminating the need for a traditional RTOS as well.
The aJ-100 features on-chip memory and all the I/O functions required for use in many real-time networked embedded applications. The chip can be used in Java based smart-phones, PDAs, wireless gadgets, and real-time networked industrial controllers and sensors.
The Nazomi Communications JA108 Java accelerator chip targets mobile wireless applications, such as 2G/2.5G/3G phones, and it improves Java software execution while extending battery life as a co-processor in the system. The JA108 offloads the microprocessor by taking over the task of executing Java bytecode instructions and thus speeds up Java software execution by 15x to 60x, depending on the application. The chip, which interfaces like a standard SRAM device, is a stand-alone Java Accelerator that can be integrated into new and existing designs on existing memory buses. The JA108 works with any baseband processor, chipset, system on chip (SoC), or microprocessor and is transparent to existing designs and legacy operating systems.
The Patriot Scientific Corporation PSC1000 Microprocessor is an implementation of the ShBoom Microprocessor architecture. It is a 32-bit RISC processor that executes at a peak performance of one instruction per CPU clock cycle. The processor addresses up to four gigabytes of physical memory, and supports virtual memory with the use of external mapping logic. The CPU is designed for use in those embedded applications for which power consumption, MPU performance, and system cost are deciding selection factors.
The PSC1000 MPU contains 52 general-purpose registers, including 16 global data registers, an index register, a count register, a 16-deep addressable register/return stack, and an 18-deep operand stack. Both stacks contain an index register in the top element, are cached on chip, and, when required, automatically spill to and refill from external memory. The stacks minimize the data movement typical of register-based architectures, and also minimize memory accesses during procedure calls, parameter passing, and variable assignments. Additionally, the MPU contains a mode/status register, two stack pointers, and 41 locally addressed registers for I/O, control, configuration, and status.
VP6K Java processor is a 4-pipeline, 32-bit RISC SoC designed by Dept. of Electronics Engineering from Sun Yat-sen Univ., China. It is specially designed for real-time, low power embedded application systems running Java programs with small chip size and high efficiency, such as set-up boxes, game console, tax-control machine, etc.
VP6K translates the Java bytecodes to local instructions by direct mapping, and all local instructions can be executed at the rate of 1 instruction per CPU clock cycle. It is a SoC which integrates common using peripheral controller IP cores, all modules within the chip are connected with AMBA standard buses.
Further details of VP6K will be discussed in next chapters.
VP6K Java core
VP6K is designed for real-time applications such as RFID system. The mechanism of VP6K is to translate Java bytecodes into segments of local instructions of the chip and execute in sequence. The Java processing core of VP6K has a stack-based fully pipelined architecture which is designed as a RISC core, so that it is time-predictable with single cycle execution of local instructions. The pipeline structure can be seen in Fig. 1.
Fig.1. VP6K Java core pipeline data-flow
As in Fig. 1, the first stage of the pipeline fetches Java bytecodes - the binary instructions of the JVM - from cache and maps these bytecodes into addresses of local instructions segments. One single bytecode can be mapped into a segment containing single local instruction or several local instructions. This is how to translate unpredictable timing into predictable one.
After bytecode translation, three more stages for the Java core executing local instruction segments are followed. The second pipeline stage fetches local instructions from the internal instruction set memory. Memory can employ either ROM or RAM technique, as we discuss it in the next chapter. Besides the usual decode function, the third pipeline stage also generates addresses for the stack RAM. As every stack machine instruction has either "pop" or "push" characteristics, it is possible to generate "fill" or "spill" addresses for instruction at this stage. The last pipeline stage, execution stage performs ALU operations, load, store and stack spill or fill. At the execution stage, operations are performed with the two topmost elements of the stack. The bytecode cache, microcode RAM/ROM, and stack RAM are implemented with single cycle access of logical ASIC memory process.
As it is shown in Fig.2, the main core is a 4-stage Java processing unit as it is discussed above with an AHB interface. A memory controller system consists of three different sub-systems which are SRAM controller system, DRAM controller system and NOR-Flash controller system. The memory system has alterable bit-width as 8/16/32 bits, it can be set to suitable bit-width according to the application requirement. Some peripheral controllers are integrated in the chip too, such as a 10/100M Ethernet controller, I2S bus controller, a small-size LCD monitor controller, a timer, 16 GPIO interfaces, I2C bus controller and a UART controller. All modules are interconnected with AMBA standard buses.
Fig. 2. VP6K schematics
VP6K chip consists of two sets of AHB bus, the main core connects to the high AHB bus while high-speed peripheral controllers connect to the low AHB bus. Two AHB buses communicate through a bridge module. So the two sets can use different clocking frequency. As a matter of fact, clocking frequency of the low AHB bus is always half of the high one. This is an effective way to reduce the total dynamic power consumption of the chip. A reset-signal generator assures that the chip will be set to the initializing status. A clock generator has 3 clock outputs which are the clocking sources of different parts in the chip. One is for the "debug" module which will be discussed later, another is for the high AHB set, the third one is for the low AHB set. There is a clock manager setting the parameters for the clocking sources, it can tune the clock frequency dynamically from 20MHz to 300MHz for the high AHB set while the chip is working. As it is mentioned before, clock frequency of the low AHB bus will be half of the high one.
Fig. 3. How debug module works with the main core
One of the most creative features of VP6K is the initializing method. The chip does not have any local instructions fixed inside. Instead, all the local instructions and other initializing data are stored in an external flash, so the data can be changed easily. Debug module loads all data into the chip when system starts. The relationship between debug module and the chip is illustrated in Fig.3.
The main core should be initialized before it can work properly, and debug module only works when the chip is initializing. The debug module has the highest priority on AMBA bus, so that it can automatically load in the contents to internal RAMs without the authorization from the main core when system is on. After initializing, debug module is no longer active. The chip is booting up then changes into normal working status. The whole initializing process will take less than half of a microsecond. Developer can make changes to the initializing data, to set the parameters as needed, such as clock frequency, R/W waiting cycles, booting codes and so on. In such case, the chip can work more properly in different situations.
This paper also presents a verifying platform for VP6K Java processor. All the functions can be tested on this hardware platform. It is shown in Fig.5. VP6K chip model is shown in Fig.4.
Fig.4. VP6K chip demonstration
Fig.5. VP6K verification platform
As Fig.4 is shown above, the VP6K processor is at the middle-left of the printed circuit board. A LCD interface is at the top side of the board. DRAM and SRAM modules are at the middle while NOR-flash module is at the back side which can not be seen in Fig.4. Also an Ethernet MII interface, a UART interface, audio input/output interface can be easily located on the board. Two sets of I2C pins are at the bottom-left, GPIO pins are at the left side of the VP6K CPU.
An Altera FPGA, model EP1C6T144C8N, is integrated into the platform in order to extend the function of the Java processor, such as a keyboard for embedded system. CPU uses 20MHz passive oscillator as the clocking source for the whole chip, and the power voltage is 3.3V for I/Os, 1.8V for core supply.
All functions have been tested thoroughly by test-benches written in Java. Test results have been certified by CCTL (Communication Calibration and Test Laboratory) of the 7th research Institute of CETC. Tab-1 includes all test results, the recording document No. is 2008(ext).391.
VP6K Java processor test results
Testing conditions: 25â„ƒ, 5V input (3.3V I/O, 1.8V core)
Communicates with PC, transferring data packages
Communicates with PC, transferring data packages
Store Java programs, and are tested by several benches
Inputs wave signals, stores them in memory, then outputs signals
Reads data from and writes data into an I2C based E2PROM
Display a RGB-color stripes animation on a 1.8' LCD screen
Inputs and outputs signals as programmed
200Mhz works well for all chips, a few works up to 300Mhz
Tested when system is playing music
A Dhrystone testing result is also presented. The Java testing program source code originated from Sun MicroSystems Inc., and the final score is 20.7 Dhrystones calculated on 40,000 cycles. The result is about three times more efficient than "soft" JVM built on the embedded CPU with same frequency.
Fig.6. Freq. comparison
Fig.7. Power comparison
Fig.8. Price comparison
Several conclusions can be drawn from above. Java processor is much more efficient than "soft" JVM implemented on embedded system when executing Java programs. In Fig.6, VP6K frequency is compared with other Java processors, figure shows that VP6K has great advantage than ARM7 core. VP6K passes all the tests based on Java. With the peripheral controllers that VP6K integrates, it can be widely used in different embedded systems. VP6K has a 2 mm ï‚´ 2 mm die size approximately using 0.18 um process. In Fig.7, appraisal of VP6K selling price includes research, development, testing and mass production, etc. When working at 100 MHz, the power consumption of VP6K is less than 60 mW. In Fig.7, it shows the dynamic core power of VP6K is about 0.25 mW/MHz based on the core size of the whole chip size. It is for sure that VP6K is one of the best Java processors for the RFID tag readers. And VP6K Java core can be trimmed to be the MCU of Java card with much less power consuming and adequate performance.