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 Software defined radio (SDR) system is a radio communication system in which some or all physical layer functions are software defined (or) SDR defines a collection of software and hardware technologies in which some or the entire physical layer processing functions are implemented through modifiable software or firmware operating on programmable processing technologies. These devices include digital signal processors (DSP), general purpose processors (GPP), field programmable gate arrays (FPGA), programmable system on chip (SoC) etc. the main use of these technologies allows new wireless features and capabilities to be added to existing radio systems without requiring new hardware.
 By employing software radio, we can reduce the cost of the base station, since a single transceiver is required, instead of a transceiver for each channel. More over we increase the flexibility of the base stations which can be programmed for the different existing standard, as well as for undefined future standards.
A digital radio system consists of three main functional blocks. They are RF unit, IF unit and base band unit. RF unit consists of essentially analog hardware modules, while IF unit and baseband unit contain digital hardware modules. The RF unit, also called RF front end is responsible for transmitting/receiving the radio frequency (RF) signal from the antenna via a coupler and converting the RF signal to an intermediate frequency (IF) signal. The RF unit on the receive path performs amplification and analog down conversion from RF to IF. On the transmit path, RF unit performs analog up conversion and RF power amplification.
Figure1. Block diagram of generic software defined radio
The ADC / DAC blocks carry out analog to digital conversion on receive path and digital to analog conversion on transmit path. DUC/DDC blocks in channelization and sample rate conversion perform modem operations, i.e. modulation of the signal on transmit path and demodulation of the signal on the receive path. The baseband unit performs baseband operations such as connection setup, equalization, frequency hopping, timing recovery, correlation and also implements the link layer protocol. DDC/DUC and baseband processing operations require large computing power and these modules are generally implemented using ASICs or DSPs.
A software defined radio system is one in which the baseband processing and DDC/DUC modules are programmable. Availability of smart antennas, wideband RF front end, ADC/DAC technologies and increasing processing capacity of DSPs and general purpose microprocessors have fostered the development of multi band, multi standard, multi mode radio systems using SDR technology.
Role of ADC/DAC in SDR:
ADC is device that converts analog (continuous) signals into digital (discrete) signals.  The role of ADC block is that of enabler for the required specification. A number of ADC architectures such as sigma-delta architecture, flash architecture, pipelined architecture are suitable for use in SDR systems. These architectures are optimized for certain parameters, for example sigma-delta architectures are optimized for power efficiency while flash converters are optimized for speed. So ADC architectures are pivotal in optimizing performance on a given process. So an architecture that is optimal on process may not be optimal on another. The pipelined architecture is one of the more common for high performance, high speed converters because it allows tradeoffs between power, speed and size, while new architectures continue to evolve, pipelined converters will continue to lead the performance.
Common ADC and DAC Architectures:
 The basic components of an ADC are a sampling circuit, comparators and encoding logic. The basic components of DAC are a voltage/current-referenced switch and decoding logic and sometimes deglitching circuit.
These basic components can be linked in a variety of ways to create different data converter structures-some that combine ADCs and DACs in a single circuit.
Parallel structures (Flash ADCs, String DACs and binary structures)
Segmented Structures (Folding and Interpolating ADCs and Segmented Ladder DACs)
Iterative structures (Subranging/Pipelining/Half-flash ADCs and Successive Approximation ADCs)
Sigma-Delta structures(Sigma delta ADCs and DACs)
One of the first data converter architectures was the flash converter. A flash or parallel converter, as they are often called, consists of 2â¿-1 comparators, where 'n' is the number of digital output codes. One input of all of the comparators is tied to the analog input via buffers, track-and-hold circuits, or the other conditioning elements. The other inputs are tied to successive steps on a resistor ladder. The top and bottom of the ladder are tied to reference voltages that represent the input range of the flash.
Figure 2: Typical flash ADC architecture
Because of the straight forward design, this architecture offers extremely fast conversion times.
For low resolution applications, premium performance can be obtained at a minimum cost.
As the number of bits increases, the size of the chip, costs, and complexity increase at an exponential rate of 2â¿.
In practice there are very few flash ADCs larger than 10 bits. Beyond this point they are too big and complex to manufacture efficiently, thus impacting on cost.
In order to overcome the complexity problem, different architectures have been developed which use small number of comparators such as in folded flash or pipelined architectures. In addition, as the number of comparators increases, the reference voltages get smaller and smaller. As the reference voltage is reduced, the offset voltage of the comparator is approached. Once this happens, the linearity and overall performance of the converter is compromised.
Finally, as more comparators are connected to the analog input, the input capacitance increases. With the increased capacitance, the effective signal bandwidth is reduced, defeating the high speed benefit of the parallel converter.
Segmented Ladder DAC:
Segmented ladder DACs combine a String DAC and a Ladder Network DAC to create a high-resolution DAC that is neither extremely complex nor cumbersome to trim. Depicted in Figure â€¦. A segmented DAC generates the MSBs(t) portion of the analog output signal with a Current Division String DAC and the LSBs(t) portion of the output signal with a Ladder Network DAC. The resistors in the String DAC assume the same resistance as the "rungs" in the Ladder Network DAC could achieve independently without incurring any penalty in speed.
 Figure 3: Seven-Bit Segmented Current Ladder DAC
Pipelined ADC/ Sub ranging ADC:
A pipelined ADC architecture implements an iterative structure. Iterative structures seek to reduce the complexity of a parallel structure by first converting the signal using a data converter with a resolution of less than B, the final desired resolution.
Sub ranging architecture uses two distinct Flash ADCs, each with B/2 bits of resolution. The output from the sample and hold circuit is analog signal which is converted to digital signal by using a Flash ADC (B/2-bit). The output from this converter forms the B/2 MSBs of the output signal. The digital output is again converted to analog by using the Flash DAC(B/2-bit). The original input is subtracted by the output of the DAC to form a difference signal. This difference signal is scaled by a factor of . The other Flash ADC is used to form the LSBs at the output of the sub ranging structure.
Figure 4: Sub ranging ADC
The settling time for the first stage ADC and DAC is more which effects the speed of the Sub ranging converter.
By using the digital error correction techniques we can overcome this drawback. Additional sample and hold circuits are used to obtain a better performance.
A pipelined architecture is formed by linking a multiple sub ranging stages. For an N-stage pipelined architecture each stage will be producing B/N bits (B-total number of quantization bits). Each stage has B/N-bit Flash ADC and DAC except for the last stage where it has only one Flash ADC. By assuming the Flash ADCs and ladder network DACs, the total number of comparators required can be assumed by the equation
Figure 5: Pipeline Sub ranging ADC
This architecture has high resolution and high speed and it can be called as good mid-range performance architecture.
The bandwidth is high for this architecture.
Due to number of cascaded stages and wide bandwidths Thermal noise limits potential SNR.
By the effects of cascaded converters and linear stages it is Spurious Limited.
In wireless applications the Î£Î” ADC can offer integration with other RF/IF functions to build highly optimized integrated circuit(IC) devices. The Î£Î” ADC consists of an analog filter, a quantizer (comparator), a decimation digital filter circuit and a DAC
Figure 6 : Sigma-delta ADC
The main principle behind the Î£Î” ADC is over-sampling, integration and decimation digital filter. Î£Î” modulators work by sampling faster than the Nyquist criterion and making the power spectral density of the density of the noise nearly zero in a narrow band of signal frequencies(quantization noise shaping).The over-sampled signal spreads the quantization noise over a wider frequency spectrum range and is then integrated linearly. The integrated result has greater dynamic range and smaller bandwidth than the over-sampled signal. The fastest conversion rates are achieved using a minimum number of quantization bits.
ðœ‚ +10 dB.
For every doubling of the sampling rate above the Nyquist rate 3dB of processing gain can be achieved.
This architecture is good for high resolution (>20bits) and is good for low to medium bandwidths.
This architecture has a small chip area and ideal for integration Baseband applications.
When bandwidth is proportional to clock rate and core ADC/DAC size the clock rate is limited and has larger ADC/DAC size which increases complexity and power consumption will be more.
When bandwidth is inversely proportional to decimation the decimation rate is determined by ADC/DAC bits, clock rate and Bandwidth.
A number of limitations exist in data converters. When considering advances in ADCs and DACs, the bottleneck is imposed by the performance limitations of ADC devices available to date. Current research is guided by attempts to overcome or bypass such limitations. While improvements have continually occurred over time, the process is at least partially reset each time a new semiconductor process is employed. Because of this, improvements often tend to be two steps forward and one step backward. Cost pressures push decisions to switch to newer processes whereas remaining on older processes would indicate that generational improvements in performance are possible but not necessarily a cost reduction.
Interfacing to the analog input is becoming more difficult. For low-frequency applications, this is not a big issue but as IF frequencies increase and direct RF sampling becomes a possibility, proper impedance matching to the source becomes more critical. At high frequencies, optimal ADC performance is only achieved when a proper match exists not only because the input is presented with a maximum of signal level but because ADC input behavior in terms of both noise and especially spurious is optimized.
3-Bit 20GS/s Interleaved Flash ADC in SiGe Technology
A 3-bit ADC for software defined radio applications to operate at Ku-band, two flash current mode logic (CML)ADCs are time interleaved to achieve a 20GHz sampling rate. A 3-bit current steering DAC is designed for testing the high-speed ADC.
The proposed 3-bit ADC-DAC RFIC is composed of two 3-bit time-interleaved flash ADCs and a single 3-bit DAC for ADC testing. Each ADC contains a sample/hold (S/H) amplifier, current comparators, thermometer-to-gray coder and D-flip-flops (DFFs) for retiming and buffer. The outputs of the two ADCs are time interleaved and combined using a high-speed multiplexer (MUX). In order to obtain the maximum sampling rate, a current-steering DAC is implemented.
Operation of ADC-DAC:
The input analog signal is sampled by two S/Hs for both odd and even channel ADCs driven by out-of-phase clocks. The signals after S/H are compared with 7 current mode comparators which are set with 7 successive offset currents representing the 7 quantization threshold levels. After thermometer-to-gray coder and DFFs, the original analog input signal is converted into digital signals with gray code weight. Due to time-interleaving, the digital outputs in every stage are needed to be multiplexed by a clock signal with double frequency to generate the desired output at the doubled sampling rate. The 3-bit DAC converts the digital signals back to an analog signal that can be tested and measured easily using a digital scope or a spectrum analyzer.
Figure 7: Simplified block diagram for the proposed 3-bit time-interleaved high-speed flash ADC and DAC.
In order to demonstrate the software defined RF receiver, the ADC-DAC chip also includes a 10GHz RF front-end with an LNA and a VGA and a VCO generating the internal clock. The ADC-DAC RFIC is implemented in a 0.12 mm SiGe technology and occupies an area of 1.5 x 1.7 mmÂ². The total power consumption for the entire ADC-DAC chip is 2.36 W with a 4.2 V power supply. The ADC-DAC RFIC is packaged in a 44-pin CLLC package and achieves a peak spurious free dynamic range (SFDR) of 30.5 dBc and a peak effective number of bits (ENOB) of 2.8 bits at a 20 GS/s sampling rate.
The maximum dynamic range the implemented ADC-DAC can achieve is 30.5 dBc with a 4.2 GHz ADC input. For larger than 20 dBc SFDR, the ADC achieves an input bandwidth larger than 5.5 GHz. When the ADC input frequency is close to the Nyquist frequency, the dynamic performance is degraded due to the channel mismatch in odd and even channels of the time-interleaved ADC and the bandwidth limitation of the S/H circuit.
Rapid Single Flux Quantum(RSFQ) :
This technology is based on a fundamental quantum mechanical property of superconductors, stating the existence of magnetic flux in discrete quantized form. In this technology single flux quantum pulses represent binary values. Since an integrated single flux quantum represent a pulse, the performance of the technology is strictly limited by the maximum slew-rate of the input signal. Hence, the performance of the technique is optimized by a trade-off between the resolution and the speed of processing. In an oversampled superconductive-based ADC, the effect of aperture jitter is reduced significantly; therefore very wideband operation becomes feasible. Superconductive ADCs operating at 19.6 GHz has been demonstrated. One important note regarding these ADCs is that the sampling rate at the input is not the same as the output of the device.
Figure 8: RSFQ ADC
There is a programmable decimator inside the converter, which has to be set based on a trade-off between number of bits and the bandwidth. The other very important feature of a superconductive ADC is its high sensitivity. The minimum required power to drive SFQ circuit is less than 1uW that is three orders of magnitude less than 1mW required power for a high speed semiconductor ADC. This feature coupled with high sampling rate eventually eliminates the necessity of a Low Noise Amplifier (LNA) and the resulting direct sampling at the antenna port leads to more system gain. Although superconductive ADCs have not yet performed significantly better than semiconductor counterpart, the main essence of the technique is very promising.