Implementation Of Controller On FPGA Computer Science Essay

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In this technological advancement of FPGA's there have been many paths for DSP applications where FPGA has many advantages in providing optimal device utilization adaptability and high design flexibility.

Basing on these features Mr.Sonny bui designed a controller in VHDL coding, and we implemented the same controller using Xilinx ISE on a FPGA board ( Virtex-II Pro Board, FG256).And we used Chipscope logic analyzer to capture the logic in VHDL coding and display the all internal node signals of the circuit using JTAG interface.Most of our thesis work deals with effective working and understanding of chipscope technology.



Problem statement



3.1 Xilinx ISE 8.2i


1.1 Introduction: The main focus of Alstom is to provide Instrumentation, control and electrification of Power plants. These kind of power plants or Industries produces flue gases and other harmful susbstances.And our thesis work is involved to turn out power generation which is helped to hygiene these flue gases. So these filtering systems consists of power converters which includes three main parts Controller, Power converter and an Observer.

In this paper, a Controller is implemented using Xilinx Chipscope logic analyzer.The main contribution of controller is to compare the incoming information with a set of points and adjust the system accordingly. Therefore the controller is built as a state feedback controller.

A/D Converter



Fig 1.1 System Overview


2.1 Purpose: Controller in general has 3 parts. A Digital signal processor, FPGA circuit and Hardware. For the high level control of the system a Digital signal processor is used and power converter's control algorithm is run by the FPGA circuit with a short sampling interval.And Hardware controller is an other way to use FPGA controller.

The main purpose of this work is to develop the programming code in order to attain quicker calculations with user constraints.

Industrial Application




Digital Signal Proce-ssor


Fig 2.1 Model Of Controller



3.1 Objective: The main Objective is to implement controller using Xilinx ISE 8.2i on FPGA board ( VIRTEX-II Pro, xc2v100 FG256 chip).This report supports users how to use Xilinx project navigator and chipscope for different methods to perform calculations on signals inside FPGA. It is a design which is fully simulated and requires board level testing.JTAG interface acts like communicator between FPGA and PC.

And the other main task is to show a user how to integrate a chipscope tool into a complex design in an efficient manner to authenticate its operation.

3.2 Software:

Xilinx ISE offers analysis tools for both design Implementation and design concept. The ISE tools help to reach optimal design results with timing predictability and reconfiguration with greater flexibility and size. Xilinx ISE maps the design over the available chip area. Once after generating the bit file and loading it on to the kit, we have an access to analyze the design using chipscope pro analyzer.

Larger silicon area, longer is the design time and high cost. In order to eliminate these serious causes, a good vendor of FPGA products, XILINX introduced a new revolutionary testing tool for large circuits.This is what we call Chipscope logic analyzer which is connected to VHDL code and implemented with the circuit under test on the same FPGA.

3.2.1 Chipscope Organization and its Importance:

Chipscope is a complete solution for both Software and Hardware. It doesn't depends upon testbench. To capture signal samples the Integrated Logic Analyzer (ILA) tool is used and Integrated Bus Analyzer(IBA) for buses.

ILA: This is a core which allows the user to view and trigger on signals in Hardware desin. One ILA supports one clock input, 64 internal trigger signals and one external signal. Maximum data/trigger width is 64 bits. There is a possibility of storing multiple ILA's on same FPGA. Each ILA core uses 32Kbits of capture storage for Virtex-II family.IBA cores are used to monitor system buses.

ICON: The second type of core is called Integrated Control core (ICON). Internal RAM signals are exported using ICON core. ILA's use a common ICON to communicate through JTAG interface with the PC . And this interface is used to configure the architecture of FPGA. These cores are very useful to manipulates signals directly form hardware during run time.

The third component is Chipscope Logic Analyzer. It has 3 features:

Configuration of ILA's and ICON

Transfering data samples to the PC

Analysis of stored signal samples

Each ILA data input has a node associated with tested circuit. Chipscope Logic Anlayzer has different options for displaying the captures signals. The data can be taken in any base types like binary, decimal, hexadecimal, octal or ASCII.

3.3 Hardware:

Hardware belongs to FPGA family called VIRTEX-II Prototype which is used to verify implementation. And the device used is xc2v1000 and package is set to FG256 ,speed is set to -6. The VIRTEX-II board has a parallel IV cable which is used for JTAG configuration.



4.1 Design Overview:


A1_in A1_delay

A2_in A2_delay

B1_in B1_delay

B2_in B2_delay




iLN A1

r2_pos A2

r2_neg B1

r2_ref B2

t B22

iLN iLN_buf_ut

uCN r_two_pos

u0N r_two_neg

yo_2 ‹




ION UON_eight

UON r2_ref_ut

cso_n mem_IO

data_in mem_UO

rd_n min_clk

addr data_out

we_n select_signal


sw t_ut







Design Of Controller

Designing of this FPGA controller was made by Sonny Bui. The function each block is defined below as

4.1 Interface2:

This is the very first design block in this heirarchy which acts like communication between FPGA and Digital signal processor. Values for ULN and ILN are provided by DSP which are stored in memory and updated whenever needed by DSP.


Conv2 looks for a reference value from the values stored in Interface2.

4.3: calc_cmp:

Normalizing calculations of values ILN and UCN are done by the calc_cmp.

Upcoming refernce value of conv2 is compared by squaring and adding of ILN and UCN values.


FSM evaluates the values of R2 with R2 reference values.Depending upon the comparsion the state of the system is determined.There are 4states.Each state has

Maximum and minimum time.In these cases if the time exceeds the maximum limit the system will be asked to stop state.The physical system's positive or negative voltage depends upon the state of the system.


The responsibility of observing track of timers between FSM and delay is maintained by TimeTest.

4.6: Delay:

There is a constant maintenance of 1µs between opening of 2 switches and closing of next 2 corresponding switches where all switches are open. This makes the system to disperse remaining energy and prevent shortcuts.

4.2 Process:

Insert control and ILA cores into HDL design.

Connect buses and internal signals

Generate Control core and ILA core using appropriate method.

Synthesize design using Xilinx design tools.

Place and route the design with ILA cores.

Download bitstream on to FPGA and analyze the signals using chipscope.

4.3 Using Project Navigator :

Digital design logics on FPGA's are mostly implemented using Xilinx Project Navigator. Design entry in Project navigator has the following steps:

4.3.1 Creating a New project:

1. Open Project Navigator and select File New Project.


2. It opens as the above figure. Give the project name and project location. It should be noted that the project location should be in hard disk(C) drive and spaces are not allowed in Project name.

3. Set the Top-Level Module Type to HDL and click Next.

4.3.2 Selecting Device properties and Design flow:

1. Select the Device properties like below. And simulator can be choosen as per available like modelsim or ISE simulator. Here in this project we use ISE Simulator(VHDL/Verilog) 2.Select Next to complete this step.


4.3.3 Adding source files or new sources:

1.Now select Project  Add source instead of Add copy of source .Navigate to the folder where you stored VHDL files(controller & sub-files).Project Navigator will keep hierarchy of files showing which modules are instantiated to top module.

2. If something goes wrong with synthesizing design then there shows some message in console and even shows '?' next to the module which are missing.


3.Hierarchy looks something like above figure in Sources window under top module.

4.3.4 Adding Chipscope Definition and Connection File.

1. Now right click on the top module (controller) of design which ought to be verified and select New Source. Then select Chipscope Definition and Connection File and give some appropriate name to it.


Click on Next to finish adding this file.


2. In order to identify easily and preferred signal names under each ILA , right click on Synthesize-XST properties. And select Keep Hierarchy 'Yes' or 'Soft'.

3. Click on Apply and OK to finish this step.

4. Double click on the Chipscope Definition and Connection source File which intends to open Chipscope pro core inserter.