Implementation Of Blocks Using Mentor Graphics Computer Science Essay

Published:

This essay has been submitted by a student. This is not an example of the work written by our professional essay writers.

Logic gates are generally constructed using transistors depending on the technologies. The new technology which used is CMOS technology where MOSFET transistors are used for constructing integrated circuits. CMOS stands for complementary metal oxide semiconductor. Every logic gate is complementary because every gate structure is made up of pull up network where p type transistors are used and pull down network where n type transistors are used. These two networks are complementary to each other.

Figure () shown is symbol of n-channel MOSFET. Each transistor consists of four terminals, gate, source, base and drain. The gate is a metallic layer deposited on the substrate (body) and voltage is applied across the gate to control the flow of current between drain and source.

If the gate voltage (Vgs) is zero, there is no current flow from drain to source because there is no path between drain and source, the MOSFET is OFF i.e., cut off. If the gate voltage (Vgs) is positive and more than the threshold value, then current flows from drain to source because there is a channel between drain and source. In this case, the MOSFET is ON (saturation).

Figure () shown is the symbol of p-channel MOSFET. The operation of p channel is similar to n type but Vds and Vgs are negative. When the gate voltage is negative i.e., zero less than the threshold voltage, there exists the channel between drain and source allows current to flow from source to drain. The transistor is ON i.e., saturation region. If the gate voltage is positive then the transistor turns OFF.

() n-channel MOSFET () p-channel MOSFET

CMOS logic uses both n channel and p- channel MOSFET to perform logic functions. CMOS technology has an advantage of low power dissipation compared to TTL logic. CMOS circuit s consists of pull up network and pull down network where pull up network consists of PMOS transistors and pull down network consists of NMOS transistors. Figure below shown is CMOS inverter.

When the positive voltage (logic 1) is applied to the gate inputs, transistor Q1 is OFF and transistor Q2 is ON and this makes the transistor Q2 to connect to VSS giving zero output. FIGURE (C): CMOS inverter

When the zero volts is applied to the input, transistor Q1 is on and transistor q2 is off and this condition makes the transistor Q1 to connect to VDD (supply voltage) giving out high output.

CMOS AND Gate:

Figure () shown is CMOS two input AND gate. Input A and input B are the two inputs to gate and output is the output of the AND gate. In the CMOS 2 input AND gate, number of transistors used in the circuit are 6(3 PMOS transistors and 3 NMOS transistors). C35B3CO technology is used to build this circuit and the characteristics of PMOS and NMOS are described above. The PMOS transistor Q1 and Q2 are connected in parallel i.e., drain of the transistor Q1 is connected to the drain of the transistor Q2 and this section forms pull up network .The NMOS transistors are connected in series i.e., source of the transistor Q3 is connected to the drain of the transistor Q4 and this forms pull down network. The parallel connection of the PMOS transistors are connected to the series connection of the NMOS transistors and output at this point is CMOS NAND gate and this is connected to the CMOS inverter circuit to form CMOS or gate.

C:\Users\Vardan\Desktop\AND gate pictures\and gate.png

Implementation of the CMOS two input AND gate using mentor graphics is shown in page ().The output waveforms for the CMOS two input AND gate is as shown in the page ().

The design is checked for errors and then it is net listed and simulated. Characteristics of the input signals given are shown below.

Name: in1, signal: inA Name: in2, signal: inB

Initial value (V/A) =0 Initial value (V/A) =0

Pulsed value (V/A) =5 Pulsed value (V/A) =5

Delay(s) =1e-09 Delay(s) =0

Rise time(s) =1e-09 Rise time(s) =1e-09

Fall time(s) =1e-09 fall time(s) =1e-09

Pulse width(s) =5e-08 Pulse width(s) =5e-08

Period(s) =1e-07 Period(s) =1e-07

For supply voltage

Name: power, signal: VDD, DC value (V/A) =5

After simulation, net listing information from the design

Number of cells: 3

Number of instances: 6

Simulation information:

Memory size allocated in bytes=1431687

Latency= 0.000%

Average number of iterations=0.704225

Nb of components=21

Nb of nodes=18

No. of MOS or BIP calls=3239

No. of steps completed=192

<<<CPU TIME 0s 200ms>>>

<<<GLOBAL CPU TIME 0s 480ms>>>

CMOS OR Gate:

Figure below shown is CMOS two input OR gate. A and B are the two inputs to gate and Q is the output of the OR gate. In the CMOS 2 input OR gate, number of transistors used in the circuit are 6(3 PMOS transistors and 3 NMOS transistors). C35B3CO technology is used to build this circuit and the characteristics of PMOS and NMOS are described above. The PMOS transistor T1 and T2 are connected in series i.e., drain of the transistor T1 is connected to the source of the transistor T2 and this section forms pull up network .The NMOS transistors are connected in parallel i.e., drain of the transistor T3 is connected to the drain of the transistor T4 and this forms pull down network. The series connection of the PMOS transistors are connected to the parallel connection of the NMOS transistors and this connection forms CMOS NOR gate and this is connected to the CMOS inverter circuit to form CMOS OR gate

C:\Users\Vardan\Desktop\orgate pictures\Untitled.png

Implementation of the CMOS two input OR gate using mentor graphics is shown on the page ().The output waveforms for the CMOS two input OR gate is as shown in the page ().

The design is checked for errors and then it is net listed and simulated. Characteristics of the input signals given are shown below.

Name: in1, signal: inA Name: in2, signal: inB

Initial value (V/A) =0 Initial value (V/A) =0

Pulsed value (V/A) =5 Pulsed value (V/A) =5

Delay(s) =1e-09 Delay(s) =0

Rise time(s) =1e-09 Rise time(s) =1e-09

Fall time(s) =1e-09 Fall time(s) =1e-09

Pulse width(s) =5e-08 Pulse width(s) =5e-08

Period(s) =1e-07 Period(s) =1e-07

For supply voltage

Name: power, signal: VDD, DC value (V/A) =5

After simulation, net listing information from the design

Number of cells: 3

Number of instances: 6

Simulation information:

Memory size allocated in bytes=1431687

Latency= 0.000%

Average number of iterations=0.704225

Nb of components=21

Nb of nodes=18

No. of MOS or BIP calls=3239

No. of steps completed=192

<<<CPU TIME 0s 200ms>>>

<<<GLOBAL CPU TIME 0s 480ms>>>

CMOS NAND GATE:

Figure below shown is CMOS three input NAND gate. A, B and C are the three inputs to gate and OUT is the output of the NAND gate. In the CMOS 3 input NAND gate, number of transistors used in the circuit are 6(3 PMOS transistors and 3 NMOS transistors). C35B3CO technology is used to build this circuit and the characteristics of PMOS and NMOS are described above. The PMOS transistor Q1, Q2 and Q3 are connected in parallel, this section forms pull up network .The NMOS transistors Q4, Q5 and Q6 are connected in series, this forms pull down network. The parallel connection of the PMOS transistors are connected to the series connection of the NMOS transistors and output at this point is CMOS NAND gate.

Implementation of the CMOS two input OR gate using mentor graphics is shown on the page ().The output waveforms for the CMOS two input OR gate is as shown in the page ().The design is checked for errors and then it is net listed and simulated. Characteristics of the input signals given are shown below.

Name: in1, signal: inA Name: in2, signal: inB

Initial value (V/A) =0 Initial value (V/A) =0

Pulsed value (V/A) =5 Pulsed value (V/A) =5

Delay(s) =1e-09 Delay(s) =0

Rise time(s) =1e-09 Rise time(s) =1e-09

Fall time(s) =1e-09 Fall time(s) =1e-09

Pulse width(s) =5e-08 Pulse width(s) =5e-08

Period(s) =1e-07 Period(s) =1e-07

Name: in1, signal: inA

Initial value (V/A) =0

Pulsed value (V/A) =5

Delay(s) =1e-09

Rise time(s) =1e-09

Fall time(s) =1e-09

Pulse width(s) =5e-08

Period(s) =1e-07

For supply voltage

Name: power, signal: VDD, DC value (V/A) =5

After simulation, net listing information from the design

Number of cells: 3

Number of instances: 6

Simulation information:

Memory size allocated in bytes=1431687

Latency= 0.000%

Average number of iterations=0.704225

Nb of components=21

Nb of nodes=18

No. of MOS or BIP calls=3239

No. of steps completed=192

<<<CPU TIME 0s 200ms>>>

<<<GLOBAL CPU TIME 0s 480ms>>>

CMOS XOR GATE:

The basic cmos XOR gate which uses both pmos and nmos is as shown

untitled12

In the CMOS 2 input XOR gate, six PMOS transistors and six NMOS transistors are used. There are two inverting circuits which are used to get the complement of the inputs.

In the pull up network both inputs A and B are connected in parallel and this is connected in series with the parallel connection of complements of A and B.

In the pull down network both inputs are connected in series and this is connected in parallel with the series connection of complements of A and B.The utput is in between the connection of pull up network and pull down network.

The design is checked for errors and then it is net listed and simulated. Characteristics of the input signals given are shown below.

Name: in1, signal: inA Name: in2, signal: inB

Initial value (V/A) =0 Initial value (V/A) =0

Pulsed value (V/A) =5 Pulsed value (V/A) =5

Delay(s) =1e-09 Delay(s) =0

Rise time(s) =1e-09 Rise time(s) =1e-09

Fall time(s) =1e-09 Fall time(s) =1e-09

Pulse width(s) =5e-08 Pulse width(s) =5e-08

Period(s) =1e-07 Period(s) =1e-07

For supply voltage

Name: power, signal: VDD, DC value (V/A) =5

After simulation, net listing information from the design

Number of cells: 3

Number of instances: 6

Simulation information:

Memory size allocated in bytes=1431687

Latency= 0.000%

Average number of iterations=0.704225

Nb of components=21

Nb of nodes=18

No. of MOS or BIP calls=3239

No. of steps completed=192

<<<CPU TIME 0s 200ms>>>

<<<GLOBAL CPU TIME 0s 480ms>>>

CIRCUIT DIAGRAM:

Half adder is designed using XOR gate AND gate and shown in the figure.

untitled13

Implementation of the CMOS two input and using mentor graphics is shown on the page ().The output waveforms for the CMOS two input AND gate is as shown in the page ().

The design is checked for errors and then it is net listed and simulated. Characteristics of the input signals given are shown below.

Name: in1, signal: inA Name: in2, signal: inB

Initial value (V/A) =0 Initial value (V/A) =0

Pulsed value (V/A) =5 Pulsed value (V/A) =5

Delay(s) =1e-09 Delay(s) =0

Rise time(s) =1e-09 Rise time(s) =1e-09

Fall time(s) =1e-09 fall time(s) =1e-09

Pulse width(s) =5e-08 Pulse width(s) =5e-08

Period(s) =1e-07 Period(s) =1e-07

For supply voltage

Name: power, signal: VDD, DC value (V/A) =5

After simulation, net listing information from the design

Number of cells: 3

Number of instances: 6

Simulation information:

Memory size allocated in bytes=1431687

Latency= 0.000%

Average number of iterations=0.704225

Nb of components=21

Nb of nodes=18

No. of MOS or BIP calls=3239

No. of steps completed=192

<<<CPU TIME 0s 200ms>>>

<<<GLOBAL CPU TIME 0s 480ms>>>

CIRCUIT DIAGRAM:

Full adder is designed using XOR, AND and OR gate and shown in the figure.

untitled14

This can also be designed using two half adders and XOR gate as shown in figure ()

http://www.doctronics.co.uk/images/4008_06.gif

Implementation of the CMOS two input and using mentor graphics is shown on the page ().The output waveforms for the CMOS two input AND gate is as shown in the page ().

The design is checked for errors and then it is net listed and simulated. Characteristics of the input signals given are shown below.

Name: in1, signal: inA Name: in2, signal: inB

Initial value (V/A) =0 Initial value (V/A) =0

Pulsed value (V/A) =5 Pulsed value (V/A) =5

Delay(s) =1e-09 Delay(s) =0

Rise time(s) =1e-09 Rise time(s) =1e-09

Fall time(s) =1e-09 fall time(s) =1e-09

Pulse width(s) =5e-08 Pulse width(s) =5e-08

Period(s) =1e-07 Period(s) =1e-07

For supply voltage

Name: power, signal: VDD, DC value (V/A) =5

After simulation, net listing information from the design

Number of cells: 3

Number of instances: 6

Simulation information:

Memory size allocated in bytes=1431687

Latency= 0.000%

Average number of iterations=0.704225

Nb of components=21

Nb of nodes=18

No. of MOS or BIP calls=3239

No. of steps completed=192

<<<CPU TIME 0s 200ms>>>

<<<GLOBAL CPU TIME 0s 480ms>>>

D-flip flop:

D flip flop which is edge triggered is used to hold the previous value than the past value and has inputs D, clock, Preset and clear and outputs Q and Q_bar.the logic symbol for the D flip flop is shown in figure().

Figure():Logic symbol of D-flip flop with preset and clear

Truth table for the D flip flop with preset and clear shown in table ().

The circuit diagram for the above D flip flop is shown in the figure ().Implementation of the CMOS two input and using mentor graphics is shown on the page ().

SHIFT REGISTERS:

The basic 4 bit shift register can be designed using four D-flip flops as shown in the figure().first the register is cleared .Then the data is given serially into the register. For each clock pulse, each bit is shifted from left to right.

Figure():circuit diagram of serial in/serial out register

Implementation of the 8 bit serial in serial out shift register using mentor garphics is shown in page():

Operation of the circuit:

Assuming data to be shifted is 1011.For the first clock pulse,data bit 1 i.e., LSB is stored in the flip flop0.

For the second clock pulse,second LSB bit 1 is given to the register and the previous bit is shifted right and stored in flip flop 1 and the present bit is stored in flip flop 0 as shown below.

For the third clock pulse,third LSB bit 0 is stored in the flip flop0 and previous two bits are shifted right.

After the fourth clock pulse, four bits 1011 are stored in register i.e., each flip flop stores each bit.

Then after each clock pulse, the data is shifted serially out bit by bit. After eight clock pulses again the register is cleared and data is transmitted out.

Writing Services

Essay Writing
Service

Find out how the very best essay writing service can help you accomplish more and achieve higher marks today.

Assignment Writing Service

From complicated assignments to tricky tasks, our experts can tackle virtually any question thrown at them.

Dissertation Writing Service

A dissertation (also known as a thesis or research project) is probably the most important piece of work for any student! From full dissertations to individual chapters, we’re on hand to support you.

Coursework Writing Service

Our expert qualified writers can help you get your coursework right first time, every time.

Dissertation Proposal Service

The first step to completing a dissertation is to create a proposal that talks about what you wish to do. Our experts can design suitable methodologies - perfect to help you get started with a dissertation.

Report Writing
Service

Reports for any audience. Perfectly structured, professionally written, and tailored to suit your exact requirements.

Essay Skeleton Answer Service

If you’re just looking for some help to get started on an essay, our outline service provides you with a perfect essay plan.

Marking & Proofreading Service

Not sure if your work is hitting the mark? Struggling to get feedback from your lecturer? Our premium marking service was created just for you - get the feedback you deserve now.

Exam Revision
Service

Exams can be one of the most stressful experiences you’ll ever have! Revision is key, and we’re here to help. With custom created revision notes and exam answers, you’ll never feel underprepared again.