The modulators are the basic requirement of the communication systems they are designed to reduce the channel distortion & to use in RF communication hence many type of carrier modulation techniques has been already proposed according to channel properties & data rate of the system. Here we are proposing the FPGA based QPSK modulator with analog filters, the proposed system has many advantages over traditional QPSK modulators such as reduced cost, better stability, less complexity. The simulation of the system proves all the features mention above. We have designed the system using VHDL codes in Xilinx & analog filter simulation in Matlab.
Keywords: QPSK, VHDL, Wavelet Transform, Filters.
Modulation is very important block in communication system to transmit the data through channel without loss of data & to reduce size of antenna incase of wireless communication it is also important aspect for FDM. Because of these requirements many models are proposed to design a stable & low power modulator because the requirement of the sine wave as carrier most of the previously proposed models uses the analog circuitry for modulators but the stability of the analog system very much depends upon physical condition of the device as temperature, humidity etc. hence to make design robust & immune to physical conditions we are here proposing the FPGA based technique which not only improves the stability but also the power requirement of the system it also works on higher bit rate than the previously proposed analog systems.
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The proposed model involves a FPGA based 4X1 multiplexer, one clock & four delay blocks to produce four phases then the output is filtered by the analog filter to produce smooth sinusoidal wave at the output.
As the demand for system-on-chip (SoC) implementations increases, the need to accurately model mixed signal designs becomes more important. Digital designs have been highly automated, and the prevalence of top down design is very strong in this area. In contrast, traditional analog RF designs are normally bottom-up, starting at the transistor level. Mixed-signal designers must then take a combination of hierarchical design approaches, and effort is being made to automate this design flow in a similar manner as seen for current digital systems. The overall goal is to provide designers tools to allow the combination of digital and RF models at the net list level, creating a physical SoC model from which masks can be made for quick prototyping and fabrication. The ability to model and co-simulate digital and RF components together was made possible by the creation of hardware description languages (HDLs) such as VHDL-AMS  and Verilog-A. That requires the development of high-level behavioral models for mixed-signal systems blocks. Later, the abstraction levels of these models can be reduced to more accurately model physical circuit implementations. Many of the recently documented system-level behavioral models in VHDL-AMS , have been basic functionality tests that use highly ideal behavioral descriptions and do not include simulation of the high frequency RF blocks. The next step in these simulations is to provide a benchmark for the transceiver system performance by implementing a realistic RF transmission channel. Although noise such as jitter has been modeled in VHDL-AMS , additive white Gaussian noise (AWGN) has not been implemented. This work has not been performed in part because there is no inherent VHDL-AMS command to create various noise distributions, a recognized problem for RF behavioral modeling in VHDL-AMS.In this paper, an AWGN channel model is implemented in VHDL-AMS , allowing a more complete model of system performance measured in terms of bit error rate (BER). Two VHDL-AMS implementations of a pi/4 QPSK transceiver system are developed to verify the functionality of the system illustrate a top-down design approach to mixed-signal behavioral modeling. The first system closely matches the architecture of the theoretical model, while the second system is an iteration of the basic model, implementing a Viterbi encoding algorithm.
3. Proposed Model
All analogue or hybrid analogue/digital QPSK modulators work with phase shift carrier angle, as a key of modulation . The phase signal is most important part in the modulator to acquire two discrete signals (Sine and Cosine) . However, the NRZ format is essential for mapping I and Q. The analogue QPSK signal can be represented mathematically as in Equation (1) and I/Q are defined in Equations (2, 3):
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QPSK (t) = I (t) cos (2ï° f c t) - Q (t) sin (2ï° f c t) (1.1)
I =ïƒ-2E/T cos [(2i-1) ï°/4] (1.2)
Q=ïƒ-2E/T sin [(2i-1) ï°/4] (1.3)
These types of technique are not suitable for medical applications, which essential work with the input data in NRZ signal form at conventional modulators. The proposed QPSK VHDL modulator is programmed generate a carrier phase which acquires four discrete states (0, 90,180,270). Two separate streams in-phase 'I', and quadrature phase Q for mapping the data for controlling the four phase different carriers interfaced to multiplexer. The output is selected by multiplexer to provide a digital QPSK signal, which passes via a passive filter before a transmission (TX) to eliminate the high frequencies . Fig.1 demonstrates the proposed VHDL modulator comparing to analogue modulator. The digital QPSK signal of the multiplexer output can be represented in Equation (4):
(1.4) The QPSK modulator consists of carrier source to produce a periodic pulse signal (carrier signal ), fed to a carrier phase shifter; which shift the input carrier into four different phase signals (0Â°, 90Â°, 180Â°, 270Â°) interfaced to multiplexer. While the data_in is fed to data mapping to generate I and Q signals to influence the four phase different carries. The output is selected by multiplexer which provides digital QPSK signal, this signal filtered with analog filter before transmitted to pass fundamental frequency and eliminates the higher frequencies associated with the square signal. The architecture block diagram of QPSK modulator is shown in Figure 1.
Data_ Map Module
Figure 1. The block diagram for the proposed QPSK Modulator
4. Simulation Results
A. VHDL programming code simulation
The proposed modulator programmed with the VHDL language for modeling, design and analysis of the proposed QPSK modulator. The simulated result of this modulator is presented in Fig.6. This demonstrates the output signals waveforms indicating the transitions (180Â°, 270Â°) of the carrier signal influence by input data signal. The carrier frequency 5 MHz was generated from the local clock signal The data signal was reduced to 5KHz by a frequency divider then fed into a random PN sequence generator. The modulator is implemented and the generated VHDL "Behavioral" RTL of the QPSK modulator is illustrated in Fig. 4
Figure 2. Top level RTL schematic for
Figure 3. RTL schematic for QPSK
B.VHDL Simulation results and discussion
In this part of paper, we provide the simulation results for testing the VHDL code modulator. Figure 6 and figure 7 shows results at rising and falling edge of Input signal.clk_2 is carreir signal ,clk_3 is clock pulse to control the data rate of input signal,data_in is input signal and data_out is output signal.
Figure 4. Output at rising edge
Pulse duration for clk_2 and clk_3 is 200ns and the pulse duration for data_out is 400ns.
Following are the different possibilities of phase variation:
1. When data_in is 00 the phase of modulated signal is 0Â°.
2. When data_in is 01 the phase of modulated signal is 90Â°.
3. When data_in is 10 the phase of modulated signal is 180Â°.
4. When data_in is 11 the phase of modulated signal is 270Â°.
Figure 5. Output at falling edge
The signal passes as digital QPSK through the passive LPF for harmonics separation.
C. Filter Implementation and MATLAB simulation Results
In wireless transmission we cannot transmit the digital signal directly without harmonics separation. The output of the multiplier is producing a QPSK digital signal "square signal" form. It is essential to use a filter to complete the process for the modulator "off-chip". We designed an analog passive filter for this purpose as it has zero power consumption. Two types of filters were
investigated Low pass Filter (Wavelet LPF) and Band Pass Filter (second order Butterworth BPF) to eliminates the harmonics from the QPSK digital signal.
(I).Butterworth BPF simulation
Our prototype analog filter selected is a Butterworth 2nd order, to filter the input QPSK digital signal. The simulation results for the output of Second order band pass butterworth filtere is shown in figure 2. It is the power spectral density of filtered modulated signal, as it is evident from the figure that the dc component and high frequency components are eliminated from the filtered signal.There are two lobes on either side of origin due to abrupt changes in the carrier phase.
Figure 6. Butterworth Filter simulation with MATLAB
(II).Wavelet LPF simulation
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Figure 3 shows the wavelet Energy spectrum for the result of the Haar transform or the frequency plot using wavelet packet frequency analysis. The peaks are formed by the filtered signal at the resolution of the level basis. By further reducing the time regions, all the frequency bands become compressed into a smaller time region. Multiple frequency bands become associated with a given time region.
Figure 7. The Wavelet Filter simulation with MATLAB
========* Final Report *========
RTL Top Level Output File Name: qpsk.ngr
Top Level Output File Name: qpsk
Output Format: NGC
Optimization Goal: Speed
Keep Hierarchy: YES
Target Technology: Automotive 9500XL
Macro Preserve: YES
XOR Preserve: YES
Clock Enable: YES
wysiwyg : NO
# IOs: 4
# BELS: 45
# AND2: 17
# AND3: 1
# GND: 1
# INV: 17
# OR2: 8
# XOR2: 1
# Flip-flops/Latches: 7
# FD: 5
# FDCE: 2
# IO Buffers: 4
# IBUF: 3
# OBUF: 1
We implemented a new simple direct QPSK digital modulator model in MATLAB simulation software. It has been successfully designed with VHDL programming code. The modulator generates QPSK signal directly from binary digital data. For test purpose it was generated with VHDL code inside the CPLD/FPGA, mapped for I / Q to control the carrier signal using VHDL multiplexer code. The output producing modulated digital signal, filtered to transmit through designed analog filters. The carrier frequency is 5MHz and input frequency is 500KHz.The filter is main key in the design, eventually we designed and simulated for optimum passive filter. The simulation results are presented for second order Butterworth band pass filter and wavelet (low pass) filter.
In this thesis implementation of digital QPSK Modulator is done on XILINX 11.1i.The results are verified by test bench generated by the FPGA. Then the Analog filter is simulated by using MATLAB 7.5
It can be concluded that the designed RTL model for QPSK Modulator is accurate and can work for real time applications.