Identification And Formulation Of Steganography And Crytopgraphy Computer Science Essay

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Steganography is the study of techniques that hide the existence of a message in the primary message where intruder cannot suspect the existence of hidden message. The primary message is referred to as carrier signal and the secondary message is referred to as payload signal. These are sometimes also called as carrier message and payload message. It also offers mechanisms for providing confidentiality and deniability and should be concerned that both requirements can be satisfied solely through cryptographic means. [8]

Audio steganography is an art and science of writing hidden messages. Audio steganography can be achieved using various techniques. In this project, for audio steganography, we are using a process of modifying the Least Significant Bit of audio files. By modifying the LSB of an sample audio file, only minor changes may occur in the sound of which, most of them cannot be differentiated by the human ear.

In this project, we discuss about the audio steganography using LSB coding principle. The text message is sent in the form of audio file and the message is encoded using Triple DES encryption algorithm. The message to be encoded or decoded is stored in register file . We use linear feedback shift registers in this project where the output of some specified inputs is fed back as a input to the register. A Serial peripheral interface is used as a mediator to read or write to the register from an external system.

1.1 Identification and formulation of the problem

We have many methods of audio steganography to embed the text message in cover audio file. The main job is to send the message to a receiver by hiding the existence of the message[1].

Digital Steganography is an art of inconspicuously hiding data within another data i.e.,.hiding a message in an particular carrier (such as audio file or image). The carrier can then be sent to a receiver without anyone else knowing that it contains a hidden message.

1. Cannot provide more security

2. Audio file cannot be reusable.

In this project, the interface we are using is very user friendly where user specifies the required inputs(such as audio, text). The user can open or save the output of a particular function at a particular time after embedding. The user can work accordingly as he desires. In the context of security, an intruder can be prevented by assigning the software password facility. To obtain an extra security in extracting the data embedded, a key has to be used while embedding and extracting message.[1]

1. Reuse the audio file.

2. More security provided.

3. We cannot identify message is presented or not in the carrier audio file.

In this project, the text of a message will be encoded within a raw digital audio stream. The key idea of steganography is to hide information in such a way that the presence of the message is undetectable.

We plan to implement a steganography scheme where one of the four lowest bits of each chunk of digital audio is used to hide one bit of the message. This bit will be chosen by a PRNG which generates a series of 2-bit random numbers. These will be used by the steganography encoder to choose which bit of each chunk of audio will be used. During decoding, the pseudo random number generator will be fed the same seed that was used during encoding, thereby producing the same sequence of random numbers and selecting the bits that the message is hidden in.

1.2 Block Diagram

This architecture consists of various sub-assemblies as shown in the above Figureure .It consists of five stages they are stego codec, prng, des3 crypt, register file and SPI interface.

Stegocodec is encode or decode unit. This device will take raw digital audio stream and hides data.

Figure 1. Schematic diagram of Data Path [16]

A hardware pseudo random number generator (PRNG) is designed to determine the particular position of lower order bits of a digital sample audio that is used to store encoded message(one bit).


The register file is used to store the message to be encoded in the audio file. In decode mode, it stores the decoded message.

A SPI interface provides a way to read and write to the register file from an external system.



2.1 Overview of Audio Steganography

Figure 2. Audio Steganography Overview [8]

Create an encrypted audio steganography (information hiding) device.

Store a DES-encrypted message into an audio stream.

Resultant audio stream should have no detectable changes from original.

Allow encrypting/encoding as well as decoding/decrypting.

Public-key encrypted message subtly stored within a seemingly benign audio signal.

To implement this, the design components required are

Stego Codec

Triple Data Encryption Standard

Pseudo Random Number Generator

Register File

Serial Peripheral Interface (SPI)

2.2 Stego Codec

A Codec is a device or computer program which encodes or decodes the digital data (stream or signal). The word "Codec" has been generated by blending of two or more words of "Composer and Decomposer" or "Coder and Decoder". Codecs are used to convert analog audio to digital audio and vice versa (digital sound back to audio) where compression is not involved.

Stego Codec is used for encoding or decoding the audio file that is MP3 audio from analog stream to digital stream. The device will take a raw digital audio stream and hide data within it. For example, an ASCII to encoded message.

The encoded data is send to the PRNG for the PRNG seed and then routed to the Triple DES for the keying purpose.

2.3 Pseudorandom Number Generator

A random number generator is a physical device designed to generate a sequence of numbers (or symbols) without any specific pattern (appears random) [14].These generators are mostly used in cryptography as the seed is secret. Automatically, Sender and receiver can generate the same set of numbers to use.

PRNG is an algorithm designed to generate a sequence of numbers which specifies the properties of random numbers. Initially, a small set of values are used tp determine the state of PRNG and sequence may not be truly random. The pseudo random numbers play an important role in procedural generation and data hiding. The random numbers can also be generated using hardware RNG. Some of the major algorithms for generating such random numbers are Linear Congruential Generators, Lagged Fibonacci Generators, Linear Feedback Shift Registers and Feedback with carry shift registers [14] .


Generally, the sequences produced by a pseudorandom generator algorithm are uniformly distributed by several tests which results a question that exists between theoretical and practical cryptography, such a way to differentiate the output of a high quality random number from a truly appeared random sequence without having a knowledge of the algorithm used and the initialized state. The security of these algorithms lies in the assumption that it is infeasible to differentiate between the use of a suitable random number generator and true random sequence. Here, Linear Feedback Shift Register are used to generate pseudo random numbers [7].

Linear Feedback Shift Register (LFSR):

A LFSR is a sequential shift register consisting of a combinational logic that causes pseudo-randomly cycle through a binary values sequence. The LFSR can be used in digital systems design in multiple ways [6].

Applications included are Data Encryption/Decryption, Data Compression, Wireless Communications, Scrambler/Descrambler, Pseudo-random Number Generation (PN), Digital Signal Processing, Data Integrity Checksums, Optimized Counters, Built-in Self Test (BIST).

An LFSR when clocked, advances the signal from one bit to the next most-significant bit through the register (Figure 3). Some of the outputs forms the feedback and are combined with exclusive-OR operation [9] .

A LFSR can be designed by performing exclusive-OR operation on the obtained outputs of two or more of the flip-flops together and the output are fed back to the input of one of the flip-flops as shown in Figure 4[9].

A linear feedback shift register (LFSR) is a register whose input bit is a linear function of its previous state [6].

Figure.3 Three Bit Shift Register [9]

Figure.4 Linear Feed Back Shift Register [9]

Register with definite possible states should enter a repeating cycles. However, an LFSR with a well-chosen feedback function results a sequence of bits that appears randomly [9].

Shift Register:

The LFSR consist of a Shift Register and the Feedback Function. A shift register shifts its contents to the adjacent positions within a register. Furthermore, the position at the other end is always left blank unless there is some new content that needs to be changed in the registry. The shift register always contains binary data [6].

Figure.5 Shift Register [6]

Feedback Register:

By definition, the values of selected bits are set before the log is recorded and the results of the evaluation function is inserted into the shift register during the quarter, to fill the seat being empty as a result of developments [9].

Table 1 shows the output para a 3-bit input XOR function. The positions selected in section use the comments are "taps." List of cranes known as "tap sequence." Listen

 Input A

Input B

Input C

XOR Output

































Read phonetically

Table 1 XOR Function [9]


The bit positions that cause disturbance to the next states are called "Taps".

Tap Sequences:

A LFSR is part of a class of devices called state machines. The state of an n-bit LFSR can be any length of 2n different values. The greatest possible condition for this type of LFSR is 2n - 1 (all values less than zero state)[11].The period of a LFSR is defined as the length of the stream before it repeats. Period, as the state space, is related to the sequence of the valve and the initial value. In fact, the period is equal to the size of the state space.

Figure. 6 LFSR 4-Bit Tap Sequence [9]

Table 2 is a listing of the internal states and the output bit stream of a 4-bit LFSR with tap sequence [4, 1].

Register States


Bit 1 (Tap)

Bit 2

Bit 3

Bit 4 (Tap)

Output Stream

















































































Table 2 4-Bit LFSR [4, 1] States and Output [9]

Pseudo Random Pattern Generator:

Shift registers with linear feedback generators are considered to be very good pseudo-random generators. When the outputs of flip-flops are loaded with an initial value (something other than 0, which would cause the LFSR to produce all models of 0) in the LFSR register, will generate a pseudo-random 1 and 0. Note that the signal is only necessary to generate test patterns is the clock.

In our proposed pseudo random numbers are used to ensure secrecy text. It ensures safety by determining the low-order bits of a piece of digital audio, which will be saved as a bit of coded messages.

A hardware PRNG is used to determine which low-order bits of a digital audio is used to store one bit of coded message. When decoding, the unit will be supplied with the same seed PRNG used in coding. Therefore, exactly the same sequence of random numbers are reproduced and the bits of the message can be extracted.

PRNG is conducted several times in the software. The motivation for hardware implementation is its relative simplicity (eg, a shift register of 32 bits and one to four gates XOR) that allow easy integration into our SoC solutions.

Our base system uses a 32-bit seed for the PRNG. As one of the four low order bits of each piece of digital audio has been changed, a number of random bits of 2 should be generated from this seed of 32 bits.

A method for generating pseudo-random numbers in hardware is the use of a shift register with linear feedback (LFSR). This is a shift register to the desired width with one or more specific XOR gates "touch" points along the chain of pseudo-random. LFSR have been investigated in the fields of mathematics and random number generation, and exploring ways to maximize the randomness of the output. On the other hand, suffer from the problem to be 100% reliable, once the seed is known. One of the keys to tackle this problem is to ensure that no perceptible change bits in the audio stream, so that the seed can be deduced from the sequence of bits changed.

Least Significant Bit Coding:

A least significant bit (LSB) encoding the easiest way to enter information into digital audio files. LSB makes a lot of data to be encrypted, preferably at least significant bit of each sampling point with a binary. The following diagram illustrates how the message 'HEY' is encoded in a 16-bit CD quality sample using the LSB method:

To extract the secret message encoded LSB target file should have information about the sample rates that were used during the integration process. In general, the secret message length is always less than the number of samples containing the secret message and let the receiver know the same thing. One technique consists of LSB encoding from the beginning of the file until the message is that the layer and leave the rest unchanged samples to create a security problem. However, the statistics are different for the two parts of the audio file [12].

Diagram of LSB coding process

Figure.7 LSB Coding [10]

One way to address these issues is to complete the secret message with a few random bits, so that the entire file has the same number of samples. But now the integration process is reflected in the evolution of several samples of the transmission required, which increases the probability of extracting the secret message by an attacker.

A more sophisticated approach is the use of a pseudo-random generator to spread the message about the audio file at random [12].

One popular approach is to use the random interval method. In this, secret key is owned by the sender that a seed is used as a generator of pseudo-random sequences to create a random sample of indices. The receiver also has access to the secret key and knowledge of the sequence generator of pseudo-random sample random clues to reconstruct the receiving end [12].

2.4 Triple Data Encryption (DES3)

Data Encryption (DES):.

A DES key consists of 64 binary digits 0 or 1 ,of which , 8 bits, which are used by the algorithm can be used for parity or error detection [17].

DES is considered insecure for many applications, such as the size of 56-bit key is too small. Even if it's feasible to mount in practice, some theoretical analysis demonstrate the weakness of the encryption algorithm. In practice, more secure algorithm is used as Triple DES


Read phonetically

The Feistel Function Of DES :

1. Expansion:

32 bit half block are expanded to 48 bits using a method called Expansion Permutation that results 6 bit pieces with a total no.of eight.

2. Key mixing:

The obtained result is operated using XOR function. Sixteen 48-bit subkeys, one for every round are derived from the main key.

. C:\Documents and Settings\Administrator\Desktop\Data_Encryption_Standard_InfoBox_Diagram.png

Figure.8 The Feistel function (F function) of DES [17]

3. Substitution:

The block is divided into eight 6 bit before processing by substitution boxes (S-boxes) after key mixing.

4. Permutation:

Using fixed permutations, outputs are rearranged by fixed permutation method. The above design supports expansion of S-box output bits in next round.


The Figure.9 explains the key schedule for encryption

C:\Documents and Settings\Administrator\Desktop\250px-DES-key-schedule.png

Figure.9 Key Schedule of DES [17]

Initially, the 56-bit key top 64 are selected by Permuted choice 1 (PC-1) and the other eight bits are used as parity check bits. The 56 bits are then divided into two halves of 28 bits, each half separately. Rotations (denoted by "<<<") describes how different set of bits used in all shades and all the bits that are used in about 14 subkeys.

The 28 bits are transmitted the same to all mailboxes of rotation [17].

To improve security Triple Data Encryption (DES3) is used because it uses three buttons for security. In key is used and does not provide greater security and is fragile. Due to this drawback of the Triple Data Encryption Standard DES is used to improve security.

Triple Data Encryption (DES3):

It is named DES3 as it applies encryption algorithm (DES) three times for each block of data. The Triple Data Encryption Algorithm (TDEA) is commonly called Triple DES. Triple DES was the answer to numerous shortcomings of DES. Since Triple DES is based on the DES algorithm, it is very easy to modify existing software to use Triple DES [18].

It has an advantage of greater reliability and key length that eliminates shortcut attacks that can be used to reduce the amount of time it takes to break DES. However, this more powerful version of DES cannot be strong enough to protect data for so long.

Triple DES is simply another mode of operation and it takes three 64-bit keys with a key length of 192 bits in general. While using In Private Encryptor, simply type in the entire 192-bit (24 character) key rather than entering each of the three keys individually.

Figure.10 Triple DES Encryption Operations [18]

Modes of Operation:

Triple ECB (Electronic Code Book)

The simplest mode of encryption is the electronic dictionary (ECB) mode. The message is divided into blocks and each block is encrypted separately. The disadvantage of this method is that the blocks are identical in clear ciphertext blocks are identical: thus, does not hide data patterns well. In a sense, does not provide message confidentiality seriously, and is not recommended for use in cryptographic protocols at all. A striking example of the extent to which the ECB may leave the data models in plaintext in the ciphertext shown below, a pixel-level version of the left image is encrypted in ECB mode to create the image of the center, compared to a non-BCE image on the right.

Figure. 11 ECB mode Encryption [18]

Triple CBC (Cipher Block Chaining)

This method is very similar to standard mode DES-CBC. In Triple ECB, the effective key length is 168-bit keys are used in the same manner as described above, but the nature of CBC chaining mode are also used. The first 64-bit key that acts as the initialization vector for the DES and Triple ECB then executed for a single 64-bit block of plaintext. The resulting ciphertext is used to XOR with the plaintext block next to quantify, and repeat the procedure. This method adds an extra security with Triple Des and therefore more secure than Triple ECB [18].

Figure. 12 CBC mode of Encryption


Encryption: Triple DES uses a "key bundle" comprising of three DES keys each 64 bits, K1, K2 and K3, each of 56 bits (excluding parity bits). The encryption algorithm is:

Ciphertext = EK1 (DK2 (EK3 (plaintext)))

Firstly, the DES key K1 is encrypted and then key K2 is decrypted and following key K3 is encrypted. First encryption then decryption and encryption is done for strong security.

Decryption: It is the reverse process of encryption

Plaintext = DK3 (EK2 (DK1 (ciphertext)))

Firstly, the DES key K1 is decrypted, then key K2 is encrypted and following key K3 is decrypted. First decryption then encryption and decryption for strong security.

Each triple encryption encrypts one block of 64 bits of data. In each case, the middle operation will be the reverse of the first and last operation, through which strength of an algorithm improves when using keying option 2, and provides backward compatibility with DES with keying option 3.[18]

Keying Options:

The standards define three keying options:

Keying option 1: All three keys are independent.

Keying option 2: K1 and K2 are independent and K3=K1.

Keying option 3: All three keys are identical, i.e., K1=K2=K3.

Keying Option 1 is the strongest, with 3*56=168 independent key bits. It provides the strong security. It is impossible for the intruder to break the key because each key is independent of each 64 bits i.e., 56 key bits plus 8 parity bits.[18]. Keying option 2 provides less security as 2 keys are dependent. Keying option 3 works same as DES [18].


Generally, Triple DES with three independent keys (keying option 1) has a key length of 168 bits (three 56-bit DES keys), but it provides only 112 bits due to the meet-in-the-middle attack of the effective security. Keying option 2 basically decreases the key size to 112 bits. In the foreseeable context, Triple DES is considered to be an excellent and highly reliable choice for high sensible information security [18].

The Figure explains that the keys used during encryption are the same keys that must be used at the decryption side i.e. same key must be used by transmitter at transmission side and also by receiver at the receiving end. Such that intruder cannot detect it .Data can be only recovered from cipher by using exactly the same key used to encipher it [18].

Figure.13 Key Usage [18]

Public and Private Keys:

Generation of Public and Private Keys:

Two keys namely public key and private key are generated in the above diagram. To begin generation of an acceptable pair of keys which are suitable for use by an asymmetric key algorithm, a random number is used

C:\Documents and Settings\Administrator\Desktop\250px-Public-key-crypto-1.svg.png

Figure.14 Block Diagram for Generation of Public and Private Keys [19]

. C:\Documents and Settings\Administrator\Desktop\250px-Public_key_encryption.svg.png

Figure.13 Asymmetric Key Encryption [19]

In an asymmetric key encryption scheme, anyone can encrypt messages using the public key, but only the holder of the paired private key can decrypt. Security depends on the secrecy of that private key.

C:\Documents and Settings\Administrator\Desktop\250px-Public_key_signing.svg.png

Figure.14 Private Key [19]

The private key is used to sign a message; but anyone using public key can check the signature. Validity depends on private key security.

2.5 Register File

A register file is an array consisting of processor registers in a central processing unit (CPU). The set of registers used to stage functional units on the chip and data between memory are defined using Instruction Set Architecture (ISA) [6].


Generally, layout convention which acts as a simple array is vertically read out. Horizontally running single word line causes a row of bit cells to transfer their data on bit lines that runs vertically. Sense amplifiers which are generally used at the bottom are used to convert low-swing read bit lines to full-swing logic levels by convention.

Register files consists of only one bit line per bit of width per read port, one word line per entry per port and two bit lines per bit of width per write port. Each bit cell is associated with the supplies Vss and Vdd. Therefore, the area of wire pitch increases as the square of the transistor area and the number of ports increases linearly.

Figure.15 Register Layout [11]

At a particular instance, we can expect a smaller or faster to get multiple redundant register files with less no.of read ports than a single register file with all the read ports. In this project, register file with 2 read ports and one write port are used for ALU ops.

Figure.17 Register file with two read ports and one write port [9]

Dynamic Register:

A high performance dynamic regfile with one write port and two read ports is used in this project. This design supports both read and write access in the same cycle. The read bitlines are precharged high during the first half of the cycle and the write bitlines are driven at the same cycle. During first half of the cycle, registers are written while during the second half of the cycle, the read data is sensed. This process avoids a bypass path of the five-stage pipeline microprocessor from the write-back stage as shown in Figure.18.Also, the energy dissipation of the read and write bit lines is observed that dominates the consumption of regfile.

Figure.19 Register File Storage [9]

The storage cell is nothing but a conventional static RAM cell [18]. The column circuitry which consists of a clocked inverter sense amplifier that provide faster read port output sensing controls the data buffering, read bit line precharges and write drive.

Register Map

The internal register file is a 32-bit word asynchronous memory with 64-word. The register map can be given as follows:

STATUS (00h) - Configuration bits for the BUNI5590

PRNGSEED (01h) - PRNG 32-bit seed

DESKEY1 (02h, 03h) - 1st round 64-bit DES crypt key (high word in 02h)

DESKEY2 (04h, 05h) - 2nd round 64-bit DES crypt key (high word in 04h)

DESKEY3 (06h, 07h) - 3rd round 64-bit DES crypt key (high word in 06h)

The STATUS register has fields as follows:













Table 3 Register Map [9]

Upon device power-up, the external system must configure the STATUS register (at address 0) with the following parameters :

MLENGTH - Message length (32-bit words)

MINMAG - Minimum Sampling Magnitude

MINMAGEN - Minimum Magnitude Enable


The Serial Peripheral Interface Bus is a synchronous serial data link standard that operates in full duplex mode. Devices communicate in master or slave mode where the master device initiates the data frame.

Interface :

The SPI bus mainly specifies about four logic signals.













Figure.20 Block Diagram of SPI [15]

SCLK - Serial Clock (output from master)

MOSI/SIMO - Master Output Slave Input (output from master)

MISO/SOMI - Master Input Slave Output (output from slave)

SS - Slave Select (output from master; active low)

Alternative naming conventions are also widely used:

SCK, CLK - Serial Clock (output from master)

SDI, DI, SI - Serial Data In, Data In, Serial In

SDO, DO, SO - Serial Data Out, Data Out, Serial Out

nCS, CS, CSB, nSS, STE - Chip Select, Slave Transmit Enable (active low; output from master)


Due to tri-state outputs of slave devices, MISO signal becomes disconnected (high impedence) when device is not selected. While SPI bus segments are not shared when used with devices without tri-state outputs and that slave acts as a mediator and also its chip select may be activated [20].

Data Transmission:

Initializing the transmission, the clock should be configured by a master using a frequency less than or equal to the maximum frequency the slave device that commonly supports the frequency range of 1-70 MHz.

Figure.21 Data Transmission In SPI [20]

The slave select is made low for the chip desired using master. During analog to digital conversion, if a waiting period is required, master should wait for that period duration before issuing the clock cycles .

At every SPI clock cycle duration, data transmission occurs in full duplex :

The master sends a bit and the slave reads it from the same MOSI line

The slave sends a bit and the master reads it from the same MISO line

It is not mandatory to operate all transmissions required in de way as described above.

Transmissions always involve two shift registers (one in master and the other in slave)of defined word size connected in a ring. MSB is shifted first while shifting the data and a new LSB is shifted into the same register. Once the data shifting in a register is completely done , slave and master exchange register values. Every value is used by device to do work such as writing to a memory. If no more data to be exchanged is available, registers are reloaded with new data and the same process repeats and transmissions may need any no.of clock cycles. It deselects slave and master stops toggling the clock [20].

Clock polarity and phase :

A timing diagram below shows the clock polarity and phase

Figure.22 Clock Polarities and Phase [21]

Besides configuring the clock polarity and phase to the corresponding data, it also sets clock frequency.

At CPOL=0, the base value of the clock is zero

For CPHA=0, data changes on a high to low clock transition i.e., falling and data is read on the clock's low to high transition i.e.,rising edge. [21]. While data changes at a rising edge and data is read on the clock's falling edge for CPHA=1.

At CPOL=1, the base value of the clock is one (inversion of CPOL=0)

For CPHA=0, data changes on a rising edge and data are read on clock's falling edge. While data are changed on a falling edge and data is read on clock's rising edge [21] for CPHA=1

CPHA=0 gives leading clock edge and CPHA=1 gives a trailing clock edga without bothering about the clock edge polarities. Data must be maintained stable for a half cycle before the first clock cycle when CPHA=0 and for all modes of CPOL and

CPHA, the initial clock value should be maintained stable before the chip select line goes up. Usually, the MISO and MOSI signals are stable for the half cycle until the next clock transition occurs at their reception points [21].

The timing of a standard 4 wire SPI interface, when CPOL=0, CPHA=0 is described as follows


Figure.23 SPI Timing Diagram [21]



3.1 Design Flow

Figure.24 Design Flow of Audio Steganography


BUNI5590 steganography audio line is a device configured to hide any message on a digital audio stream. Works on the principles of change of the sample LSB, where one of the LSB 4 of a sample of 16 bits is changed with each successive bit of the message should be encapsulated. The device also includes a configurable set of minimum size, which defines the minimum size required before an audio sample is changed.


Read phonetically

The configured device using a serial interface with 4 wired and that runs in a slave mode. Internally it has 32 bit register file with 56 words for a message and a total of 224 bytes for message output.

Messages hidden in the audio file are encrypted using Triple DES using the keys in register file which are well defined to provide an extra security. PRNG is used to modify the bits within a unit. The three DES keys along with the seed and the minimum magnitude setting are mandatory to extract a message hidden in a register on the receiving end.

3.2 Operation

16 bit digital audio stream has a fine resolution that even if corruption occurs at LSB's of any audio sample, it is imperceptible to the human ear. If and only if the sample exceeds the minimum magnitude, the stego design cannot modify one of the LSB. For example, If the minimum magnitude value is 128, the resulting magnitude of a sample never differ by more than 2^3/128 = 6.25% of its original value. Generally, minimum magnitude with higher values are choosen so as to decrease the maximum distortion percentage.

Mode of Operation:

The device Audio Steganographer used in this project consists of audio input, an audio output and a SPI read or write interface. In encode mode - the selected bit is modified with the next bit of the message which is user defined. This encryption is done using triple DES method. In decode mode - selected bit is used as the next bit of encrypted data in the audio stream. The result obtained has 64 bit chunks, the decryption is done with triple DES scheme and stored in a register file.

As the configured device is a standard 4 wire SPI, the message length, operating mode of a device , minimum sample magnitude are defined using the STATUS register at address "o". Other parameters such as crypto keys, PRNG seed are defined using SPI.

The PRNG register initialized with 32 bit seed acts as an PRN generator. The message is stored in MESSSAGE registers. Once the SPI is initialized, the RST flag should be asserted and de- asserted and the clock should be run for N cycles (NUMCYCLES) with SCLK_IN low before the device is ready for operation. This period of initialization allows to initialize the PRNG, the CODEC module to load the PRNG seed and also to load the DES keys from the register file.

Encode Mode:

The audio stream is sent to a chip using the bit clock BCLK_IN, sampling clock SCLK_IN, and the audio stream AUD_IN when DEC flag of the STATUS register set to 0 is initialized. The audio stream is modified and provided on the output lines BCLK_OUT, SCLK_OUT, and AUD_OUT. Activity on SCLK_IN can be observed when stego writes a message into the stream continuously as long as the data is provided. The BLCK_OUT is 180 degrees out of phase with input.

Decode Mode:

This mode can be achieved by setting Dec flag in the STATUS register. By intializing the module, the audio stream with hidden data can be sent to stego via SCLK_IN, BCLK_IN and AUD_IN lines. Using the same random number sequence that is used in encode mode, audio data may be extracted. Decryption is done using the 3DES keys configured and stored into a register file using serial peripheral interface.

Audio Interface:


Figure.25 Audio Interface[21]

Above Figure explains the general format of audio interface. The nominal sampling frequency of audio interface is 32kHz along with a 2.048MHz bit clock. The falling edge of bit clock and sample clock should always be in sync. BCLK_OUT and BCLK_IN runs with the same frequency but with 180 degrees out of phase.



4.1 Simulation

Encode Mode :

Figure.26 Simulation of encode 1

Figure.27 Simulation of encode 2

Decode mode:

Figure. 28 Simulation of Decode 1

Figure.29 Simulation of Decode 2

Figure. 30 Simulation of PRNG

Figure. 31 Simulation of Register File

4.2 RTL Schematics

Figure. 32 RTL Schematic of Stegocodec

Figure. 33 RTL Schematic of PRNG

Figure. 34 RTL Schematic of Register File



5.1 Conclusion

In this project, a lossless audio steganography is designed using LSB coding technique by altering the lower chunk bits and embedded the secret text into the audio file. By using Pseudo Random Number Generator (PRNG) and Triples DES, security has been provided to the secret text. The encoding and Decoding is processed using CODEC. The cipher text is obtained from plain text using triple DES and vice versa. The simulations are obtained for CODEC, PRNG, REGISTER FILE, SPI using ISIM Simulator Log with a verilog code .

5.2 Future Scope

The future work would be towards hiding text into digital data such as video files.


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[2] D-artz-IEEE Internet Computing 2001, "Digital Steganography: Hiding data within Data. IEEE internet computing magazine". Accessed on 09-25-2010

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